A copy of arch/arm/include/asm/arch-axg/regs.h in the amlogic U-Boot tree.
1 /*
2 * Copyright (C) 2017 Amlogic, Inc. All rights reserved.
3 * *
4 This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 * *
9 This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 * *
14 You should have received a copy of the GNU General Public License along
15 * with this program; if not, write to the Free Software Foundation, Inc.,
16 * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
17 * *
18 Description:
19 */
20
21 // ----------------------------------------------------------------------
22 // regs.h header
23 //
24 // bus base define, update manually
25 //
26 // ----------------------------------------------------------------------
27 //
28 #ifndef _BASE_REGISTER
29 #define _BASE_REGISTER
30 #define REG_BASE_AOBUS (0xFF800000L)
31 #define REG_BASE_PERIPHS (0xFF634000L)
32 #define REG_BASE_CBUS (0xFFD00000L)
33 #define REG_BASE_HIU (0xFF63C000L)
34 #define REG_BASE_VCBUS (0xFF900000L)
35 #define DMC_REG_BASE (0xFF638000L)
36 #define REG_BASE_DSI_HOST (0xFFD00000L)/* 0xFFD06000L*/
37
38 #endif /*_BASE_REGISTER*/
39
40
41 #ifndef REG_OTHERS
42 #define REG_OTHERS
43 /* other regs */
44 #define SPI_START_ADDR 0xFB000000
45 #define P_SPI_START_ADDR (volatile unsigned int *)0xFB000000
46
47 /* name changed, need convert */
48 #define AO_RTI_PIN_MUX_REG AO_RTI_PINMUX_REG0
49 #define SEC_AO_RTI_PIN_MUX_REG SEC_AO_RTI_PINMUX_REG0
50 #define P_AO_RTI_PIN_MUX_REG P_AO_RTI_PINMUX_REG0
51 #define AO_RTI_PIN_MUX_REG2 AO_RTI_PINMUX_REG1
52 #define SEC_AO_RTI_PIN_MUX_REG2 SEC_AO_RTI_PINMUX_REG1
53 #define P_AO_RTI_PIN_MUX_REG2 P_AO_RTI_PINMUX_REG1
54
55 #endif /*REG_OTHERS*/
56
57 // ----------------------------------------------------------------------
58 // This file is automatically generated for the SW team:
59 //
60 // From three scripts:./create_headers_from_register_map_h.pl, create_headers_from_secure_apb4_h.pl, create_headers_for_mmc_register_map_h.pl
61 //
62 // DO NOT EDIT!!!!!
63 // ----------------------------------------------------------------------
64 //
65
66 #ifndef REGS_H
67 #define REGS_H
68
69
70 //
71 // Reading file: ./register_map.h
72 //
73 // synopsys translate_off
74 // synopsys translate_on
75 //
76 // Reading file: periphs_reg.h
77 //
78 // $periphs/rtl/periphs_core register defines for the
79 // APB bus
80 // ------------------------------------------------------------------------------------
81 // -----------------------------------------------
82 // CBUS_BASE: UART0_CBUS_BASE = 0x90
83 // -----------------------------------------------
84 #define UART0_WFIFO (0x9000)
85 #define P_UART0_WFIFO (volatile uint32_t *)((0x9000 << 2) + 0xffd00000)
86 #define UART0_RFIFO (0x9001)
87 #define P_UART0_RFIFO (volatile uint32_t *)((0x9001 << 2) + 0xffd00000)
88 #define UART0_CONTROL (0x9002)
89 #define P_UART0_CONTROL (volatile uint32_t *)((0x9002 << 2) + 0xffd00000)
90 #define UART0_STATUS (0x9003)
91 #define P_UART0_STATUS (volatile uint32_t *)((0x9003 << 2) + 0xffd00000)
92 #define UART0_MISC (0x9004)
93 #define P_UART0_MISC (volatile uint32_t *)((0x9004 << 2) + 0xffd00000)
94 #define UART0_REG5 (0x9005)
95 #define P_UART0_REG5 (volatile uint32_t *)((0x9005 << 2) + 0xffd00000)
96 // ------------------------------------------------------------------------------------
97 // -----------------------------------------------
98 // CBUS_BASE: UART1_CBUS_BASE = 0x8c
99 // -----------------------------------------------
100 #define UART1_WFIFO (0x8c00)
101 #define P_UART1_WFIFO (volatile uint32_t *)((0x8c00 << 2) + 0xffd00000)
102 #define UART1_RFIFO (0x8c01)
103 #define P_UART1_RFIFO (volatile uint32_t *)((0x8c01 << 2) + 0xffd00000)
104 #define UART1_CONTROL (0x8c02)
105 #define P_UART1_CONTROL (volatile uint32_t *)((0x8c02 << 2) + 0xffd00000)
106 #define UART1_STATUS (0x8c03)
107 #define P_UART1_STATUS (volatile uint32_t *)((0x8c03 << 2) + 0xffd00000)
108 #define UART1_MISC (0x8c04)
109 #define P_UART1_MISC (volatile uint32_t *)((0x8c04 << 2) + 0xffd00000)
110 #define UART1_REG5 (0x8c05)
111 #define P_UART1_REG5 (volatile uint32_t *)((0x8c05 << 2) + 0xffd00000)
112 // ------------------------------------------------------------------------------------
113 // -----------------------------------------------
114 // CBUS_BASE: I2C_M_0_CBUS_BASE = 0x7c
115 // -----------------------------------------------
116 #define I2C_M_0_CONTROL_REG (0x7c00)
117 #define P_I2C_M_0_CONTROL_REG (volatile uint32_t *)((0x7c00 << 2) + 0xffd00000)
118 #define I2C_M_MANUAL_SDA_I 26
119 #define I2C_M_MANUAL_SCL_I 25
120 #define I2C_M_MANUAL_SDA_O 24
121 #define I2C_M_MANUAL_SCL_O 23
122 #define I2C_M_MANUAL_EN 22
123 #define I2C_M_DELAY_MSB 21
124 #define I2C_M_DELAY_LSB 12
125 #define I2C_M_DATA_CNT_MSB 11
126 #define I2C_M_DATA_CNT_LSB 8
127 #define I2C_M_CURR_TOKEN_MSB 7
128 #define I2C_M_CURR_TOKEN_LSB 4
129 #define I2C_M_ERROR 3
130 #define I2C_M_STATUS 2
131 #define I2C_M_ACK_IGNORE 1
132 #define I2C_M_START 0
133 #define I2C_M_0_SLAVE_ADDR (0x7c01)
134 #define P_I2C_M_0_SLAVE_ADDR (volatile uint32_t *)((0x7c01 << 2) + 0xffd00000)
135 #define I2C_M_0_TOKEN_LIST0 (0x7c02)
136 #define P_I2C_M_0_TOKEN_LIST0 (volatile uint32_t *)((0x7c02 << 2) + 0xffd00000)
137 #define I2C_M_0_TOKEN_LIST1 (0x7c03)
138 #define P_I2C_M_0_TOKEN_LIST1 (volatile uint32_t *)((0x7c03 << 2) + 0xffd00000)
139 #define I2C_M_0_WDATA_REG0 (0x7c04)
140 #define P_I2C_M_0_WDATA_REG0 (volatile uint32_t *)((0x7c04 << 2) + 0xffd00000)
141 #define I2C_M_0_WDATA_REG1 (0x7c05)
142 #define P_I2C_M_0_WDATA_REG1 (volatile uint32_t *)((0x7c05 << 2) + 0xffd00000)
143 #define I2C_M_0_RDATA_REG0 (0x7c06)
144 #define P_I2C_M_0_RDATA_REG0 (volatile uint32_t *)((0x7c06 << 2) + 0xffd00000)
145 #define I2C_M_0_RDATA_REG1 (0x7c07)
146 #define P_I2C_M_0_RDATA_REG1 (volatile uint32_t *)((0x7c07 << 2) + 0xffd00000)
147 #define I2C_M_0_TIMEOUT_TH (0x7c08)
148 #define P_I2C_M_0_TIMEOUT_TH (volatile uint32_t *)((0x7c08 << 2) + 0xffd00000)
149 // -----------------------------------------------
150 // CBUS_BASE: I2C_M_1_CBUS_BASE = 0x78
151 // -----------------------------------------------
152 #define I2C_M_1_CONTROL_REG (0x7800)
153 #define P_I2C_M_1_CONTROL_REG (volatile uint32_t *)((0x7800 << 2) + 0xffd00000)
154 #define I2C_M_1_SLAVE_ADDR (0x7801)
155 #define P_I2C_M_1_SLAVE_ADDR (volatile uint32_t *)((0x7801 << 2) + 0xffd00000)
156 #define I2C_M_1_TOKEN_LIST0 (0x7802)
157 #define P_I2C_M_1_TOKEN_LIST0 (volatile uint32_t *)((0x7802 << 2) + 0xffd00000)
158 #define I2C_M_1_TOKEN_LIST1 (0x7803)
159 #define P_I2C_M_1_TOKEN_LIST1 (volatile uint32_t *)((0x7803 << 2) + 0xffd00000)
160 #define I2C_M_1_WDATA_REG0 (0x7804)
161 #define P_I2C_M_1_WDATA_REG0 (volatile uint32_t *)((0x7804 << 2) + 0xffd00000)
162 #define I2C_M_1_WDATA_REG1 (0x7805)
163 #define P_I2C_M_1_WDATA_REG1 (volatile uint32_t *)((0x7805 << 2) + 0xffd00000)
164 #define I2C_M_1_RDATA_REG0 (0x7806)
165 #define P_I2C_M_1_RDATA_REG0 (volatile uint32_t *)((0x7806 << 2) + 0xffd00000)
166 #define I2C_M_1_RDATA_REG1 (0x7807)
167 #define P_I2C_M_1_RDATA_REG1 (volatile uint32_t *)((0x7807 << 2) + 0xffd00000)
168 #define I2C_M_1_TIMEOUT_TH (0x7808)
169 #define P_I2C_M_1_TIMEOUT_TH (volatile uint32_t *)((0x7808 << 2) + 0xffd00000)
170 // ------------------------------------------------------------------------------------
171 // -----------------------------------------------
172 // CBUS_BASE: I2C_M_2_CBUS_BASE = 0x74
173 // -----------------------------------------------
174 #define I2C_M_2_CONTROL_REG (0x7400)
175 #define P_I2C_M_2_CONTROL_REG (volatile uint32_t *)((0x7400 << 2) + 0xffd00000)
176 #define I2C_M_2_SLAVE_ADDR (0x7401)
177 #define P_I2C_M_2_SLAVE_ADDR (volatile uint32_t *)((0x7401 << 2) + 0xffd00000)
178 #define I2C_M_2_TOKEN_LIST0 (0x7402)
179 #define P_I2C_M_2_TOKEN_LIST0 (volatile uint32_t *)((0x7402 << 2) + 0xffd00000)
180 #define I2C_M_2_TOKEN_LIST1 (0x7403)
181 #define P_I2C_M_2_TOKEN_LIST1 (volatile uint32_t *)((0x7403 << 2) + 0xffd00000)
182 #define I2C_M_2_WDATA_REG0 (0x7404)
183 #define P_I2C_M_2_WDATA_REG0 (volatile uint32_t *)((0x7404 << 2) + 0xffd00000)
184 #define I2C_M_2_WDATA_REG1 (0x7405)
185 #define P_I2C_M_2_WDATA_REG1 (volatile uint32_t *)((0x7405 << 2) + 0xffd00000)
186 #define I2C_M_2_RDATA_REG0 (0x7406)
187 #define P_I2C_M_2_RDATA_REG0 (volatile uint32_t *)((0x7406 << 2) + 0xffd00000)
188 #define I2C_M_2_RDATA_REG1 (0x7407)
189 #define P_I2C_M_2_RDATA_REG1 (volatile uint32_t *)((0x7407 << 2) + 0xffd00000)
190 #define I2C_M_2_TIMEOUT_TH (0x7408)
191 #define P_I2C_M_2_TIMEOUT_TH (volatile uint32_t *)((0x7408 << 2) + 0xffd00000)
192 // ------------------------------------------------------------------------------------
193 // -----------------------------------------------
194 // CBUS_BASE: I2C_M_3_CBUS_BASE = 0x70
195 // -----------------------------------------------
196 #define I2C_M_3_CONTROL_REG (0x7000)
197 #define P_I2C_M_3_CONTROL_REG (volatile uint32_t *)((0x7000 << 2) + 0xffd00000)
198 #define I2C_M_3_SLAVE_ADDR (0x7001)
199 #define P_I2C_M_3_SLAVE_ADDR (volatile uint32_t *)((0x7001 << 2) + 0xffd00000)
200 #define I2C_M_3_TOKEN_LIST0 (0x7002)
201 #define P_I2C_M_3_TOKEN_LIST0 (volatile uint32_t *)((0x7002 << 2) + 0xffd00000)
202 #define I2C_M_3_TOKEN_LIST1 (0x7003)
203 #define P_I2C_M_3_TOKEN_LIST1 (volatile uint32_t *)((0x7003 << 2) + 0xffd00000)
204 #define I2C_M_3_WDATA_REG0 (0x7004)
205 #define P_I2C_M_3_WDATA_REG0 (volatile uint32_t *)((0x7004 << 2) + 0xffd00000)
206 #define I2C_M_3_WDATA_REG1 (0x7005)
207 #define P_I2C_M_3_WDATA_REG1 (volatile uint32_t *)((0x7005 << 2) + 0xffd00000)
208 #define I2C_M_3_RDATA_REG0 (0x7006)
209 #define P_I2C_M_3_RDATA_REG0 (volatile uint32_t *)((0x7006 << 2) + 0xffd00000)
210 #define I2C_M_3_RDATA_REG1 (0x7007)
211 #define P_I2C_M_3_RDATA_REG1 (volatile uint32_t *)((0x7007 << 2) + 0xffd00000)
212 #define I2C_M_3_TIMEOUT_TH (0x7008)
213 #define P_I2C_M_3_TIMEOUT_TH (volatile uint32_t *)((0x7008 << 2) + 0xffd00000)
214 // ------------------------------------------------------------------------------------
215 // -----------------------------------------------
216 // CBUS_BASE: PWM_AB_CBUS_BASE = 0x6c
217 // -----------------------------------------------
218 #define PWM_PWM_A (0x6c00)
219 #define P_PWM_PWM_A (volatile uint32_t *)((0x6c00 << 2) + 0xffd00000)
220 #define PWM_PWM_B (0x6c01)
221 #define P_PWM_PWM_B (volatile uint32_t *)((0x6c01 << 2) + 0xffd00000)
222 #define PWM_MISC_REG_AB (0x6c02)
223 #define P_PWM_MISC_REG_AB (volatile uint32_t *)((0x6c02 << 2) + 0xffd00000)
224 #define PWM_DELTA_SIGMA_AB (0x6c03)
225 #define P_PWM_DELTA_SIGMA_AB (volatile uint32_t *)((0x6c03 << 2) + 0xffd00000)
226 #define PWM_TIME_AB (0x6c04)
227 #define P_PWM_TIME_AB (volatile uint32_t *)((0x6c04 << 2) + 0xffd00000)
228 #define PWM_A2 (0x6c05)
229 #define P_PWM_A2 (volatile uint32_t *)((0x6c05 << 2) + 0xffd00000)
230 #define PWM_B2 (0x6c06)
231 #define P_PWM_B2 (volatile uint32_t *)((0x6c06 << 2) + 0xffd00000)
232 #define PWM_BLINK_AB (0x6c07)
233 #define P_PWM_BLINK_AB (volatile uint32_t *)((0x6c07 << 2) + 0xffd00000)
234 // ------------------------------------------------------------------------------------
235 // -----------------------------------------------
236 // CBUS_BASE: PWM_CD_CBUS_BASE = 0x68
237 // -----------------------------------------------
238 #define PWM_PWM_C (0x6800)
239 #define P_PWM_PWM_C (volatile uint32_t *)((0x6800 << 2) + 0xffd00000)
240 #define PWM_PWM_D (0x6801)
241 #define P_PWM_PWM_D (volatile uint32_t *)((0x6801 << 2) + 0xffd00000)
242 #define PWM_MISC_REG_CD (0x6802)
243 #define P_PWM_MISC_REG_CD (volatile uint32_t *)((0x6802 << 2) + 0xffd00000)
244 #define PWM_DELTA_SIGMA_CD (0x6803)
245 #define P_PWM_DELTA_SIGMA_CD (volatile uint32_t *)((0x6803 << 2) + 0xffd00000)
246 #define PWM_TIME_CD (0x6804)
247 #define P_PWM_TIME_CD (volatile uint32_t *)((0x6804 << 2) + 0xffd00000)
248 #define PWM_C2 (0x6805)
249 #define P_PWM_C2 (volatile uint32_t *)((0x6805 << 2) + 0xffd00000)
250 #define PWM_D2 (0x6806)
251 #define P_PWM_D2 (volatile uint32_t *)((0x6806 << 2) + 0xffd00000)
252 #define PWM_BLINK_CD (0x6807)
253 #define P_PWM_BLINK_CD (volatile uint32_t *)((0x6807 << 2) + 0xffd00000)
254 // ------------------------------------------------------------------------------------
255 // -----------------------------------------------
256 // CBUS_BASE: MSR_CLK_CBUS_BASE = 0x60
257 // -----------------------------------------------
258 #define MSR_CLK_DUTY (0x6000)
259 #define P_MSR_CLK_DUTY (volatile uint32_t *)((0x6000 << 2) + 0xffd00000)
260 #define MSR_CLK_REG0 (0x6001)
261 #define P_MSR_CLK_REG0 (volatile uint32_t *)((0x6001 << 2) + 0xffd00000)
262 #define MSR_CLK_REG1 (0x6002)
263 #define P_MSR_CLK_REG1 (volatile uint32_t *)((0x6002 << 2) + 0xffd00000)
264 #define MSR_CLK_REG2 (0x6003)
265 #define P_MSR_CLK_REG2 (volatile uint32_t *)((0x6003 << 2) + 0xffd00000)
266 #define MSR_CLK_REG3 (0x6004)
267 #define P_MSR_CLK_REG3 (volatile uint32_t *)((0x6004 << 2) + 0xffd00000)
268 #define MSR_CLK_REG4 (0x6005)
269 #define P_MSR_CLK_REG4 (volatile uint32_t *)((0x6005 << 2) + 0xffd00000)
270 #define MSR_CLK_REG5 (0x6006)
271 #define P_MSR_CLK_REG5 (volatile uint32_t *)((0x6006 << 2) + 0xffd00000)
272 // ------------------------------------------------------------------------------------
273 // -----------------------------------------------
274 // CBUS_BASE: SPIFC_CBUS_BASE = 0x50
275 // -----------------------------------------------
276 #define SPI_FLASH_CMD (0x5000)
277 #define P_SPI_FLASH_CMD (volatile uint32_t *)((0x5000 << 2) + 0xffd00000)
278 #define SPI_FLASH_ADDR (0x5001)
279 #define P_SPI_FLASH_ADDR (volatile uint32_t *)((0x5001 << 2) + 0xffd00000)
280 #define SPI_FLASH_CTRL (0x5002)
281 #define P_SPI_FLASH_CTRL (volatile uint32_t *)((0x5002 << 2) + 0xffd00000)
282 #define SPI_FLASH_CTRL1 (0x5003)
283 #define P_SPI_FLASH_CTRL1 (volatile uint32_t *)((0x5003 << 2) + 0xffd00000)
284 #define SPI_FLASH_STATUS (0x5004)
285 #define P_SPI_FLASH_STATUS (volatile uint32_t *)((0x5004 << 2) + 0xffd00000)
286 #define SPI_FLASH_CTRL2 (0x5005)
287 #define P_SPI_FLASH_CTRL2 (volatile uint32_t *)((0x5005 << 2) + 0xffd00000)
288 #define SPI_FLASH_CLOCK (0x5006)
289 #define P_SPI_FLASH_CLOCK (volatile uint32_t *)((0x5006 << 2) + 0xffd00000)
290 #define SPI_FLASH_USER (0x5007)
291 #define P_SPI_FLASH_USER (volatile uint32_t *)((0x5007 << 2) + 0xffd00000)
292 #define SPI_FLASH_USER1 (0x5008)
293 #define P_SPI_FLASH_USER1 (volatile uint32_t *)((0x5008 << 2) + 0xffd00000)
294 #define SPI_FLASH_USER2 (0x5009)
295 #define P_SPI_FLASH_USER2 (volatile uint32_t *)((0x5009 << 2) + 0xffd00000)
296 #define SPI_FLASH_USER3 (0x500a)
297 #define P_SPI_FLASH_USER3 (volatile uint32_t *)((0x500a << 2) + 0xffd00000)
298 #define SPI_FLASH_USER4 (0x500b)
299 #define P_SPI_FLASH_USER4 (volatile uint32_t *)((0x500b << 2) + 0xffd00000)
300 #define SPI_FLASH_SLAVE (0x500c)
301 #define P_SPI_FLASH_SLAVE (volatile uint32_t *)((0x500c << 2) + 0xffd00000)
302 #define SPI_FLASH_SLAVE1 (0x500d)
303 #define P_SPI_FLASH_SLAVE1 (volatile uint32_t *)((0x500d << 2) + 0xffd00000)
304 #define SPI_FLASH_SLAVE2 (0x500e)
305 #define P_SPI_FLASH_SLAVE2 (volatile uint32_t *)((0x500e << 2) + 0xffd00000)
306 #define SPI_FLASH_SLAVE3 (0x500f)
307 #define P_SPI_FLASH_SLAVE3 (volatile uint32_t *)((0x500f << 2) + 0xffd00000)
308 #define SPI_FLASH_C0 (0x5010)
309 #define P_SPI_FLASH_C0 (volatile uint32_t *)((0x5010 << 2) + 0xffd00000)
310 #define SPI_FLASH_C1 (0x5011)
311 #define P_SPI_FLASH_C1 (volatile uint32_t *)((0x5011 << 2) + 0xffd00000)
312 #define SPI_FLASH_C2 (0x5012)
313 #define P_SPI_FLASH_C2 (volatile uint32_t *)((0x5012 << 2) + 0xffd00000)
314 #define SPI_FLASH_C3 (0x5013)
315 #define P_SPI_FLASH_C3 (volatile uint32_t *)((0x5013 << 2) + 0xffd00000)
316 #define SPI_FLASH_C4 (0x5014)
317 #define P_SPI_FLASH_C4 (volatile uint32_t *)((0x5014 << 2) + 0xffd00000)
318 #define SPI_FLASH_C5 (0x5015)
319 #define P_SPI_FLASH_C5 (volatile uint32_t *)((0x5015 << 2) + 0xffd00000)
320 #define SPI_FLASH_C6 (0x5016)
321 #define P_SPI_FLASH_C6 (volatile uint32_t *)((0x5016 << 2) + 0xffd00000)
322 #define SPI_FLASH_C7 (0x5017)
323 #define P_SPI_FLASH_C7 (volatile uint32_t *)((0x5017 << 2) + 0xffd00000)
324 #define SPI_FLASH_B8 (0x5018)
325 #define P_SPI_FLASH_B8 (volatile uint32_t *)((0x5018 << 2) + 0xffd00000)
326 #define SPI_FLASH_B9 (0x5019)
327 #define P_SPI_FLASH_B9 (volatile uint32_t *)((0x5019 << 2) + 0xffd00000)
328 #define SPI_FLASH_B10 (0x501a)
329 #define P_SPI_FLASH_B10 (volatile uint32_t *)((0x501a << 2) + 0xffd00000)
330 #define SPI_FLASH_B11 (0x501b)
331 #define P_SPI_FLASH_B11 (volatile uint32_t *)((0x501b << 2) + 0xffd00000)
332 #define SPI_FLASH_B12 (0x501c)
333 #define P_SPI_FLASH_B12 (volatile uint32_t *)((0x501c << 2) + 0xffd00000)
334 #define SPI_FLASH_B13 (0x501d)
335 #define P_SPI_FLASH_B13 (volatile uint32_t *)((0x501d << 2) + 0xffd00000)
336 #define SPI_FLASH_B14 (0x501e)
337 #define P_SPI_FLASH_B14 (volatile uint32_t *)((0x501e << 2) + 0xffd00000)
338 #define SPI_FLASH_B15 (0x501f)
339 #define P_SPI_FLASH_B15 (volatile uint32_t *)((0x501f << 2) + 0xffd00000)
340 // ------------------------------------------------------------------------------------
341 //spicc 0
342 // -----------------------------------------------
343 // CBUS_BASE: SPICC0_CBUS_BASE = 0x4c
344 // -----------------------------------------------
345 #define SPICC0_RXDATA (0x4c00)
346 #define P_SPICC0_RXDATA (volatile uint32_t *)((0x4c00 << 2) + 0xffd00000)
347 #define SPICC0_TXDATA (0x4c01)
348 #define P_SPICC0_TXDATA (volatile uint32_t *)((0x4c01 << 2) + 0xffd00000)
349 #define SPICC0_CONREG (0x4c02)
350 #define P_SPICC0_CONREG (volatile uint32_t *)((0x4c02 << 2) + 0xffd00000)
351 #define SPICC0_INTREG (0x4c03)
352 #define P_SPICC0_INTREG (volatile uint32_t *)((0x4c03 << 2) + 0xffd00000)
353 #define SPICC0_DMAREG (0x4c04)
354 #define P_SPICC0_DMAREG (volatile uint32_t *)((0x4c04 << 2) + 0xffd00000)
355 #define SPICC0_STATREG (0x4c05)
356 #define P_SPICC0_STATREG (volatile uint32_t *)((0x4c05 << 2) + 0xffd00000)
357 #define SPICC0_PERIODREG (0x4c06)
358 #define P_SPICC0_PERIODREG (volatile uint32_t *)((0x4c06 << 2) + 0xffd00000)
359 #define SPICC0_TESTREG (0x4c07)
360 #define P_SPICC0_TESTREG (volatile uint32_t *)((0x4c07 << 2) + 0xffd00000)
361 #define SPICC0_DRADDR (0x4c08)
362 #define P_SPICC0_DRADDR (volatile uint32_t *)((0x4c08 << 2) + 0xffd00000)
363 #define SPICC0_DWADDR (0x4c09)
364 #define P_SPICC0_DWADDR (volatile uint32_t *)((0x4c09 << 2) + 0xffd00000)
365 #define SPICC0_LD_CNTL0 (0x4c0a)
366 #define P_SPICC0_LD_CNTL0 (volatile uint32_t *)((0x4c0a << 2) + 0xffd00000)
367 #define SPICC0_LD_CNTL1 (0x4c0b)
368 #define P_SPICC0_LD_CNTL1 (volatile uint32_t *)((0x4c0b << 2) + 0xffd00000)
369 #define SPICC0_LD_RADDR (0x4c0c)
370 #define P_SPICC0_LD_RADDR (volatile uint32_t *)((0x4c0c << 2) + 0xffd00000)
371 #define SPICC0_LD_WADDR (0x4c0d)
372 #define P_SPICC0_LD_WADDR (volatile uint32_t *)((0x4c0d << 2) + 0xffd00000)
373 #define SPICC0_ENHANCE_CNTL (0x4c0e)
374 #define P_SPICC0_ENHANCE_CNTL (volatile uint32_t *)((0x4c0e << 2) + 0xffd00000)
375 #define SPICC0_ENHANCE_CNTL1 (0x4c0f)
376 #define P_SPICC0_ENHANCE_CNTL1 (volatile uint32_t *)((0x4c0f << 2) + 0xffd00000)
377 // ------------------------------------------------------------------------------------
378 //spicc 1
379 // -----------------------------------------------
380 // CBUS_BASE: SPICC1_CBUS_BASE = 0x54
381 // -----------------------------------------------
382 #define SPICC1_RXDATA (0x5400)
383 #define P_SPICC1_RXDATA (volatile uint32_t *)((0x5400 << 2) + 0xffd00000)
384 #define SPICC1_TXDATA (0x5401)
385 #define P_SPICC1_TXDATA (volatile uint32_t *)((0x5401 << 2) + 0xffd00000)
386 #define SPICC1_CONREG (0x5402)
387 #define P_SPICC1_CONREG (volatile uint32_t *)((0x5402 << 2) + 0xffd00000)
388 #define SPICC1_INTREG (0x5403)
389 #define P_SPICC1_INTREG (volatile uint32_t *)((0x5403 << 2) + 0xffd00000)
390 #define SPICC1_DMAREG (0x5404)
391 #define P_SPICC1_DMAREG (volatile uint32_t *)((0x5404 << 2) + 0xffd00000)
392 #define SPICC1_STATREG (0x5405)
393 #define P_SPICC1_STATREG (volatile uint32_t *)((0x5405 << 2) + 0xffd00000)
394 #define SPICC1_PERIODREG (0x5406)
395 #define P_SPICC1_PERIODREG (volatile uint32_t *)((0x5406 << 2) + 0xffd00000)
396 #define SPICC1_TESTREG (0x5407)
397 #define P_SPICC1_TESTREG (volatile uint32_t *)((0x5407 << 2) + 0xffd00000)
398 #define SPICC1_DRADDR (0x5408)
399 #define P_SPICC1_DRADDR (volatile uint32_t *)((0x5408 << 2) + 0xffd00000)
400 #define SPICC1_DWADDR (0x5409)
401 #define P_SPICC1_DWADDR (volatile uint32_t *)((0x5409 << 2) + 0xffd00000)
402 #define SPICC1_LD_CNTL0 (0x540a)
403 #define P_SPICC1_LD_CNTL0 (volatile uint32_t *)((0x540a << 2) + 0xffd00000)
404 #define SPICC1_LD_CNTL1 (0x540b)
405 #define P_SPICC1_LD_CNTL1 (volatile uint32_t *)((0x540b << 2) + 0xffd00000)
406 #define SPICC1_LD_RADDR (0x540c)
407 #define P_SPICC1_LD_RADDR (volatile uint32_t *)((0x540c << 2) + 0xffd00000)
408 #define SPICC1_LD_WADDR (0x540d)
409 #define P_SPICC1_LD_WADDR (volatile uint32_t *)((0x540d << 2) + 0xffd00000)
410 #define SPICC1_ENHANCE_CNTL (0x540e)
411 #define P_SPICC1_ENHANCE_CNTL (volatile uint32_t *)((0x540e << 2) + 0xffd00000)
412 #define SPICC1_ENHANCE_CNTL1 (0x540f)
413 #define P_SPICC1_ENHANCE_CNTL1 (volatile uint32_t *)((0x540f << 2) + 0xffd00000)
414 //
415 //
416 // Closing file: periphs_reg.h
417 //
418 //
419 // Reading file: isa_reg.h
420 //
421 // $isa/rtl/isa_core register defines for the APB bus
422 // CBUS base slave address
423 // -----------------------------------------------
424 // CBUS_BASE: ISA_CBUS_BASE = 0x3c
425 // -----------------------------------------------
426 // Up to 256 registers for this base
427 #define ISA_DEBUG_REG0 (0x3c00)
428 #define P_ISA_DEBUG_REG0 (volatile uint32_t *)((0x3c00 << 2) + 0xffd00000)
429 #define ISA_DEBUG_REG1 (0x3c01)
430 #define P_ISA_DEBUG_REG1 (volatile uint32_t *)((0x3c01 << 2) + 0xffd00000)
431 #define ISA_DEBUG_REG2 (0x3c02)
432 #define P_ISA_DEBUG_REG2 (volatile uint32_t *)((0x3c02 << 2) + 0xffd00000)
433 #define ISA_DEBUG_REG3 (0x3c03)
434 #define P_ISA_DEBUG_REG3 (volatile uint32_t *)((0x3c03 << 2) + 0xffd00000)
435 #define ISA_PLL_CLK_SIM0 (0x3c08)
436 #define P_ISA_PLL_CLK_SIM0 (volatile uint32_t *)((0x3c08 << 2) + 0xffd00000)
437 #define ISA_CNTL_REG0 (0x3c09)
438 #define P_ISA_CNTL_REG0 (volatile uint32_t *)((0x3c09 << 2) + 0xffd00000)
439 // -----------------------------------------------------------
440 #define AO_CPU_IRQ_IN0_INTR_STAT (0x3c10)
441 #define P_AO_CPU_IRQ_IN0_INTR_STAT (volatile uint32_t *)((0x3c10 << 2) + 0xffd00000)
442 #define AO_CPU_IRQ_IN0_INTR_STAT_CLR (0x3c11)
443 #define P_AO_CPU_IRQ_IN0_INTR_STAT_CLR (volatile uint32_t *)((0x3c11 << 2) + 0xffd00000)
444 #define AO_CPU_IRQ_IN0_INTR_MASK (0x3c12)
445 #define P_AO_CPU_IRQ_IN0_INTR_MASK (volatile uint32_t *)((0x3c12 << 2) + 0xffd00000)
446 #define AO_CPU_IRQ_IN0_INTR_FIRQ_SEL (0x3c13)
447 #define P_AO_CPU_IRQ_IN0_INTR_FIRQ_SEL (volatile uint32_t *)((0x3c13 << 2) + 0xffd00000)
448 #define GPIO_INTR_EDGE_POL (0x3c20)
449 #define P_GPIO_INTR_EDGE_POL (volatile uint32_t *)((0x3c20 << 2) + 0xffd00000)
450 #define GPIO_INTR_GPIO_SEL0 (0x3c21)
451 #define P_GPIO_INTR_GPIO_SEL0 (volatile uint32_t *)((0x3c21 << 2) + 0xffd00000)
452 #define GPIO_INTR_GPIO_SEL1 (0x3c22)
453 #define P_GPIO_INTR_GPIO_SEL1 (volatile uint32_t *)((0x3c22 << 2) + 0xffd00000)
454 #define GPIO_INTR_FILTER_SEL0 (0x3c23)
455 #define P_GPIO_INTR_FILTER_SEL0 (volatile uint32_t *)((0x3c23 << 2) + 0xffd00000)
456 // `define GLOBAL_INTR_DISABLE 8'h24 never used
457 #define MEDIA_CPU_INTR_STAT (0x3c28)
458 #define P_MEDIA_CPU_INTR_STAT (volatile uint32_t *)((0x3c28 << 2) + 0xffd00000)
459 #define MEDIA_CPU_INTR_STAT_CLR (0x3c29)
460 #define P_MEDIA_CPU_INTR_STAT_CLR (volatile uint32_t *)((0x3c29 << 2) + 0xffd00000)
461 #define MEDIA_CPU_INTR_MASK (0x3c2a)
462 #define P_MEDIA_CPU_INTR_MASK (volatile uint32_t *)((0x3c2a << 2) + 0xffd00000)
463 #define MEDIA_CPU_INTR_FIRQ_SEL (0x3c2b)
464 #define P_MEDIA_CPU_INTR_FIRQ_SEL (volatile uint32_t *)((0x3c2b << 2) + 0xffd00000)
465 // -----------------------------------------------------------
466 #define ISA_BIST_REG0 (0x3c30)
467 #define P_ISA_BIST_REG0 (volatile uint32_t *)((0x3c30 << 2) + 0xffd00000)
468 #define ISA_BIST_REG1 (0x3c31)
469 #define P_ISA_BIST_REG1 (volatile uint32_t *)((0x3c31 << 2) + 0xffd00000)
470 // -----------------------------------------------------------
471 #define WATCHDOG_CNTL (0x3c34)
472 #define P_WATCHDOG_CNTL (volatile uint32_t *)((0x3c34 << 2) + 0xffd00000)
473 #define WATCHDOG_CNTL1 (0x3c35)
474 #define P_WATCHDOG_CNTL1 (volatile uint32_t *)((0x3c35 << 2) + 0xffd00000)
475 #define WATCHDOG_TCNT (0x3c36)
476 #define P_WATCHDOG_TCNT (volatile uint32_t *)((0x3c36 << 2) + 0xffd00000)
477 #define WATCHDOG_RESET (0x3c37)
478 #define P_WATCHDOG_RESET (volatile uint32_t *)((0x3c37 << 2) + 0xffd00000)
479 // -----------------------------------------------------------
480 #define AHB_ARBITER_REG (0x3c42)
481 #define P_AHB_ARBITER_REG (volatile uint32_t *)((0x3c42 << 2) + 0xffd00000)
482 #define AHB_ARBDEC_REG (0x3c43)
483 #define P_AHB_ARBDEC_REG (volatile uint32_t *)((0x3c43 << 2) + 0xffd00000)
484 #define AHB_ARBITER2_REG (0x3c4a)
485 #define P_AHB_ARBITER2_REG (volatile uint32_t *)((0x3c4a << 2) + 0xffd00000)
486 #define DEVICE_MMCP_CNTL (0x3c4b)
487 #define P_DEVICE_MMCP_CNTL (volatile uint32_t *)((0x3c4b << 2) + 0xffd00000)
488 #define AUDIO_MMCP_CNTL (0x3c4c)
489 #define P_AUDIO_MMCP_CNTL (volatile uint32_t *)((0x3c4c << 2) + 0xffd00000)
490 // -----------------------------------------------------------
491 #define ISA_TIMER_MUX (0x3c50)
492 #define P_ISA_TIMER_MUX (volatile uint32_t *)((0x3c50 << 2) + 0xffd00000)
493 #define ISA_TIMERA (0x3c51)
494 #define P_ISA_TIMERA (volatile uint32_t *)((0x3c51 << 2) + 0xffd00000)
495 #define ISA_TIMERB (0x3c52)
496 #define P_ISA_TIMERB (volatile uint32_t *)((0x3c52 << 2) + 0xffd00000)
497 #define ISA_TIMERC (0x3c53)
498 #define P_ISA_TIMERC (volatile uint32_t *)((0x3c53 << 2) + 0xffd00000)
499 #define ISA_TIMERD (0x3c54)
500 #define P_ISA_TIMERD (volatile uint32_t *)((0x3c54 << 2) + 0xffd00000)
501 #define FBUF_ADDR (0x3c56)
502 #define P_FBUF_ADDR (volatile uint32_t *)((0x3c56 << 2) + 0xffd00000)
503 #define VIDEO_FRM_BUF_MSB_BIT 23
504 #define VIDEO_FRM_BUF_LSB_BIT 2
505 #define SDRAM_CTL0 (0x3c57)
506 #define P_SDRAM_CTL0 (volatile uint32_t *)((0x3c57 << 2) + 0xffd00000)
507 #define SDRAM_CTL2 (0x3c58)
508 #define P_SDRAM_CTL2 (volatile uint32_t *)((0x3c58 << 2) + 0xffd00000)
509 //`define AO_CPU_CTL 8'h59
510 #define SDRAM_CTL4 (0x3c5a)
511 #define P_SDRAM_CTL4 (volatile uint32_t *)((0x3c5a << 2) + 0xffd00000)
512 #define SDRAM_CTL5 (0x3c5b)
513 #define P_SDRAM_CTL5 (volatile uint32_t *)((0x3c5b << 2) + 0xffd00000)
514 #define SDRAM_CTL6 (0x3c5c)
515 #define P_SDRAM_CTL6 (volatile uint32_t *)((0x3c5c << 2) + 0xffd00000)
516 #define SDRAM_CTL7 (0x3c5d)
517 #define P_SDRAM_CTL7 (volatile uint32_t *)((0x3c5d << 2) + 0xffd00000)
518 #define SDRAM_CTL8 (0x3c5e)
519 #define P_SDRAM_CTL8 (volatile uint32_t *)((0x3c5e << 2) + 0xffd00000)
520 #define AHB_MP4_MC_CTL (0x3c5f)
521 #define P_AHB_MP4_MC_CTL (volatile uint32_t *)((0x3c5f << 2) + 0xffd00000)
522 #define MEDIA_CPU_PCR (0x3c60)
523 #define P_MEDIA_CPU_PCR (volatile uint32_t *)((0x3c60 << 2) + 0xffd00000)
524 #define MEDIA_CPU_CTL (0x3c61)
525 #define P_MEDIA_CPU_CTL (volatile uint32_t *)((0x3c61 << 2) + 0xffd00000)
526 #define ISA_TIMERE (0x3c62)
527 #define P_ISA_TIMERE (volatile uint32_t *)((0x3c62 << 2) + 0xffd00000)
528 #define ISA_TIMERE_HI (0x3c63)
529 #define P_ISA_TIMERE_HI (volatile uint32_t *)((0x3c63 << 2) + 0xffd00000)
530 #define ISA_TIMER_MUX1 (0x3c64)
531 #define P_ISA_TIMER_MUX1 (volatile uint32_t *)((0x3c64 << 2) + 0xffd00000)
532 #define ISA_TIMERF (0x3c65)
533 #define P_ISA_TIMERF (volatile uint32_t *)((0x3c65 << 2) + 0xffd00000)
534 #define ISA_TIMERG (0x3c66)
535 #define P_ISA_TIMERG (volatile uint32_t *)((0x3c66 << 2) + 0xffd00000)
536 #define ISA_TIMERH (0x3c67)
537 #define P_ISA_TIMERH (volatile uint32_t *)((0x3c67 << 2) + 0xffd00000)
538 #define ISA_TIMERI (0x3c68)
539 #define P_ISA_TIMERI (volatile uint32_t *)((0x3c68 << 2) + 0xffd00000)
540 // ---------------------------------------------
541 #define AHB_BRIDGE_CNTL_WR (0x3c80)
542 #define P_AHB_BRIDGE_CNTL_WR (volatile uint32_t *)((0x3c80 << 2) + 0xffd00000)
543 #define AHB_BRIDGE_REMAP0 (0x3c81)
544 #define P_AHB_BRIDGE_REMAP0 (volatile uint32_t *)((0x3c81 << 2) + 0xffd00000)
545 #define AHB_BRIDGE_REMAP1 (0x3c82)
546 #define P_AHB_BRIDGE_REMAP1 (volatile uint32_t *)((0x3c82 << 2) + 0xffd00000)
547 #define AHB_BRIDGE_REMAP2 (0x3c83)
548 #define P_AHB_BRIDGE_REMAP2 (volatile uint32_t *)((0x3c83 << 2) + 0xffd00000)
549 #define AHB_BRIDGE_REMAP3 (0x3c84)
550 #define P_AHB_BRIDGE_REMAP3 (volatile uint32_t *)((0x3c84 << 2) + 0xffd00000)
551 #define AHB_BRIDGE_CNTL_REG1 (0x3c85)
552 #define P_AHB_BRIDGE_CNTL_REG1 (volatile uint32_t *)((0x3c85 << 2) + 0xffd00000)
553 #define AHB_BRIDGE_CNTL_REG2 (0x3c86)
554 #define P_AHB_BRIDGE_CNTL_REG2 (volatile uint32_t *)((0x3c86 << 2) + 0xffd00000)
555 // ---------------------------------------------
556 //
557 // Closing file: isa_reg.h
558 //
559 //
560 // Reading file: emmc_reg.h
561 //
562 // $periphs/rtl/periphs_core register defines for the
563 // APB bus
564 // ------------------------------------------------------------------------------------
565 // -----------------------------------------------
566 // CBUS_BASE: EMMCA_CBUS_BASE = 0x40c
567 // -----------------------------------------------
568 #define EMMC_A_GCLOCK (0x40c00)
569 #define P_EMMC_A_GCLOCK (volatile uint32_t *)((0x40c00 << 2) + 0xffd00000)
570 #define EMMC_A_GDELAY0 (0x40c01)
571 #define P_EMMC_A_GDELAY0 (volatile uint32_t *)((0x40c01 << 2) + 0xffd00000)
572 #define EMMC_A_GDELAY1 (0x40c02)
573 #define P_EMMC_A_GDELAY1 (volatile uint32_t *)((0x40c02 << 2) + 0xffd00000)
574 #define EMMC_A_GADJUST (0x40c03)
575 #define P_EMMC_A_GADJUST (volatile uint32_t *)((0x40c03 << 2) + 0xffd00000)
576 #define EMMC_A_GCALOUT0 (0x40c04)
577 #define P_EMMC_A_GCALOUT0 (volatile uint32_t *)((0x40c04 << 2) + 0xffd00000)
578 #define EMMC_A_GCALOUT1 (0x40c05)
579 #define P_EMMC_A_GCALOUT1 (volatile uint32_t *)((0x40c05 << 2) + 0xffd00000)
580 #define EMMC_A_GCALOUT2 (0x40c06)
581 #define P_EMMC_A_GCALOUT2 (volatile uint32_t *)((0x40c06 << 2) + 0xffd00000)
582 #define EMMC_A_GCALOUT3 (0x40c07)
583 #define P_EMMC_A_GCALOUT3 (volatile uint32_t *)((0x40c07 << 2) + 0xffd00000)
584 #define EMMC_A_GADJ_LOG (0x40c08)
585 #define P_EMMC_A_GADJ_LOG (volatile uint32_t *)((0x40c08 << 2) + 0xffd00000)
586 #define EMMC_A_GCLKTEST_LOG (0x40c09)
587 #define P_EMMC_A_GCLKTEST_LOG (volatile uint32_t *)((0x40c09 << 2) + 0xffd00000)
588 #define EMMC_A_GCLKTEST_OUT (0x40c0a)
589 #define P_EMMC_A_GCLKTEST_OUT (volatile uint32_t *)((0x40c0a << 2) + 0xffd00000)
590 #define EMMC_A_GEYETEST_LOG (0x40c0b)
591 #define P_EMMC_A_GEYETEST_LOG (volatile uint32_t *)((0x40c0b << 2) + 0xffd00000)
592 #define EMMC_A_GEYETEST_OUT0 (0x40c0c)
593 #define P_EMMC_A_GEYETEST_OUT0 (volatile uint32_t *)((0x40c0c << 2) + 0xffd00000)
594 #define EMMC_A_GEYETEST_OUT1 (0x40c0d)
595 #define P_EMMC_A_GEYETEST_OUT1 (volatile uint32_t *)((0x40c0d << 2) + 0xffd00000)
596 #define EMMC_A_GINTF3 (0x40c0e)
597 #define P_EMMC_A_GINTF3 (volatile uint32_t *)((0x40c0e << 2) + 0xffd00000)
598 #define EMMC_A_GRESERVE (0x40c0f)
599 #define P_EMMC_A_GRESERVE (volatile uint32_t *)((0x40c0f << 2) + 0xffd00000)
600 #define EMMC_A_GSTART (0x40c10)
601 #define P_EMMC_A_GSTART (volatile uint32_t *)((0x40c10 << 2) + 0xffd00000)
602 #define EMMC_A_GCFG (0x40c11)
603 #define P_EMMC_A_GCFG (volatile uint32_t *)((0x40c11 << 2) + 0xffd00000)
604 #define EMMC_A_GSTATUS (0x40c12)
605 #define P_EMMC_A_GSTATUS (volatile uint32_t *)((0x40c12 << 2) + 0xffd00000)
606 #define EMMC_A_GIRQ_EN (0x40c13)
607 #define P_EMMC_A_GIRQ_EN (volatile uint32_t *)((0x40c13 << 2) + 0xffd00000)
608 #define EMMC_A_GCMD_CFG (0x40c14)
609 #define P_EMMC_A_GCMD_CFG (volatile uint32_t *)((0x40c14 << 2) + 0xffd00000)
610 #define EMMC_A_GCMD_ARG (0x40c15)
611 #define P_EMMC_A_GCMD_ARG (volatile uint32_t *)((0x40c15 << 2) + 0xffd00000)
612 #define EMMC_A_GCMD_DAT (0x40c16)
613 #define P_EMMC_A_GCMD_DAT (volatile uint32_t *)((0x40c16 << 2) + 0xffd00000)
614 #define EMMC_A_GCMD_RSP (0x40c17)
615 #define P_EMMC_A_GCMD_RSP (volatile uint32_t *)((0x40c17 << 2) + 0xffd00000)
616 #define EMMC_A_GCMD_RSP1 (0x40c18)
617 #define P_EMMC_A_GCMD_RSP1 (volatile uint32_t *)((0x40c18 << 2) + 0xffd00000)
618 #define EMMC_A_GCMD_RSP2 (0x40c19)
619 #define P_EMMC_A_GCMD_RSP2 (volatile uint32_t *)((0x40c19 << 2) + 0xffd00000)
620 #define EMMC_A_GCMD_RSP3 (0x40c1a)
621 #define P_EMMC_A_GCMD_RSP3 (volatile uint32_t *)((0x40c1a << 2) + 0xffd00000)
622 #define EMMC_A_RESERVED_6C (0x40c1b)
623 #define P_EMMC_A_RESERVED_6C (volatile uint32_t *)((0x40c1b << 2) + 0xffd00000)
624 #define EMMC_A_GCURR_CFG (0x40c1c)
625 #define P_EMMC_A_GCURR_CFG (volatile uint32_t *)((0x40c1c << 2) + 0xffd00000)
626 #define EMMC_A_GCURR_ARG (0x40c1d)
627 #define P_EMMC_A_GCURR_ARG (volatile uint32_t *)((0x40c1d << 2) + 0xffd00000)
628 #define EMMC_A_GCURR_DAT (0x40c1e)
629 #define P_EMMC_A_GCURR_DAT (volatile uint32_t *)((0x40c1e << 2) + 0xffd00000)
630 #define EMMC_A_GCURR_RSP (0x40c1f)
631 #define P_EMMC_A_GCURR_RSP (volatile uint32_t *)((0x40c1f << 2) + 0xffd00000)
632 #define EMMC_A_GNEXT_CFG (0x40c20)
633 #define P_EMMC_A_GNEXT_CFG (volatile uint32_t *)((0x40c20 << 2) + 0xffd00000)
634 #define EMMC_A_GNEXT_ARG (0x40c21)
635 #define P_EMMC_A_GNEXT_ARG (volatile uint32_t *)((0x40c21 << 2) + 0xffd00000)
636 #define EMMC_A_GNEXT_DAT (0x40c22)
637 #define P_EMMC_A_GNEXT_DAT (volatile uint32_t *)((0x40c22 << 2) + 0xffd00000)
638 #define EMMC_A_GNEXT_RSP (0x40c23)
639 #define P_EMMC_A_GNEXT_RSP (volatile uint32_t *)((0x40c23 << 2) + 0xffd00000)
640 #define EMMC_A_GRXD (0x40c24)
641 #define P_EMMC_A_GRXD (volatile uint32_t *)((0x40c24 << 2) + 0xffd00000)
642 #define EMMC_A_GTXD (0x40c25)
643 #define P_EMMC_A_GTXD (volatile uint32_t *)((0x40c25 << 2) + 0xffd00000)
644 #define EMMC_A_RESERVED_98_00 (0x40c26)
645 #define P_EMMC_A_RESERVED_98_00 (volatile uint32_t *)((0x40c26 << 2) + 0xffd00000)
646 #define EMMC_A_RESERVED_98_01 (0x40c27)
647 #define P_EMMC_A_RESERVED_98_01 (volatile uint32_t *)((0x40c27 << 2) + 0xffd00000)
648 #define EMMC_A_RESERVED_98_02 (0x40c28)
649 #define P_EMMC_A_RESERVED_98_02 (volatile uint32_t *)((0x40c28 << 2) + 0xffd00000)
650 #define EMMC_A_RESERVED_98_03 (0x40c29)
651 #define P_EMMC_A_RESERVED_98_03 (volatile uint32_t *)((0x40c29 << 2) + 0xffd00000)
652 #define EMMC_A_RESERVED_98_04 (0x40c2a)
653 #define P_EMMC_A_RESERVED_98_04 (volatile uint32_t *)((0x40c2a << 2) + 0xffd00000)
654 #define EMMC_A_RESERVED_98_05 (0x40c2b)
655 #define P_EMMC_A_RESERVED_98_05 (volatile uint32_t *)((0x40c2b << 2) + 0xffd00000)
656 #define EMMC_A_RESERVED_98_06 (0x40c2c)
657 #define P_EMMC_A_RESERVED_98_06 (volatile uint32_t *)((0x40c2c << 2) + 0xffd00000)
658 #define EMMC_A_RESERVED_98_07 (0x40c2d)
659 #define P_EMMC_A_RESERVED_98_07 (volatile uint32_t *)((0x40c2d << 2) + 0xffd00000)
660 #define EMMC_A_RESERVED_98_08 (0x40c2e)
661 #define P_EMMC_A_RESERVED_98_08 (volatile uint32_t *)((0x40c2e << 2) + 0xffd00000)
662 #define EMMC_A_RESERVED_98_09 (0x40c2f)
663 #define P_EMMC_A_RESERVED_98_09 (volatile uint32_t *)((0x40c2f << 2) + 0xffd00000)
664 #define EMMC_A_RESERVED_98_10 (0x40c30)
665 #define P_EMMC_A_RESERVED_98_10 (volatile uint32_t *)((0x40c30 << 2) + 0xffd00000)
666 #define EMMC_A_RESERVED_98_11 (0x40c31)
667 #define P_EMMC_A_RESERVED_98_11 (volatile uint32_t *)((0x40c31 << 2) + 0xffd00000)
668 #define EMMC_A_RESERVED_98_12 (0x40c32)
669 #define P_EMMC_A_RESERVED_98_12 (volatile uint32_t *)((0x40c32 << 2) + 0xffd00000)
670 #define EMMC_A_RESERVED_98_13 (0x40c33)
671 #define P_EMMC_A_RESERVED_98_13 (volatile uint32_t *)((0x40c33 << 2) + 0xffd00000)
672 #define EMMC_A_RESERVED_98_14 (0x40c34)
673 #define P_EMMC_A_RESERVED_98_14 (volatile uint32_t *)((0x40c34 << 2) + 0xffd00000)
674 #define EMMC_A_RESERVED_98_15 (0x40c35)
675 #define P_EMMC_A_RESERVED_98_15 (volatile uint32_t *)((0x40c35 << 2) + 0xffd00000)
676 #define EMMC_A_RESERVED_98_16 (0x40c36)
677 #define P_EMMC_A_RESERVED_98_16 (volatile uint32_t *)((0x40c36 << 2) + 0xffd00000)
678 #define EMMC_A_RESERVED_98_17 (0x40c37)
679 #define P_EMMC_A_RESERVED_98_17 (volatile uint32_t *)((0x40c37 << 2) + 0xffd00000)
680 #define EMMC_A_RESERVED_98_18 (0x40c38)
681 #define P_EMMC_A_RESERVED_98_18 (volatile uint32_t *)((0x40c38 << 2) + 0xffd00000)
682 #define EMMC_A_RESERVED_98_19 (0x40c39)
683 #define P_EMMC_A_RESERVED_98_19 (volatile uint32_t *)((0x40c39 << 2) + 0xffd00000)
684 #define EMMC_A_RESERVED_98_20 (0x40c3a)
685 #define P_EMMC_A_RESERVED_98_20 (volatile uint32_t *)((0x40c3a << 2) + 0xffd00000)
686 #define EMMC_A_RESERVED_98_21 (0x40c3b)
687 #define P_EMMC_A_RESERVED_98_21 (volatile uint32_t *)((0x40c3b << 2) + 0xffd00000)
688 #define EMMC_A_RESERVED_98_22 (0x40c3c)
689 #define P_EMMC_A_RESERVED_98_22 (volatile uint32_t *)((0x40c3c << 2) + 0xffd00000)
690 #define EMMC_A_RESERVED_98_23 (0x40c3d)
691 #define P_EMMC_A_RESERVED_98_23 (volatile uint32_t *)((0x40c3d << 2) + 0xffd00000)
692 #define EMMC_A_RESERVED_98_24 (0x40c3e)
693 #define P_EMMC_A_RESERVED_98_24 (volatile uint32_t *)((0x40c3e << 2) + 0xffd00000)
694 #define EMMC_A_RESERVED_98_25 (0x40c3f)
695 #define P_EMMC_A_RESERVED_98_25 (volatile uint32_t *)((0x40c3f << 2) + 0xffd00000)
696 #define EMMC_A_RESERVED_98_26 (0x40c40)
697 #define P_EMMC_A_RESERVED_98_26 (volatile uint32_t *)((0x40c40 << 2) + 0xffd00000)
698 #define EMMC_A_RESERVED_98_27 (0x40c41)
699 #define P_EMMC_A_RESERVED_98_27 (volatile uint32_t *)((0x40c41 << 2) + 0xffd00000)
700 #define EMMC_A_RESERVED_98_28 (0x40c42)
701 #define P_EMMC_A_RESERVED_98_28 (volatile uint32_t *)((0x40c42 << 2) + 0xffd00000)
702 #define EMMC_A_RESERVED_98_29 (0x40c43)
703 #define P_EMMC_A_RESERVED_98_29 (volatile uint32_t *)((0x40c43 << 2) + 0xffd00000)
704 #define EMMC_A_RESERVED_98_30 (0x40c44)
705 #define P_EMMC_A_RESERVED_98_30 (volatile uint32_t *)((0x40c44 << 2) + 0xffd00000)
706 #define EMMC_A_RESERVED_98_31 (0x40c45)
707 #define P_EMMC_A_RESERVED_98_31 (volatile uint32_t *)((0x40c45 << 2) + 0xffd00000)
708 #define EMMC_A_RESERVED_98_32 (0x40c46)
709 #define P_EMMC_A_RESERVED_98_32 (volatile uint32_t *)((0x40c46 << 2) + 0xffd00000)
710 #define EMMC_A_RESERVED_98_33 (0x40c47)
711 #define P_EMMC_A_RESERVED_98_33 (volatile uint32_t *)((0x40c47 << 2) + 0xffd00000)
712 #define EMMC_A_RESERVED_98_34 (0x40c48)
713 #define P_EMMC_A_RESERVED_98_34 (volatile uint32_t *)((0x40c48 << 2) + 0xffd00000)
714 #define EMMC_A_RESERVED_98_35 (0x40c49)
715 #define P_EMMC_A_RESERVED_98_35 (volatile uint32_t *)((0x40c49 << 2) + 0xffd00000)
716 #define EMMC_A_RESERVED_98_36 (0x40c4a)
717 #define P_EMMC_A_RESERVED_98_36 (volatile uint32_t *)((0x40c4a << 2) + 0xffd00000)
718 #define EMMC_A_RESERVED_98_37 (0x40c4b)
719 #define P_EMMC_A_RESERVED_98_37 (volatile uint32_t *)((0x40c4b << 2) + 0xffd00000)
720 #define EMMC_A_RESERVED_98_38 (0x40c4c)
721 #define P_EMMC_A_RESERVED_98_38 (volatile uint32_t *)((0x40c4c << 2) + 0xffd00000)
722 #define EMMC_A_RESERVED_98_39 (0x40c4d)
723 #define P_EMMC_A_RESERVED_98_39 (volatile uint32_t *)((0x40c4d << 2) + 0xffd00000)
724 #define EMMC_A_RESERVED_98_40 (0x40c4e)
725 #define P_EMMC_A_RESERVED_98_40 (volatile uint32_t *)((0x40c4e << 2) + 0xffd00000)
726 #define EMMC_A_RESERVED_98_41 (0x40c4f)
727 #define P_EMMC_A_RESERVED_98_41 (volatile uint32_t *)((0x40c4f << 2) + 0xffd00000)
728 #define EMMC_A_RESERVED_98_42 (0x40c50)
729 #define P_EMMC_A_RESERVED_98_42 (volatile uint32_t *)((0x40c50 << 2) + 0xffd00000)
730 #define EMMC_A_RESERVED_98_43 (0x40c51)
731 #define P_EMMC_A_RESERVED_98_43 (volatile uint32_t *)((0x40c51 << 2) + 0xffd00000)
732 #define EMMC_A_RESERVED_98_44 (0x40c52)
733 #define P_EMMC_A_RESERVED_98_44 (volatile uint32_t *)((0x40c52 << 2) + 0xffd00000)
734 #define EMMC_A_RESERVED_98_45 (0x40c53)
735 #define P_EMMC_A_RESERVED_98_45 (volatile uint32_t *)((0x40c53 << 2) + 0xffd00000)
736 #define EMMC_A_RESERVED_98_46 (0x40c54)
737 #define P_EMMC_A_RESERVED_98_46 (volatile uint32_t *)((0x40c54 << 2) + 0xffd00000)
738 #define EMMC_A_RESERVED_98_47 (0x40c55)
739 #define P_EMMC_A_RESERVED_98_47 (volatile uint32_t *)((0x40c55 << 2) + 0xffd00000)
740 #define EMMC_A_RESERVED_98_48 (0x40c56)
741 #define P_EMMC_A_RESERVED_98_48 (volatile uint32_t *)((0x40c56 << 2) + 0xffd00000)
742 #define EMMC_A_RESERVED_98_49 (0x40c57)
743 #define P_EMMC_A_RESERVED_98_49 (volatile uint32_t *)((0x40c57 << 2) + 0xffd00000)
744 #define EMMC_A_RESERVED_98_50 (0x40c58)
745 #define P_EMMC_A_RESERVED_98_50 (volatile uint32_t *)((0x40c58 << 2) + 0xffd00000)
746 #define EMMC_A_RESERVED_98_51 (0x40c59)
747 #define P_EMMC_A_RESERVED_98_51 (volatile uint32_t *)((0x40c59 << 2) + 0xffd00000)
748 #define EMMC_A_RESERVED_98_52 (0x40c5a)
749 #define P_EMMC_A_RESERVED_98_52 (volatile uint32_t *)((0x40c5a << 2) + 0xffd00000)
750 #define EMMC_A_RESERVED_98_53 (0x40c5b)
751 #define P_EMMC_A_RESERVED_98_53 (volatile uint32_t *)((0x40c5b << 2) + 0xffd00000)
752 #define EMMC_A_RESERVED_98_54 (0x40c5c)
753 #define P_EMMC_A_RESERVED_98_54 (volatile uint32_t *)((0x40c5c << 2) + 0xffd00000)
754 #define EMMC_A_RESERVED_98_55 (0x40c5d)
755 #define P_EMMC_A_RESERVED_98_55 (volatile uint32_t *)((0x40c5d << 2) + 0xffd00000)
756 #define EMMC_A_RESERVED_98_56 (0x40c5e)
757 #define P_EMMC_A_RESERVED_98_56 (volatile uint32_t *)((0x40c5e << 2) + 0xffd00000)
758 #define EMMC_A_RESERVED_98_57 (0x40c5f)
759 #define P_EMMC_A_RESERVED_98_57 (volatile uint32_t *)((0x40c5f << 2) + 0xffd00000)
760 #define EMMC_A_RESERVED_98_58 (0x40c60)
761 #define P_EMMC_A_RESERVED_98_58 (volatile uint32_t *)((0x40c60 << 2) + 0xffd00000)
762 #define EMMC_A_RESERVED_98_59 (0x40c61)
763 #define P_EMMC_A_RESERVED_98_59 (volatile uint32_t *)((0x40c61 << 2) + 0xffd00000)
764 #define EMMC_A_RESERVED_98_60 (0x40c62)
765 #define P_EMMC_A_RESERVED_98_60 (volatile uint32_t *)((0x40c62 << 2) + 0xffd00000)
766 #define EMMC_A_RESERVED_98_61 (0x40c63)
767 #define P_EMMC_A_RESERVED_98_61 (volatile uint32_t *)((0x40c63 << 2) + 0xffd00000)
768 #define EMMC_A_RESERVED_98_62 (0x40c64)
769 #define P_EMMC_A_RESERVED_98_62 (volatile uint32_t *)((0x40c64 << 2) + 0xffd00000)
770 #define EMMC_A_RESERVED_98_63 (0x40c65)
771 #define P_EMMC_A_RESERVED_98_63 (volatile uint32_t *)((0x40c65 << 2) + 0xffd00000)
772 #define EMMC_A_RESERVED_98_64 (0x40c66)
773 #define P_EMMC_A_RESERVED_98_64 (volatile uint32_t *)((0x40c66 << 2) + 0xffd00000)
774 #define EMMC_A_RESERVED_98_65 (0x40c67)
775 #define P_EMMC_A_RESERVED_98_65 (volatile uint32_t *)((0x40c67 << 2) + 0xffd00000)
776 #define EMMC_A_RESERVED_98_66 (0x40c68)
777 #define P_EMMC_A_RESERVED_98_66 (volatile uint32_t *)((0x40c68 << 2) + 0xffd00000)
778 #define EMMC_A_RESERVED_98_67 (0x40c69)
779 #define P_EMMC_A_RESERVED_98_67 (volatile uint32_t *)((0x40c69 << 2) + 0xffd00000)
780 #define EMMC_A_RESERVED_98_68 (0x40c6a)
781 #define P_EMMC_A_RESERVED_98_68 (volatile uint32_t *)((0x40c6a << 2) + 0xffd00000)
782 #define EMMC_A_RESERVED_98_69 (0x40c6b)
783 #define P_EMMC_A_RESERVED_98_69 (volatile uint32_t *)((0x40c6b << 2) + 0xffd00000)
784 #define EMMC_A_RESERVED_98_70 (0x40c6c)
785 #define P_EMMC_A_RESERVED_98_70 (volatile uint32_t *)((0x40c6c << 2) + 0xffd00000)
786 #define EMMC_A_RESERVED_98_71 (0x40c6d)
787 #define P_EMMC_A_RESERVED_98_71 (volatile uint32_t *)((0x40c6d << 2) + 0xffd00000)
788 #define EMMC_A_RESERVED_98_72 (0x40c6e)
789 #define P_EMMC_A_RESERVED_98_72 (volatile uint32_t *)((0x40c6e << 2) + 0xffd00000)
790 #define EMMC_A_RESERVED_98_73 (0x40c6f)
791 #define P_EMMC_A_RESERVED_98_73 (volatile uint32_t *)((0x40c6f << 2) + 0xffd00000)
792 #define EMMC_A_RESERVED_98_74 (0x40c70)
793 #define P_EMMC_A_RESERVED_98_74 (volatile uint32_t *)((0x40c70 << 2) + 0xffd00000)
794 #define EMMC_A_RESERVED_98_75 (0x40c71)
795 #define P_EMMC_A_RESERVED_98_75 (volatile uint32_t *)((0x40c71 << 2) + 0xffd00000)
796 #define EMMC_A_RESERVED_98_76 (0x40c72)
797 #define P_EMMC_A_RESERVED_98_76 (volatile uint32_t *)((0x40c72 << 2) + 0xffd00000)
798 #define EMMC_A_RESERVED_98_77 (0x40c73)
799 #define P_EMMC_A_RESERVED_98_77 (volatile uint32_t *)((0x40c73 << 2) + 0xffd00000)
800 #define EMMC_A_RESERVED_98_78 (0x40c74)
801 #define P_EMMC_A_RESERVED_98_78 (volatile uint32_t *)((0x40c74 << 2) + 0xffd00000)
802 #define EMMC_A_RESERVED_98_79 (0x40c75)
803 #define P_EMMC_A_RESERVED_98_79 (volatile uint32_t *)((0x40c75 << 2) + 0xffd00000)
804 #define EMMC_A_RESERVED_98_80 (0x40c76)
805 #define P_EMMC_A_RESERVED_98_80 (volatile uint32_t *)((0x40c76 << 2) + 0xffd00000)
806 #define EMMC_A_RESERVED_98_81 (0x40c77)
807 #define P_EMMC_A_RESERVED_98_81 (volatile uint32_t *)((0x40c77 << 2) + 0xffd00000)
808 #define EMMC_A_RESERVED_98_82 (0x40c78)
809 #define P_EMMC_A_RESERVED_98_82 (volatile uint32_t *)((0x40c78 << 2) + 0xffd00000)
810 #define EMMC_A_RESERVED_98_83 (0x40c79)
811 #define P_EMMC_A_RESERVED_98_83 (volatile uint32_t *)((0x40c79 << 2) + 0xffd00000)
812 #define EMMC_A_RESERVED_98_84 (0x40c7a)
813 #define P_EMMC_A_RESERVED_98_84 (volatile uint32_t *)((0x40c7a << 2) + 0xffd00000)
814 #define EMMC_A_RESERVED_98_85 (0x40c7b)
815 #define P_EMMC_A_RESERVED_98_85 (volatile uint32_t *)((0x40c7b << 2) + 0xffd00000)
816 #define EMMC_A_RESERVED_98_86 (0x40c7c)
817 #define P_EMMC_A_RESERVED_98_86 (volatile uint32_t *)((0x40c7c << 2) + 0xffd00000)
818 #define EMMC_A_RESERVED_98_87 (0x40c7d)
819 #define P_EMMC_A_RESERVED_98_87 (volatile uint32_t *)((0x40c7d << 2) + 0xffd00000)
820 #define EMMC_A_RESERVED_98_88 (0x40c7e)
821 #define P_EMMC_A_RESERVED_98_88 (volatile uint32_t *)((0x40c7e << 2) + 0xffd00000)
822 #define EMMC_A_RESERVED_98_89 (0x40c7f)
823 #define P_EMMC_A_RESERVED_98_89 (volatile uint32_t *)((0x40c7f << 2) + 0xffd00000)
824 #define EMMC_A_GDESC_000 (0x40c80)
825 #define P_EMMC_A_GDESC_000 (volatile uint32_t *)((0x40c80 << 2) + 0xffd00000)
826 #define EMMC_A_GDESC_001 (0x40c81)
827 #define P_EMMC_A_GDESC_001 (volatile uint32_t *)((0x40c81 << 2) + 0xffd00000)
828 #define EMMC_A_GDESC_002 (0x40c82)
829 #define P_EMMC_A_GDESC_002 (volatile uint32_t *)((0x40c82 << 2) + 0xffd00000)
830 #define EMMC_A_GDESC_003 (0x40c83)
831 #define P_EMMC_A_GDESC_003 (volatile uint32_t *)((0x40c83 << 2) + 0xffd00000)
832 #define EMMC_A_GDESC_004 (0x40c84)
833 #define P_EMMC_A_GDESC_004 (volatile uint32_t *)((0x40c84 << 2) + 0xffd00000)
834 #define EMMC_A_GDESC_005 (0x40c85)
835 #define P_EMMC_A_GDESC_005 (volatile uint32_t *)((0x40c85 << 2) + 0xffd00000)
836 #define EMMC_A_GDESC_006 (0x40c86)
837 #define P_EMMC_A_GDESC_006 (volatile uint32_t *)((0x40c86 << 2) + 0xffd00000)
838 #define EMMC_A_GDESC_007 (0x40c87)
839 #define P_EMMC_A_GDESC_007 (volatile uint32_t *)((0x40c87 << 2) + 0xffd00000)
840 #define EMMC_A_GDESC_008 (0x40c88)
841 #define P_EMMC_A_GDESC_008 (volatile uint32_t *)((0x40c88 << 2) + 0xffd00000)
842 #define EMMC_A_GDESC_009 (0x40c89)
843 #define P_EMMC_A_GDESC_009 (volatile uint32_t *)((0x40c89 << 2) + 0xffd00000)
844 #define EMMC_A_GDESC_010 (0x40c8a)
845 #define P_EMMC_A_GDESC_010 (volatile uint32_t *)((0x40c8a << 2) + 0xffd00000)
846 #define EMMC_A_GDESC_011 (0x40c8b)
847 #define P_EMMC_A_GDESC_011 (volatile uint32_t *)((0x40c8b << 2) + 0xffd00000)
848 #define EMMC_A_GDESC_012 (0x40c8c)
849 #define P_EMMC_A_GDESC_012 (volatile uint32_t *)((0x40c8c << 2) + 0xffd00000)
850 #define EMMC_A_GDESC_013 (0x40c8d)
851 #define P_EMMC_A_GDESC_013 (volatile uint32_t *)((0x40c8d << 2) + 0xffd00000)
852 #define EMMC_A_GDESC_014 (0x40c8e)
853 #define P_EMMC_A_GDESC_014 (volatile uint32_t *)((0x40c8e << 2) + 0xffd00000)
854 #define EMMC_A_GDESC_015 (0x40c8f)
855 #define P_EMMC_A_GDESC_015 (volatile uint32_t *)((0x40c8f << 2) + 0xffd00000)
856 #define EMMC_A_GDESC_016 (0x40c90)
857 #define P_EMMC_A_GDESC_016 (volatile uint32_t *)((0x40c90 << 2) + 0xffd00000)
858 #define EMMC_A_GDESC_017 (0x40c91)
859 #define P_EMMC_A_GDESC_017 (volatile uint32_t *)((0x40c91 << 2) + 0xffd00000)
860 #define EMMC_A_GDESC_018 (0x40c92)
861 #define P_EMMC_A_GDESC_018 (volatile uint32_t *)((0x40c92 << 2) + 0xffd00000)
862 #define EMMC_A_GDESC_019 (0x40c93)
863 #define P_EMMC_A_GDESC_019 (volatile uint32_t *)((0x40c93 << 2) + 0xffd00000)
864 #define EMMC_A_GDESC_020 (0x40c94)
865 #define P_EMMC_A_GDESC_020 (volatile uint32_t *)((0x40c94 << 2) + 0xffd00000)
866 #define EMMC_A_GDESC_021 (0x40c95)
867 #define P_EMMC_A_GDESC_021 (volatile uint32_t *)((0x40c95 << 2) + 0xffd00000)
868 #define EMMC_A_GDESC_022 (0x40c96)
869 #define P_EMMC_A_GDESC_022 (volatile uint32_t *)((0x40c96 << 2) + 0xffd00000)
870 #define EMMC_A_GDESC_023 (0x40c97)
871 #define P_EMMC_A_GDESC_023 (volatile uint32_t *)((0x40c97 << 2) + 0xffd00000)
872 #define EMMC_A_GDESC_024 (0x40c98)
873 #define P_EMMC_A_GDESC_024 (volatile uint32_t *)((0x40c98 << 2) + 0xffd00000)
874 #define EMMC_A_GDESC_025 (0x40c99)
875 #define P_EMMC_A_GDESC_025 (volatile uint32_t *)((0x40c99 << 2) + 0xffd00000)
876 #define EMMC_A_GDESC_026 (0x40c9a)
877 #define P_EMMC_A_GDESC_026 (volatile uint32_t *)((0x40c9a << 2) + 0xffd00000)
878 #define EMMC_A_GDESC_027 (0x40c9b)
879 #define P_EMMC_A_GDESC_027 (volatile uint32_t *)((0x40c9b << 2) + 0xffd00000)
880 #define EMMC_A_GDESC_028 (0x40c9c)
881 #define P_EMMC_A_GDESC_028 (volatile uint32_t *)((0x40c9c << 2) + 0xffd00000)
882 #define EMMC_A_GDESC_029 (0x40c9d)
883 #define P_EMMC_A_GDESC_029 (volatile uint32_t *)((0x40c9d << 2) + 0xffd00000)
884 #define EMMC_A_GDESC_030 (0x40c9e)
885 #define P_EMMC_A_GDESC_030 (volatile uint32_t *)((0x40c9e << 2) + 0xffd00000)
886 #define EMMC_A_GDESC_031 (0x40c9f)
887 #define P_EMMC_A_GDESC_031 (volatile uint32_t *)((0x40c9f << 2) + 0xffd00000)
888 #define EMMC_A_GDESC_032 (0x40ca0)
889 #define P_EMMC_A_GDESC_032 (volatile uint32_t *)((0x40ca0 << 2) + 0xffd00000)
890 #define EMMC_A_GDESC_033 (0x40ca1)
891 #define P_EMMC_A_GDESC_033 (volatile uint32_t *)((0x40ca1 << 2) + 0xffd00000)
892 #define EMMC_A_GDESC_034 (0x40ca2)
893 #define P_EMMC_A_GDESC_034 (volatile uint32_t *)((0x40ca2 << 2) + 0xffd00000)
894 #define EMMC_A_GDESC_035 (0x40ca3)
895 #define P_EMMC_A_GDESC_035 (volatile uint32_t *)((0x40ca3 << 2) + 0xffd00000)
896 #define EMMC_A_GDESC_036 (0x40ca4)
897 #define P_EMMC_A_GDESC_036 (volatile uint32_t *)((0x40ca4 << 2) + 0xffd00000)
898 #define EMMC_A_GDESC_037 (0x40ca5)
899 #define P_EMMC_A_GDESC_037 (volatile uint32_t *)((0x40ca5 << 2) + 0xffd00000)
900 #define EMMC_A_GDESC_038 (0x40ca6)
901 #define P_EMMC_A_GDESC_038 (volatile uint32_t *)((0x40ca6 << 2) + 0xffd00000)
902 #define EMMC_A_GDESC_039 (0x40ca7)
903 #define P_EMMC_A_GDESC_039 (volatile uint32_t *)((0x40ca7 << 2) + 0xffd00000)
904 #define EMMC_A_GDESC_040 (0x40ca8)
905 #define P_EMMC_A_GDESC_040 (volatile uint32_t *)((0x40ca8 << 2) + 0xffd00000)
906 #define EMMC_A_GDESC_041 (0x40ca9)
907 #define P_EMMC_A_GDESC_041 (volatile uint32_t *)((0x40ca9 << 2) + 0xffd00000)
908 #define EMMC_A_GDESC_042 (0x40caa)
909 #define P_EMMC_A_GDESC_042 (volatile uint32_t *)((0x40caa << 2) + 0xffd00000)
910 #define EMMC_A_GDESC_043 (0x40cab)
911 #define P_EMMC_A_GDESC_043 (volatile uint32_t *)((0x40cab << 2) + 0xffd00000)
912 #define EMMC_A_GDESC_044 (0x40cac)
913 #define P_EMMC_A_GDESC_044 (volatile uint32_t *)((0x40cac << 2) + 0xffd00000)
914 #define EMMC_A_GDESC_045 (0x40cad)
915 #define P_EMMC_A_GDESC_045 (volatile uint32_t *)((0x40cad << 2) + 0xffd00000)
916 #define EMMC_A_GDESC_046 (0x40cae)
917 #define P_EMMC_A_GDESC_046 (volatile uint32_t *)((0x40cae << 2) + 0xffd00000)
918 #define EMMC_A_GDESC_047 (0x40caf)
919 #define P_EMMC_A_GDESC_047 (volatile uint32_t *)((0x40caf << 2) + 0xffd00000)
920 #define EMMC_A_GDESC_048 (0x40cb0)
921 #define P_EMMC_A_GDESC_048 (volatile uint32_t *)((0x40cb0 << 2) + 0xffd00000)
922 #define EMMC_A_GDESC_049 (0x40cb1)
923 #define P_EMMC_A_GDESC_049 (volatile uint32_t *)((0x40cb1 << 2) + 0xffd00000)
924 #define EMMC_A_GDESC_050 (0x40cb2)
925 #define P_EMMC_A_GDESC_050 (volatile uint32_t *)((0x40cb2 << 2) + 0xffd00000)
926 #define EMMC_A_GDESC_051 (0x40cb3)
927 #define P_EMMC_A_GDESC_051 (volatile uint32_t *)((0x40cb3 << 2) + 0xffd00000)
928 #define EMMC_A_GDESC_052 (0x40cb4)
929 #define P_EMMC_A_GDESC_052 (volatile uint32_t *)((0x40cb4 << 2) + 0xffd00000)
930 #define EMMC_A_GDESC_053 (0x40cb5)
931 #define P_EMMC_A_GDESC_053 (volatile uint32_t *)((0x40cb5 << 2) + 0xffd00000)
932 #define EMMC_A_GDESC_054 (0x40cb6)
933 #define P_EMMC_A_GDESC_054 (volatile uint32_t *)((0x40cb6 << 2) + 0xffd00000)
934 #define EMMC_A_GDESC_055 (0x40cb7)
935 #define P_EMMC_A_GDESC_055 (volatile uint32_t *)((0x40cb7 << 2) + 0xffd00000)
936 #define EMMC_A_GDESC_056 (0x40cb8)
937 #define P_EMMC_A_GDESC_056 (volatile uint32_t *)((0x40cb8 << 2) + 0xffd00000)
938 #define EMMC_A_GDESC_057 (0x40cb9)
939 #define P_EMMC_A_GDESC_057 (volatile uint32_t *)((0x40cb9 << 2) + 0xffd00000)
940 #define EMMC_A_GDESC_058 (0x40cba)
941 #define P_EMMC_A_GDESC_058 (volatile uint32_t *)((0x40cba << 2) + 0xffd00000)
942 #define EMMC_A_GDESC_059 (0x40cbb)
943 #define P_EMMC_A_GDESC_059 (volatile uint32_t *)((0x40cbb << 2) + 0xffd00000)
944 #define EMMC_A_GDESC_060 (0x40cbc)
945 #define P_EMMC_A_GDESC_060 (volatile uint32_t *)((0x40cbc << 2) + 0xffd00000)
946 #define EMMC_A_GDESC_061 (0x40cbd)
947 #define P_EMMC_A_GDESC_061 (volatile uint32_t *)((0x40cbd << 2) + 0xffd00000)
948 #define EMMC_A_GDESC_062 (0x40cbe)
949 #define P_EMMC_A_GDESC_062 (volatile uint32_t *)((0x40cbe << 2) + 0xffd00000)
950 #define EMMC_A_GDESC_063 (0x40cbf)
951 #define P_EMMC_A_GDESC_063 (volatile uint32_t *)((0x40cbf << 2) + 0xffd00000)
952 #define EMMC_A_GDESC_064 (0x40cc0)
953 #define P_EMMC_A_GDESC_064 (volatile uint32_t *)((0x40cc0 << 2) + 0xffd00000)
954 #define EMMC_A_GDESC_065 (0x40cc1)
955 #define P_EMMC_A_GDESC_065 (volatile uint32_t *)((0x40cc1 << 2) + 0xffd00000)
956 #define EMMC_A_GDESC_066 (0x40cc2)
957 #define P_EMMC_A_GDESC_066 (volatile uint32_t *)((0x40cc2 << 2) + 0xffd00000)
958 #define EMMC_A_GDESC_067 (0x40cc3)
959 #define P_EMMC_A_GDESC_067 (volatile uint32_t *)((0x40cc3 << 2) + 0xffd00000)
960 #define EMMC_A_GDESC_068 (0x40cc4)
961 #define P_EMMC_A_GDESC_068 (volatile uint32_t *)((0x40cc4 << 2) + 0xffd00000)
962 #define EMMC_A_GDESC_069 (0x40cc5)
963 #define P_EMMC_A_GDESC_069 (volatile uint32_t *)((0x40cc5 << 2) + 0xffd00000)
964 #define EMMC_A_GDESC_070 (0x40cc6)
965 #define P_EMMC_A_GDESC_070 (volatile uint32_t *)((0x40cc6 << 2) + 0xffd00000)
966 #define EMMC_A_GDESC_071 (0x40cc7)
967 #define P_EMMC_A_GDESC_071 (volatile uint32_t *)((0x40cc7 << 2) + 0xffd00000)
968 #define EMMC_A_GDESC_072 (0x40cc8)
969 #define P_EMMC_A_GDESC_072 (volatile uint32_t *)((0x40cc8 << 2) + 0xffd00000)
970 #define EMMC_A_GDESC_073 (0x40cc9)
971 #define P_EMMC_A_GDESC_073 (volatile uint32_t *)((0x40cc9 << 2) + 0xffd00000)
972 #define EMMC_A_GDESC_074 (0x40cca)
973 #define P_EMMC_A_GDESC_074 (volatile uint32_t *)((0x40cca << 2) + 0xffd00000)
974 #define EMMC_A_GDESC_075 (0x40ccb)
975 #define P_EMMC_A_GDESC_075 (volatile uint32_t *)((0x40ccb << 2) + 0xffd00000)
976 #define EMMC_A_GDESC_076 (0x40ccc)
977 #define P_EMMC_A_GDESC_076 (volatile uint32_t *)((0x40ccc << 2) + 0xffd00000)
978 #define EMMC_A_GDESC_077 (0x40ccd)
979 #define P_EMMC_A_GDESC_077 (volatile uint32_t *)((0x40ccd << 2) + 0xffd00000)
980 #define EMMC_A_GDESC_078 (0x40cce)
981 #define P_EMMC_A_GDESC_078 (volatile uint32_t *)((0x40cce << 2) + 0xffd00000)
982 #define EMMC_A_GDESC_079 (0x40ccf)
983 #define P_EMMC_A_GDESC_079 (volatile uint32_t *)((0x40ccf << 2) + 0xffd00000)
984 #define EMMC_A_GDESC_080 (0x40cd0)
985 #define P_EMMC_A_GDESC_080 (volatile uint32_t *)((0x40cd0 << 2) + 0xffd00000)
986 #define EMMC_A_GDESC_081 (0x40cd1)
987 #define P_EMMC_A_GDESC_081 (volatile uint32_t *)((0x40cd1 << 2) + 0xffd00000)
988 #define EMMC_A_GDESC_082 (0x40cd2)
989 #define P_EMMC_A_GDESC_082 (volatile uint32_t *)((0x40cd2 << 2) + 0xffd00000)
990 #define EMMC_A_GDESC_083 (0x40cd3)
991 #define P_EMMC_A_GDESC_083 (volatile uint32_t *)((0x40cd3 << 2) + 0xffd00000)
992 #define EMMC_A_GDESC_084 (0x40cd4)
993 #define P_EMMC_A_GDESC_084 (volatile uint32_t *)((0x40cd4 << 2) + 0xffd00000)
994 #define EMMC_A_GDESC_085 (0x40cd5)
995 #define P_EMMC_A_GDESC_085 (volatile uint32_t *)((0x40cd5 << 2) + 0xffd00000)
996 #define EMMC_A_GDESC_086 (0x40cd6)
997 #define P_EMMC_A_GDESC_086 (volatile uint32_t *)((0x40cd6 << 2) + 0xffd00000)
998 #define EMMC_A_GDESC_087 (0x40cd7)
999 #define P_EMMC_A_GDESC_087 (volatile uint32_t *)((0x40cd7 << 2) + 0xffd00000)
1000 #define EMMC_A_GDESC_088 (0x40cd8)
1001 #define P_EMMC_A_GDESC_088 (volatile uint32_t *)((0x40cd8 << 2) + 0xffd00000)
1002 #define EMMC_A_GDESC_089 (0x40cd9)
1003 #define P_EMMC_A_GDESC_089 (volatile uint32_t *)((0x40cd9 << 2) + 0xffd00000)
1004 #define EMMC_A_GDESC_090 (0x40cda)
1005 #define P_EMMC_A_GDESC_090 (volatile uint32_t *)((0x40cda << 2) + 0xffd00000)
1006 #define EMMC_A_GDESC_091 (0x40cdb)
1007 #define P_EMMC_A_GDESC_091 (volatile uint32_t *)((0x40cdb << 2) + 0xffd00000)
1008 #define EMMC_A_GDESC_092 (0x40cdc)
1009 #define P_EMMC_A_GDESC_092 (volatile uint32_t *)((0x40cdc << 2) + 0xffd00000)
1010 #define EMMC_A_GDESC_093 (0x40cdd)
1011 #define P_EMMC_A_GDESC_093 (volatile uint32_t *)((0x40cdd << 2) + 0xffd00000)
1012 #define EMMC_A_GDESC_094 (0x40cde)
1013 #define P_EMMC_A_GDESC_094 (volatile uint32_t *)((0x40cde << 2) + 0xffd00000)
1014 #define EMMC_A_GDESC_095 (0x40cdf)
1015 #define P_EMMC_A_GDESC_095 (volatile uint32_t *)((0x40cdf << 2) + 0xffd00000)
1016 #define EMMC_A_GDESC_096 (0x40ce0)
1017 #define P_EMMC_A_GDESC_096 (volatile uint32_t *)((0x40ce0 << 2) + 0xffd00000)
1018 #define EMMC_A_GDESC_097 (0x40ce1)
1019 #define P_EMMC_A_GDESC_097 (volatile uint32_t *)((0x40ce1 << 2) + 0xffd00000)
1020 #define EMMC_A_GDESC_098 (0x40ce2)
1021 #define P_EMMC_A_GDESC_098 (volatile uint32_t *)((0x40ce2 << 2) + 0xffd00000)
1022 #define EMMC_A_GDESC_099 (0x40ce3)
1023 #define P_EMMC_A_GDESC_099 (volatile uint32_t *)((0x40ce3 << 2) + 0xffd00000)
1024 #define EMMC_A_GDESC_100 (0x40ce4)
1025 #define P_EMMC_A_GDESC_100 (volatile uint32_t *)((0x40ce4 << 2) + 0xffd00000)
1026 #define EMMC_A_GDESC_101 (0x40ce5)
1027 #define P_EMMC_A_GDESC_101 (volatile uint32_t *)((0x40ce5 << 2) + 0xffd00000)
1028 #define EMMC_A_GDESC_102 (0x40ce6)
1029 #define P_EMMC_A_GDESC_102 (volatile uint32_t *)((0x40ce6 << 2) + 0xffd00000)
1030 #define EMMC_A_GDESC_103 (0x40ce7)
1031 #define P_EMMC_A_GDESC_103 (volatile uint32_t *)((0x40ce7 << 2) + 0xffd00000)
1032 #define EMMC_A_GDESC_104 (0x40ce8)
1033 #define P_EMMC_A_GDESC_104 (volatile uint32_t *)((0x40ce8 << 2) + 0xffd00000)
1034 #define EMMC_A_GDESC_105 (0x40ce9)
1035 #define P_EMMC_A_GDESC_105 (volatile uint32_t *)((0x40ce9 << 2) + 0xffd00000)
1036 #define EMMC_A_GDESC_106 (0x40cea)
1037 #define P_EMMC_A_GDESC_106 (volatile uint32_t *)((0x40cea << 2) + 0xffd00000)
1038 #define EMMC_A_GDESC_107 (0x40ceb)
1039 #define P_EMMC_A_GDESC_107 (volatile uint32_t *)((0x40ceb << 2) + 0xffd00000)
1040 #define EMMC_A_GDESC_108 (0x40cec)
1041 #define P_EMMC_A_GDESC_108 (volatile uint32_t *)((0x40cec << 2) + 0xffd00000)
1042 #define EMMC_A_GDESC_109 (0x40ced)
1043 #define P_EMMC_A_GDESC_109 (volatile uint32_t *)((0x40ced << 2) + 0xffd00000)
1044 #define EMMC_A_GDESC_110 (0x40cee)
1045 #define P_EMMC_A_GDESC_110 (volatile uint32_t *)((0x40cee << 2) + 0xffd00000)
1046 #define EMMC_A_GDESC_111 (0x40cef)
1047 #define P_EMMC_A_GDESC_111 (volatile uint32_t *)((0x40cef << 2) + 0xffd00000)
1048 #define EMMC_A_GDESC_112 (0x40cf0)
1049 #define P_EMMC_A_GDESC_112 (volatile uint32_t *)((0x40cf0 << 2) + 0xffd00000)
1050 #define EMMC_A_GDESC_113 (0x40cf1)
1051 #define P_EMMC_A_GDESC_113 (volatile uint32_t *)((0x40cf1 << 2) + 0xffd00000)
1052 #define EMMC_A_GDESC_114 (0x40cf2)
1053 #define P_EMMC_A_GDESC_114 (volatile uint32_t *)((0x40cf2 << 2) + 0xffd00000)
1054 #define EMMC_A_GDESC_115 (0x40cf3)
1055 #define P_EMMC_A_GDESC_115 (volatile uint32_t *)((0x40cf3 << 2) + 0xffd00000)
1056 #define EMMC_A_GDESC_116 (0x40cf4)
1057 #define P_EMMC_A_GDESC_116 (volatile uint32_t *)((0x40cf4 << 2) + 0xffd00000)
1058 #define EMMC_A_GDESC_117 (0x40cf5)
1059 #define P_EMMC_A_GDESC_117 (volatile uint32_t *)((0x40cf5 << 2) + 0xffd00000)
1060 #define EMMC_A_GDESC_118 (0x40cf6)
1061 #define P_EMMC_A_GDESC_118 (volatile uint32_t *)((0x40cf6 << 2) + 0xffd00000)
1062 #define EMMC_A_GDESC_119 (0x40cf7)
1063 #define P_EMMC_A_GDESC_119 (volatile uint32_t *)((0x40cf7 << 2) + 0xffd00000)
1064 #define EMMC_A_GDESC_120 (0x40cf8)
1065 #define P_EMMC_A_GDESC_120 (volatile uint32_t *)((0x40cf8 << 2) + 0xffd00000)
1066 #define EMMC_A_GDESC_121 (0x40cf9)
1067 #define P_EMMC_A_GDESC_121 (volatile uint32_t *)((0x40cf9 << 2) + 0xffd00000)
1068 #define EMMC_A_GDESC_122 (0x40cfa)
1069 #define P_EMMC_A_GDESC_122 (volatile uint32_t *)((0x40cfa << 2) + 0xffd00000)
1070 #define EMMC_A_GDESC_123 (0x40cfb)
1071 #define P_EMMC_A_GDESC_123 (volatile uint32_t *)((0x40cfb << 2) + 0xffd00000)
1072 #define EMMC_A_GDESC_124 (0x40cfc)
1073 #define P_EMMC_A_GDESC_124 (volatile uint32_t *)((0x40cfc << 2) + 0xffd00000)
1074 #define EMMC_A_GDESC_125 (0x40cfd)
1075 #define P_EMMC_A_GDESC_125 (volatile uint32_t *)((0x40cfd << 2) + 0xffd00000)
1076 #define EMMC_A_GDESC_126 (0x40cfe)
1077 #define P_EMMC_A_GDESC_126 (volatile uint32_t *)((0x40cfe << 2) + 0xffd00000)
1078 #define EMMC_A_GDESC_127 (0x40cff)
1079 #define P_EMMC_A_GDESC_127 (volatile uint32_t *)((0x40cff << 2) + 0xffd00000)
1080 #define EMMC_A_GPING_000 (0x40d00)
1081 #define P_EMMC_A_GPING_000 (volatile uint32_t *)((0x40d00 << 2) + 0xffd00000)
1082 #define EMMC_A_GPING_001 (0x40d01)
1083 #define P_EMMC_A_GPING_001 (volatile uint32_t *)((0x40d01 << 2) + 0xffd00000)
1084 #define EMMC_A_GPING_002 (0x40d02)
1085 #define P_EMMC_A_GPING_002 (volatile uint32_t *)((0x40d02 << 2) + 0xffd00000)
1086 #define EMMC_A_GPING_003 (0x40d03)
1087 #define P_EMMC_A_GPING_003 (volatile uint32_t *)((0x40d03 << 2) + 0xffd00000)
1088 #define EMMC_A_GPING_004 (0x40d04)
1089 #define P_EMMC_A_GPING_004 (volatile uint32_t *)((0x40d04 << 2) + 0xffd00000)
1090 #define EMMC_A_GPING_005 (0x40d05)
1091 #define P_EMMC_A_GPING_005 (volatile uint32_t *)((0x40d05 << 2) + 0xffd00000)
1092 #define EMMC_A_GPING_006 (0x40d06)
1093 #define P_EMMC_A_GPING_006 (volatile uint32_t *)((0x40d06 << 2) + 0xffd00000)
1094 #define EMMC_A_GPING_007 (0x40d07)
1095 #define P_EMMC_A_GPING_007 (volatile uint32_t *)((0x40d07 << 2) + 0xffd00000)
1096 #define EMMC_A_GPING_008 (0x40d08)
1097 #define P_EMMC_A_GPING_008 (volatile uint32_t *)((0x40d08 << 2) + 0xffd00000)
1098 #define EMMC_A_GPING_009 (0x40d09)
1099 #define P_EMMC_A_GPING_009 (volatile uint32_t *)((0x40d09 << 2) + 0xffd00000)
1100 #define EMMC_A_GPING_010 (0x40d0a)
1101 #define P_EMMC_A_GPING_010 (volatile uint32_t *)((0x40d0a << 2) + 0xffd00000)
1102 #define EMMC_A_GPING_011 (0x40d0b)
1103 #define P_EMMC_A_GPING_011 (volatile uint32_t *)((0x40d0b << 2) + 0xffd00000)
1104 #define EMMC_A_GPING_012 (0x40d0c)
1105 #define P_EMMC_A_GPING_012 (volatile uint32_t *)((0x40d0c << 2) + 0xffd00000)
1106 #define EMMC_A_GPING_013 (0x40d0d)
1107 #define P_EMMC_A_GPING_013 (volatile uint32_t *)((0x40d0d << 2) + 0xffd00000)
1108 #define EMMC_A_GPING_014 (0x40d0e)
1109 #define P_EMMC_A_GPING_014 (volatile uint32_t *)((0x40d0e << 2) + 0xffd00000)
1110 #define EMMC_A_GPING_015 (0x40d0f)
1111 #define P_EMMC_A_GPING_015 (volatile uint32_t *)((0x40d0f << 2) + 0xffd00000)
1112 #define EMMC_A_GPING_016 (0x40d10)
1113 #define P_EMMC_A_GPING_016 (volatile uint32_t *)((0x40d10 << 2) + 0xffd00000)
1114 #define EMMC_A_GPING_017 (0x40d11)
1115 #define P_EMMC_A_GPING_017 (volatile uint32_t *)((0x40d11 << 2) + 0xffd00000)
1116 #define EMMC_A_GPING_018 (0x40d12)
1117 #define P_EMMC_A_GPING_018 (volatile uint32_t *)((0x40d12 << 2) + 0xffd00000)
1118 #define EMMC_A_GPING_019 (0x40d13)
1119 #define P_EMMC_A_GPING_019 (volatile uint32_t *)((0x40d13 << 2) + 0xffd00000)
1120 #define EMMC_A_GPING_020 (0x40d14)
1121 #define P_EMMC_A_GPING_020 (volatile uint32_t *)((0x40d14 << 2) + 0xffd00000)
1122 #define EMMC_A_GPING_021 (0x40d15)
1123 #define P_EMMC_A_GPING_021 (volatile uint32_t *)((0x40d15 << 2) + 0xffd00000)
1124 #define EMMC_A_GPING_022 (0x40d16)
1125 #define P_EMMC_A_GPING_022 (volatile uint32_t *)((0x40d16 << 2) + 0xffd00000)
1126 #define EMMC_A_GPING_023 (0x40d17)
1127 #define P_EMMC_A_GPING_023 (volatile uint32_t *)((0x40d17 << 2) + 0xffd00000)
1128 #define EMMC_A_GPING_024 (0x40d18)
1129 #define P_EMMC_A_GPING_024 (volatile uint32_t *)((0x40d18 << 2) + 0xffd00000)
1130 #define EMMC_A_GPING_025 (0x40d19)
1131 #define P_EMMC_A_GPING_025 (volatile uint32_t *)((0x40d19 << 2) + 0xffd00000)
1132 #define EMMC_A_GPING_026 (0x40d1a)
1133 #define P_EMMC_A_GPING_026 (volatile uint32_t *)((0x40d1a << 2) + 0xffd00000)
1134 #define EMMC_A_GPING_027 (0x40d1b)
1135 #define P_EMMC_A_GPING_027 (volatile uint32_t *)((0x40d1b << 2) + 0xffd00000)
1136 #define EMMC_A_GPING_028 (0x40d1c)
1137 #define P_EMMC_A_GPING_028 (volatile uint32_t *)((0x40d1c << 2) + 0xffd00000)
1138 #define EMMC_A_GPING_029 (0x40d1d)
1139 #define P_EMMC_A_GPING_029 (volatile uint32_t *)((0x40d1d << 2) + 0xffd00000)
1140 #define EMMC_A_GPING_030 (0x40d1e)
1141 #define P_EMMC_A_GPING_030 (volatile uint32_t *)((0x40d1e << 2) + 0xffd00000)
1142 #define EMMC_A_GPING_031 (0x40d1f)
1143 #define P_EMMC_A_GPING_031 (volatile uint32_t *)((0x40d1f << 2) + 0xffd00000)
1144 #define EMMC_A_GPING_032 (0x40d20)
1145 #define P_EMMC_A_GPING_032 (volatile uint32_t *)((0x40d20 << 2) + 0xffd00000)
1146 #define EMMC_A_GPING_033 (0x40d21)
1147 #define P_EMMC_A_GPING_033 (volatile uint32_t *)((0x40d21 << 2) + 0xffd00000)
1148 #define EMMC_A_GPING_034 (0x40d22)
1149 #define P_EMMC_A_GPING_034 (volatile uint32_t *)((0x40d22 << 2) + 0xffd00000)
1150 #define EMMC_A_GPING_035 (0x40d23)
1151 #define P_EMMC_A_GPING_035 (volatile uint32_t *)((0x40d23 << 2) + 0xffd00000)
1152 #define EMMC_A_GPING_036 (0x40d24)
1153 #define P_EMMC_A_GPING_036 (volatile uint32_t *)((0x40d24 << 2) + 0xffd00000)
1154 #define EMMC_A_GPING_037 (0x40d25)
1155 #define P_EMMC_A_GPING_037 (volatile uint32_t *)((0x40d25 << 2) + 0xffd00000)
1156 #define EMMC_A_GPING_038 (0x40d26)
1157 #define P_EMMC_A_GPING_038 (volatile uint32_t *)((0x40d26 << 2) + 0xffd00000)
1158 #define EMMC_A_GPING_039 (0x40d27)
1159 #define P_EMMC_A_GPING_039 (volatile uint32_t *)((0x40d27 << 2) + 0xffd00000)
1160 #define EMMC_A_GPING_040 (0x40d28)
1161 #define P_EMMC_A_GPING_040 (volatile uint32_t *)((0x40d28 << 2) + 0xffd00000)
1162 #define EMMC_A_GPING_041 (0x40d29)
1163 #define P_EMMC_A_GPING_041 (volatile uint32_t *)((0x40d29 << 2) + 0xffd00000)
1164 #define EMMC_A_GPING_042 (0x40d2a)
1165 #define P_EMMC_A_GPING_042 (volatile uint32_t *)((0x40d2a << 2) + 0xffd00000)
1166 #define EMMC_A_GPING_043 (0x40d2b)
1167 #define P_EMMC_A_GPING_043 (volatile uint32_t *)((0x40d2b << 2) + 0xffd00000)
1168 #define EMMC_A_GPING_044 (0x40d2c)
1169 #define P_EMMC_A_GPING_044 (volatile uint32_t *)((0x40d2c << 2) + 0xffd00000)
1170 #define EMMC_A_GPING_045 (0x40d2d)
1171 #define P_EMMC_A_GPING_045 (volatile uint32_t *)((0x40d2d << 2) + 0xffd00000)
1172 #define EMMC_A_GPING_046 (0x40d2e)
1173 #define P_EMMC_A_GPING_046 (volatile uint32_t *)((0x40d2e << 2) + 0xffd00000)
1174 #define EMMC_A_GPING_047 (0x40d2f)
1175 #define P_EMMC_A_GPING_047 (volatile uint32_t *)((0x40d2f << 2) + 0xffd00000)
1176 #define EMMC_A_GPING_048 (0x40d30)
1177 #define P_EMMC_A_GPING_048 (volatile uint32_t *)((0x40d30 << 2) + 0xffd00000)
1178 #define EMMC_A_GPING_049 (0x40d31)
1179 #define P_EMMC_A_GPING_049 (volatile uint32_t *)((0x40d31 << 2) + 0xffd00000)
1180 #define EMMC_A_GPING_050 (0x40d32)
1181 #define P_EMMC_A_GPING_050 (volatile uint32_t *)((0x40d32 << 2) + 0xffd00000)
1182 #define EMMC_A_GPING_051 (0x40d33)
1183 #define P_EMMC_A_GPING_051 (volatile uint32_t *)((0x40d33 << 2) + 0xffd00000)
1184 #define EMMC_A_GPING_052 (0x40d34)
1185 #define P_EMMC_A_GPING_052 (volatile uint32_t *)((0x40d34 << 2) + 0xffd00000)
1186 #define EMMC_A_GPING_053 (0x40d35)
1187 #define P_EMMC_A_GPING_053 (volatile uint32_t *)((0x40d35 << 2) + 0xffd00000)
1188 #define EMMC_A_GPING_054 (0x40d36)
1189 #define P_EMMC_A_GPING_054 (volatile uint32_t *)((0x40d36 << 2) + 0xffd00000)
1190 #define EMMC_A_GPING_055 (0x40d37)
1191 #define P_EMMC_A_GPING_055 (volatile uint32_t *)((0x40d37 << 2) + 0xffd00000)
1192 #define EMMC_A_GPING_056 (0x40d38)
1193 #define P_EMMC_A_GPING_056 (volatile uint32_t *)((0x40d38 << 2) + 0xffd00000)
1194 #define EMMC_A_GPING_057 (0x40d39)
1195 #define P_EMMC_A_GPING_057 (volatile uint32_t *)((0x40d39 << 2) + 0xffd00000)
1196 #define EMMC_A_GPING_058 (0x40d3a)
1197 #define P_EMMC_A_GPING_058 (volatile uint32_t *)((0x40d3a << 2) + 0xffd00000)
1198 #define EMMC_A_GPING_059 (0x40d3b)
1199 #define P_EMMC_A_GPING_059 (volatile uint32_t *)((0x40d3b << 2) + 0xffd00000)
1200 #define EMMC_A_GPING_060 (0x40d3c)
1201 #define P_EMMC_A_GPING_060 (volatile uint32_t *)((0x40d3c << 2) + 0xffd00000)
1202 #define EMMC_A_GPING_061 (0x40d3d)
1203 #define P_EMMC_A_GPING_061 (volatile uint32_t *)((0x40d3d << 2) + 0xffd00000)
1204 #define EMMC_A_GPING_062 (0x40d3e)
1205 #define P_EMMC_A_GPING_062 (volatile uint32_t *)((0x40d3e << 2) + 0xffd00000)
1206 #define EMMC_A_GPING_063 (0x40d3f)
1207 #define P_EMMC_A_GPING_063 (volatile uint32_t *)((0x40d3f << 2) + 0xffd00000)
1208 #define EMMC_A_GPING_064 (0x40d40)
1209 #define P_EMMC_A_GPING_064 (volatile uint32_t *)((0x40d40 << 2) + 0xffd00000)
1210 #define EMMC_A_GPING_065 (0x40d41)
1211 #define P_EMMC_A_GPING_065 (volatile uint32_t *)((0x40d41 << 2) + 0xffd00000)
1212 #define EMMC_A_GPING_066 (0x40d42)
1213 #define P_EMMC_A_GPING_066 (volatile uint32_t *)((0x40d42 << 2) + 0xffd00000)
1214 #define EMMC_A_GPING_067 (0x40d43)
1215 #define P_EMMC_A_GPING_067 (volatile uint32_t *)((0x40d43 << 2) + 0xffd00000)
1216 #define EMMC_A_GPING_068 (0x40d44)
1217 #define P_EMMC_A_GPING_068 (volatile uint32_t *)((0x40d44 << 2) + 0xffd00000)
1218 #define EMMC_A_GPING_069 (0x40d45)
1219 #define P_EMMC_A_GPING_069 (volatile uint32_t *)((0x40d45 << 2) + 0xffd00000)
1220 #define EMMC_A_GPING_070 (0x40d46)
1221 #define P_EMMC_A_GPING_070 (volatile uint32_t *)((0x40d46 << 2) + 0xffd00000)
1222 #define EMMC_A_GPING_071 (0x40d47)
1223 #define P_EMMC_A_GPING_071 (volatile uint32_t *)((0x40d47 << 2) + 0xffd00000)
1224 #define EMMC_A_GPING_072 (0x40d48)
1225 #define P_EMMC_A_GPING_072 (volatile uint32_t *)((0x40d48 << 2) + 0xffd00000)
1226 #define EMMC_A_GPING_073 (0x40d49)
1227 #define P_EMMC_A_GPING_073 (volatile uint32_t *)((0x40d49 << 2) + 0xffd00000)
1228 #define EMMC_A_GPING_074 (0x40d4a)
1229 #define P_EMMC_A_GPING_074 (volatile uint32_t *)((0x40d4a << 2) + 0xffd00000)
1230 #define EMMC_A_GPING_075 (0x40d4b)
1231 #define P_EMMC_A_GPING_075 (volatile uint32_t *)((0x40d4b << 2) + 0xffd00000)
1232 #define EMMC_A_GPING_076 (0x40d4c)
1233 #define P_EMMC_A_GPING_076 (volatile uint32_t *)((0x40d4c << 2) + 0xffd00000)
1234 #define EMMC_A_GPING_077 (0x40d4d)
1235 #define P_EMMC_A_GPING_077 (volatile uint32_t *)((0x40d4d << 2) + 0xffd00000)
1236 #define EMMC_A_GPING_078 (0x40d4e)
1237 #define P_EMMC_A_GPING_078 (volatile uint32_t *)((0x40d4e << 2) + 0xffd00000)
1238 #define EMMC_A_GPING_079 (0x40d4f)
1239 #define P_EMMC_A_GPING_079 (volatile uint32_t *)((0x40d4f << 2) + 0xffd00000)
1240 #define EMMC_A_GPING_080 (0x40d50)
1241 #define P_EMMC_A_GPING_080 (volatile uint32_t *)((0x40d50 << 2) + 0xffd00000)
1242 #define EMMC_A_GPING_081 (0x40d51)
1243 #define P_EMMC_A_GPING_081 (volatile uint32_t *)((0x40d51 << 2) + 0xffd00000)
1244 #define EMMC_A_GPING_082 (0x40d52)
1245 #define P_EMMC_A_GPING_082 (volatile uint32_t *)((0x40d52 << 2) + 0xffd00000)
1246 #define EMMC_A_GPING_083 (0x40d53)
1247 #define P_EMMC_A_GPING_083 (volatile uint32_t *)((0x40d53 << 2) + 0xffd00000)
1248 #define EMMC_A_GPING_084 (0x40d54)
1249 #define P_EMMC_A_GPING_084 (volatile uint32_t *)((0x40d54 << 2) + 0xffd00000)
1250 #define EMMC_A_GPING_085 (0x40d55)
1251 #define P_EMMC_A_GPING_085 (volatile uint32_t *)((0x40d55 << 2) + 0xffd00000)
1252 #define EMMC_A_GPING_086 (0x40d56)
1253 #define P_EMMC_A_GPING_086 (volatile uint32_t *)((0x40d56 << 2) + 0xffd00000)
1254 #define EMMC_A_GPING_087 (0x40d57)
1255 #define P_EMMC_A_GPING_087 (volatile uint32_t *)((0x40d57 << 2) + 0xffd00000)
1256 #define EMMC_A_GPING_088 (0x40d58)
1257 #define P_EMMC_A_GPING_088 (volatile uint32_t *)((0x40d58 << 2) + 0xffd00000)
1258 #define EMMC_A_GPING_089 (0x40d59)
1259 #define P_EMMC_A_GPING_089 (volatile uint32_t *)((0x40d59 << 2) + 0xffd00000)
1260 #define EMMC_A_GPING_090 (0x40d5a)
1261 #define P_EMMC_A_GPING_090 (volatile uint32_t *)((0x40d5a << 2) + 0xffd00000)
1262 #define EMMC_A_GPING_091 (0x40d5b)
1263 #define P_EMMC_A_GPING_091 (volatile uint32_t *)((0x40d5b << 2) + 0xffd00000)
1264 #define EMMC_A_GPING_092 (0x40d5c)
1265 #define P_EMMC_A_GPING_092 (volatile uint32_t *)((0x40d5c << 2) + 0xffd00000)
1266 #define EMMC_A_GPING_093 (0x40d5d)
1267 #define P_EMMC_A_GPING_093 (volatile uint32_t *)((0x40d5d << 2) + 0xffd00000)
1268 #define EMMC_A_GPING_094 (0x40d5e)
1269 #define P_EMMC_A_GPING_094 (volatile uint32_t *)((0x40d5e << 2) + 0xffd00000)
1270 #define EMMC_A_GPING_095 (0x40d5f)
1271 #define P_EMMC_A_GPING_095 (volatile uint32_t *)((0x40d5f << 2) + 0xffd00000)
1272 #define EMMC_A_GPING_096 (0x40d60)
1273 #define P_EMMC_A_GPING_096 (volatile uint32_t *)((0x40d60 << 2) + 0xffd00000)
1274 #define EMMC_A_GPING_097 (0x40d61)
1275 #define P_EMMC_A_GPING_097 (volatile uint32_t *)((0x40d61 << 2) + 0xffd00000)
1276 #define EMMC_A_GPING_098 (0x40d62)
1277 #define P_EMMC_A_GPING_098 (volatile uint32_t *)((0x40d62 << 2) + 0xffd00000)
1278 #define EMMC_A_GPING_099 (0x40d63)
1279 #define P_EMMC_A_GPING_099 (volatile uint32_t *)((0x40d63 << 2) + 0xffd00000)
1280 #define EMMC_A_GPING_100 (0x40d64)
1281 #define P_EMMC_A_GPING_100 (volatile uint32_t *)((0x40d64 << 2) + 0xffd00000)
1282 #define EMMC_A_GPING_101 (0x40d65)
1283 #define P_EMMC_A_GPING_101 (volatile uint32_t *)((0x40d65 << 2) + 0xffd00000)
1284 #define EMMC_A_GPING_102 (0x40d66)
1285 #define P_EMMC_A_GPING_102 (volatile uint32_t *)((0x40d66 << 2) + 0xffd00000)
1286 #define EMMC_A_GPING_103 (0x40d67)
1287 #define P_EMMC_A_GPING_103 (volatile uint32_t *)((0x40d67 << 2) + 0xffd00000)
1288 #define EMMC_A_GPING_104 (0x40d68)
1289 #define P_EMMC_A_GPING_104 (volatile uint32_t *)((0x40d68 << 2) + 0xffd00000)
1290 #define EMMC_A_GPING_105 (0x40d69)
1291 #define P_EMMC_A_GPING_105 (volatile uint32_t *)((0x40d69 << 2) + 0xffd00000)
1292 #define EMMC_A_GPING_106 (0x40d6a)
1293 #define P_EMMC_A_GPING_106 (volatile uint32_t *)((0x40d6a << 2) + 0xffd00000)
1294 #define EMMC_A_GPING_107 (0x40d6b)
1295 #define P_EMMC_A_GPING_107 (volatile uint32_t *)((0x40d6b << 2) + 0xffd00000)
1296 #define EMMC_A_GPING_108 (0x40d6c)
1297 #define P_EMMC_A_GPING_108 (volatile uint32_t *)((0x40d6c << 2) + 0xffd00000)
1298 #define EMMC_A_GPING_109 (0x40d6d)
1299 #define P_EMMC_A_GPING_109 (volatile uint32_t *)((0x40d6d << 2) + 0xffd00000)
1300 #define EMMC_A_GPING_110 (0x40d6e)
1301 #define P_EMMC_A_GPING_110 (volatile uint32_t *)((0x40d6e << 2) + 0xffd00000)
1302 #define EMMC_A_GPING_111 (0x40d6f)
1303 #define P_EMMC_A_GPING_111 (volatile uint32_t *)((0x40d6f << 2) + 0xffd00000)
1304 #define EMMC_A_GPING_112 (0x40d70)
1305 #define P_EMMC_A_GPING_112 (volatile uint32_t *)((0x40d70 << 2) + 0xffd00000)
1306 #define EMMC_A_GPING_113 (0x40d71)
1307 #define P_EMMC_A_GPING_113 (volatile uint32_t *)((0x40d71 << 2) + 0xffd00000)
1308 #define EMMC_A_GPING_114 (0x40d72)
1309 #define P_EMMC_A_GPING_114 (volatile uint32_t *)((0x40d72 << 2) + 0xffd00000)
1310 #define EMMC_A_GPING_115 (0x40d73)
1311 #define P_EMMC_A_GPING_115 (volatile uint32_t *)((0x40d73 << 2) + 0xffd00000)
1312 #define EMMC_A_GPING_116 (0x40d74)
1313 #define P_EMMC_A_GPING_116 (volatile uint32_t *)((0x40d74 << 2) + 0xffd00000)
1314 #define EMMC_A_GPING_117 (0x40d75)
1315 #define P_EMMC_A_GPING_117 (volatile uint32_t *)((0x40d75 << 2) + 0xffd00000)
1316 #define EMMC_A_GPING_118 (0x40d76)
1317 #define P_EMMC_A_GPING_118 (volatile uint32_t *)((0x40d76 << 2) + 0xffd00000)
1318 #define EMMC_A_GPING_119 (0x40d77)
1319 #define P_EMMC_A_GPING_119 (volatile uint32_t *)((0x40d77 << 2) + 0xffd00000)
1320 #define EMMC_A_GPING_120 (0x40d78)
1321 #define P_EMMC_A_GPING_120 (volatile uint32_t *)((0x40d78 << 2) + 0xffd00000)
1322 #define EMMC_A_GPING_121 (0x40d79)
1323 #define P_EMMC_A_GPING_121 (volatile uint32_t *)((0x40d79 << 2) + 0xffd00000)
1324 #define EMMC_A_GPING_122 (0x40d7a)
1325 #define P_EMMC_A_GPING_122 (volatile uint32_t *)((0x40d7a << 2) + 0xffd00000)
1326 #define EMMC_A_GPING_123 (0x40d7b)
1327 #define P_EMMC_A_GPING_123 (volatile uint32_t *)((0x40d7b << 2) + 0xffd00000)
1328 #define EMMC_A_GPING_124 (0x40d7c)
1329 #define P_EMMC_A_GPING_124 (volatile uint32_t *)((0x40d7c << 2) + 0xffd00000)
1330 #define EMMC_A_GPING_125 (0x40d7d)
1331 #define P_EMMC_A_GPING_125 (volatile uint32_t *)((0x40d7d << 2) + 0xffd00000)
1332 #define EMMC_A_GPING_126 (0x40d7e)
1333 #define P_EMMC_A_GPING_126 (volatile uint32_t *)((0x40d7e << 2) + 0xffd00000)
1334 #define EMMC_A_GPING_127 (0x40d7f)
1335 #define P_EMMC_A_GPING_127 (volatile uint32_t *)((0x40d7f << 2) + 0xffd00000)
1336 #define EMMC_A_GPONG_000 (0x40d80)
1337 #define P_EMMC_A_GPONG_000 (volatile uint32_t *)((0x40d80 << 2) + 0xffd00000)
1338 #define EMMC_A_GPONG_001 (0x40d81)
1339 #define P_EMMC_A_GPONG_001 (volatile uint32_t *)((0x40d81 << 2) + 0xffd00000)
1340 #define EMMC_A_GPONG_002 (0x40d82)
1341 #define P_EMMC_A_GPONG_002 (volatile uint32_t *)((0x40d82 << 2) + 0xffd00000)
1342 #define EMMC_A_GPONG_003 (0x40d83)
1343 #define P_EMMC_A_GPONG_003 (volatile uint32_t *)((0x40d83 << 2) + 0xffd00000)
1344 #define EMMC_A_GPONG_004 (0x40d84)
1345 #define P_EMMC_A_GPONG_004 (volatile uint32_t *)((0x40d84 << 2) + 0xffd00000)
1346 #define EMMC_A_GPONG_005 (0x40d85)
1347 #define P_EMMC_A_GPONG_005 (volatile uint32_t *)((0x40d85 << 2) + 0xffd00000)
1348 #define EMMC_A_GPONG_006 (0x40d86)
1349 #define P_EMMC_A_GPONG_006 (volatile uint32_t *)((0x40d86 << 2) + 0xffd00000)
1350 #define EMMC_A_GPONG_007 (0x40d87)
1351 #define P_EMMC_A_GPONG_007 (volatile uint32_t *)((0x40d87 << 2) + 0xffd00000)
1352 #define EMMC_A_GPONG_008 (0x40d88)
1353 #define P_EMMC_A_GPONG_008 (volatile uint32_t *)((0x40d88 << 2) + 0xffd00000)
1354 #define EMMC_A_GPONG_009 (0x40d89)
1355 #define P_EMMC_A_GPONG_009 (volatile uint32_t *)((0x40d89 << 2) + 0xffd00000)
1356 #define EMMC_A_GPONG_010 (0x40d8a)
1357 #define P_EMMC_A_GPONG_010 (volatile uint32_t *)((0x40d8a << 2) + 0xffd00000)
1358 #define EMMC_A_GPONG_011 (0x40d8b)
1359 #define P_EMMC_A_GPONG_011 (volatile uint32_t *)((0x40d8b << 2) + 0xffd00000)
1360 #define EMMC_A_GPONG_012 (0x40d8c)
1361 #define P_EMMC_A_GPONG_012 (volatile uint32_t *)((0x40d8c << 2) + 0xffd00000)
1362 #define EMMC_A_GPONG_013 (0x40d8d)
1363 #define P_EMMC_A_GPONG_013 (volatile uint32_t *)((0x40d8d << 2) + 0xffd00000)
1364 #define EMMC_A_GPONG_014 (0x40d8e)
1365 #define P_EMMC_A_GPONG_014 (volatile uint32_t *)((0x40d8e << 2) + 0xffd00000)
1366 #define EMMC_A_GPONG_015 (0x40d8f)
1367 #define P_EMMC_A_GPONG_015 (volatile uint32_t *)((0x40d8f << 2) + 0xffd00000)
1368 #define EMMC_A_GPONG_016 (0x40d90)
1369 #define P_EMMC_A_GPONG_016 (volatile uint32_t *)((0x40d90 << 2) + 0xffd00000)
1370 #define EMMC_A_GPONG_017 (0x40d91)
1371 #define P_EMMC_A_GPONG_017 (volatile uint32_t *)((0x40d91 << 2) + 0xffd00000)
1372 #define EMMC_A_GPONG_018 (0x40d92)
1373 #define P_EMMC_A_GPONG_018 (volatile uint32_t *)((0x40d92 << 2) + 0xffd00000)
1374 #define EMMC_A_GPONG_019 (0x40d93)
1375 #define P_EMMC_A_GPONG_019 (volatile uint32_t *)((0x40d93 << 2) + 0xffd00000)
1376 #define EMMC_A_GPONG_020 (0x40d94)
1377 #define P_EMMC_A_GPONG_020 (volatile uint32_t *)((0x40d94 << 2) + 0xffd00000)
1378 #define EMMC_A_GPONG_021 (0x40d95)
1379 #define P_EMMC_A_GPONG_021 (volatile uint32_t *)((0x40d95 << 2) + 0xffd00000)
1380 #define EMMC_A_GPONG_022 (0x40d96)
1381 #define P_EMMC_A_GPONG_022 (volatile uint32_t *)((0x40d96 << 2) + 0xffd00000)
1382 #define EMMC_A_GPONG_023 (0x40d97)
1383 #define P_EMMC_A_GPONG_023 (volatile uint32_t *)((0x40d97 << 2) + 0xffd00000)
1384 #define EMMC_A_GPONG_024 (0x40d98)
1385 #define P_EMMC_A_GPONG_024 (volatile uint32_t *)((0x40d98 << 2) + 0xffd00000)
1386 #define EMMC_A_GPONG_025 (0x40d99)
1387 #define P_EMMC_A_GPONG_025 (volatile uint32_t *)((0x40d99 << 2) + 0xffd00000)
1388 #define EMMC_A_GPONG_026 (0x40d9a)
1389 #define P_EMMC_A_GPONG_026 (volatile uint32_t *)((0x40d9a << 2) + 0xffd00000)
1390 #define EMMC_A_GPONG_027 (0x40d9b)
1391 #define P_EMMC_A_GPONG_027 (volatile uint32_t *)((0x40d9b << 2) + 0xffd00000)
1392 #define EMMC_A_GPONG_028 (0x40d9c)
1393 #define P_EMMC_A_GPONG_028 (volatile uint32_t *)((0x40d9c << 2) + 0xffd00000)
1394 #define EMMC_A_GPONG_029 (0x40d9d)
1395 #define P_EMMC_A_GPONG_029 (volatile uint32_t *)((0x40d9d << 2) + 0xffd00000)
1396 #define EMMC_A_GPONG_030 (0x40d9e)
1397 #define P_EMMC_A_GPONG_030 (volatile uint32_t *)((0x40d9e << 2) + 0xffd00000)
1398 #define EMMC_A_GPONG_031 (0x40d9f)
1399 #define P_EMMC_A_GPONG_031 (volatile uint32_t *)((0x40d9f << 2) + 0xffd00000)
1400 #define EMMC_A_GPONG_032 (0x40da0)
1401 #define P_EMMC_A_GPONG_032 (volatile uint32_t *)((0x40da0 << 2) + 0xffd00000)
1402 #define EMMC_A_GPONG_033 (0x40da1)
1403 #define P_EMMC_A_GPONG_033 (volatile uint32_t *)((0x40da1 << 2) + 0xffd00000)
1404 #define EMMC_A_GPONG_034 (0x40da2)
1405 #define P_EMMC_A_GPONG_034 (volatile uint32_t *)((0x40da2 << 2) + 0xffd00000)
1406 #define EMMC_A_GPONG_035 (0x40da3)
1407 #define P_EMMC_A_GPONG_035 (volatile uint32_t *)((0x40da3 << 2) + 0xffd00000)
1408 #define EMMC_A_GPONG_036 (0x40da4)
1409 #define P_EMMC_A_GPONG_036 (volatile uint32_t *)((0x40da4 << 2) + 0xffd00000)
1410 #define EMMC_A_GPONG_037 (0x40da5)
1411 #define P_EMMC_A_GPONG_037 (volatile uint32_t *)((0x40da5 << 2) + 0xffd00000)
1412 #define EMMC_A_GPONG_038 (0x40da6)
1413 #define P_EMMC_A_GPONG_038 (volatile uint32_t *)((0x40da6 << 2) + 0xffd00000)
1414 #define EMMC_A_GPONG_039 (0x40da7)
1415 #define P_EMMC_A_GPONG_039 (volatile uint32_t *)((0x40da7 << 2) + 0xffd00000)
1416 #define EMMC_A_GPONG_040 (0x40da8)
1417 #define P_EMMC_A_GPONG_040 (volatile uint32_t *)((0x40da8 << 2) + 0xffd00000)
1418 #define EMMC_A_GPONG_041 (0x40da9)
1419 #define P_EMMC_A_GPONG_041 (volatile uint32_t *)((0x40da9 << 2) + 0xffd00000)
1420 #define EMMC_A_GPONG_042 (0x40daa)
1421 #define P_EMMC_A_GPONG_042 (volatile uint32_t *)((0x40daa << 2) + 0xffd00000)
1422 #define EMMC_A_GPONG_043 (0x40dab)
1423 #define P_EMMC_A_GPONG_043 (volatile uint32_t *)((0x40dab << 2) + 0xffd00000)
1424 #define EMMC_A_GPONG_044 (0x40dac)
1425 #define P_EMMC_A_GPONG_044 (volatile uint32_t *)((0x40dac << 2) + 0xffd00000)
1426 #define EMMC_A_GPONG_045 (0x40dad)
1427 #define P_EMMC_A_GPONG_045 (volatile uint32_t *)((0x40dad << 2) + 0xffd00000)
1428 #define EMMC_A_GPONG_046 (0x40dae)
1429 #define P_EMMC_A_GPONG_046 (volatile uint32_t *)((0x40dae << 2) + 0xffd00000)
1430 #define EMMC_A_GPONG_047 (0x40daf)
1431 #define P_EMMC_A_GPONG_047 (volatile uint32_t *)((0x40daf << 2) + 0xffd00000)
1432 #define EMMC_A_GPONG_048 (0x40db0)
1433 #define P_EMMC_A_GPONG_048 (volatile uint32_t *)((0x40db0 << 2) + 0xffd00000)
1434 #define EMMC_A_GPONG_049 (0x40db1)
1435 #define P_EMMC_A_GPONG_049 (volatile uint32_t *)((0x40db1 << 2) + 0xffd00000)
1436 #define EMMC_A_GPONG_050 (0x40db2)
1437 #define P_EMMC_A_GPONG_050 (volatile uint32_t *)((0x40db2 << 2) + 0xffd00000)
1438 #define EMMC_A_GPONG_051 (0x40db3)
1439 #define P_EMMC_A_GPONG_051 (volatile uint32_t *)((0x40db3 << 2) + 0xffd00000)
1440 #define EMMC_A_GPONG_052 (0x40db4)
1441 #define P_EMMC_A_GPONG_052 (volatile uint32_t *)((0x40db4 << 2) + 0xffd00000)
1442 #define EMMC_A_GPONG_053 (0x40db5)
1443 #define P_EMMC_A_GPONG_053 (volatile uint32_t *)((0x40db5 << 2) + 0xffd00000)
1444 #define EMMC_A_GPONG_054 (0x40db6)
1445 #define P_EMMC_A_GPONG_054 (volatile uint32_t *)((0x40db6 << 2) + 0xffd00000)
1446 #define EMMC_A_GPONG_055 (0x40db7)
1447 #define P_EMMC_A_GPONG_055 (volatile uint32_t *)((0x40db7 << 2) + 0xffd00000)
1448 #define EMMC_A_GPONG_056 (0x40db8)
1449 #define P_EMMC_A_GPONG_056 (volatile uint32_t *)((0x40db8 << 2) + 0xffd00000)
1450 #define EMMC_A_GPONG_057 (0x40db9)
1451 #define P_EMMC_A_GPONG_057 (volatile uint32_t *)((0x40db9 << 2) + 0xffd00000)
1452 #define EMMC_A_GPONG_058 (0x40dba)
1453 #define P_EMMC_A_GPONG_058 (volatile uint32_t *)((0x40dba << 2) + 0xffd00000)
1454 #define EMMC_A_GPONG_059 (0x40dbb)
1455 #define P_EMMC_A_GPONG_059 (volatile uint32_t *)((0x40dbb << 2) + 0xffd00000)
1456 #define EMMC_A_GPONG_060 (0x40dbc)
1457 #define P_EMMC_A_GPONG_060 (volatile uint32_t *)((0x40dbc << 2) + 0xffd00000)
1458 #define EMMC_A_GPONG_061 (0x40dbd)
1459 #define P_EMMC_A_GPONG_061 (volatile uint32_t *)((0x40dbd << 2) + 0xffd00000)
1460 #define EMMC_A_GPONG_062 (0x40dbe)
1461 #define P_EMMC_A_GPONG_062 (volatile uint32_t *)((0x40dbe << 2) + 0xffd00000)
1462 #define EMMC_A_GPONG_063 (0x40dbf)
1463 #define P_EMMC_A_GPONG_063 (volatile uint32_t *)((0x40dbf << 2) + 0xffd00000)
1464 #define EMMC_A_GPONG_064 (0x40dc0)
1465 #define P_EMMC_A_GPONG_064 (volatile uint32_t *)((0x40dc0 << 2) + 0xffd00000)
1466 #define EMMC_A_GPONG_065 (0x40dc1)
1467 #define P_EMMC_A_GPONG_065 (volatile uint32_t *)((0x40dc1 << 2) + 0xffd00000)
1468 #define EMMC_A_GPONG_066 (0x40dc2)
1469 #define P_EMMC_A_GPONG_066 (volatile uint32_t *)((0x40dc2 << 2) + 0xffd00000)
1470 #define EMMC_A_GPONG_067 (0x40dc3)
1471 #define P_EMMC_A_GPONG_067 (volatile uint32_t *)((0x40dc3 << 2) + 0xffd00000)
1472 #define EMMC_A_GPONG_068 (0x40dc4)
1473 #define P_EMMC_A_GPONG_068 (volatile uint32_t *)((0x40dc4 << 2) + 0xffd00000)
1474 #define EMMC_A_GPONG_069 (0x40dc5)
1475 #define P_EMMC_A_GPONG_069 (volatile uint32_t *)((0x40dc5 << 2) + 0xffd00000)
1476 #define EMMC_A_GPONG_070 (0x40dc6)
1477 #define P_EMMC_A_GPONG_070 (volatile uint32_t *)((0x40dc6 << 2) + 0xffd00000)
1478 #define EMMC_A_GPONG_071 (0x40dc7)
1479 #define P_EMMC_A_GPONG_071 (volatile uint32_t *)((0x40dc7 << 2) + 0xffd00000)
1480 #define EMMC_A_GPONG_072 (0x40dc8)
1481 #define P_EMMC_A_GPONG_072 (volatile uint32_t *)((0x40dc8 << 2) + 0xffd00000)
1482 #define EMMC_A_GPONG_073 (0x40dc9)
1483 #define P_EMMC_A_GPONG_073 (volatile uint32_t *)((0x40dc9 << 2) + 0xffd00000)
1484 #define EMMC_A_GPONG_074 (0x40dca)
1485 #define P_EMMC_A_GPONG_074 (volatile uint32_t *)((0x40dca << 2) + 0xffd00000)
1486 #define EMMC_A_GPONG_075 (0x40dcb)
1487 #define P_EMMC_A_GPONG_075 (volatile uint32_t *)((0x40dcb << 2) + 0xffd00000)
1488 #define EMMC_A_GPONG_076 (0x40dcc)
1489 #define P_EMMC_A_GPONG_076 (volatile uint32_t *)((0x40dcc << 2) + 0xffd00000)
1490 #define EMMC_A_GPONG_077 (0x40dcd)
1491 #define P_EMMC_A_GPONG_077 (volatile uint32_t *)((0x40dcd << 2) + 0xffd00000)
1492 #define EMMC_A_GPONG_078 (0x40dce)
1493 #define P_EMMC_A_GPONG_078 (volatile uint32_t *)((0x40dce << 2) + 0xffd00000)
1494 #define EMMC_A_GPONG_079 (0x40dcf)
1495 #define P_EMMC_A_GPONG_079 (volatile uint32_t *)((0x40dcf << 2) + 0xffd00000)
1496 #define EMMC_A_GPONG_080 (0x40dd0)
1497 #define P_EMMC_A_GPONG_080 (volatile uint32_t *)((0x40dd0 << 2) + 0xffd00000)
1498 #define EMMC_A_GPONG_081 (0x40dd1)
1499 #define P_EMMC_A_GPONG_081 (volatile uint32_t *)((0x40dd1 << 2) + 0xffd00000)
1500 #define EMMC_A_GPONG_082 (0x40dd2)
1501 #define P_EMMC_A_GPONG_082 (volatile uint32_t *)((0x40dd2 << 2) + 0xffd00000)
1502 #define EMMC_A_GPONG_083 (0x40dd3)
1503 #define P_EMMC_A_GPONG_083 (volatile uint32_t *)((0x40dd3 << 2) + 0xffd00000)
1504 #define EMMC_A_GPONG_084 (0x40dd4)
1505 #define P_EMMC_A_GPONG_084 (volatile uint32_t *)((0x40dd4 << 2) + 0xffd00000)
1506 #define EMMC_A_GPONG_085 (0x40dd5)
1507 #define P_EMMC_A_GPONG_085 (volatile uint32_t *)((0x40dd5 << 2) + 0xffd00000)
1508 #define EMMC_A_GPONG_086 (0x40dd6)
1509 #define P_EMMC_A_GPONG_086 (volatile uint32_t *)((0x40dd6 << 2) + 0xffd00000)
1510 #define EMMC_A_GPONG_087 (0x40dd7)
1511 #define P_EMMC_A_GPONG_087 (volatile uint32_t *)((0x40dd7 << 2) + 0xffd00000)
1512 #define EMMC_A_GPONG_088 (0x40dd8)
1513 #define P_EMMC_A_GPONG_088 (volatile uint32_t *)((0x40dd8 << 2) + 0xffd00000)
1514 #define EMMC_A_GPONG_089 (0x40dd9)
1515 #define P_EMMC_A_GPONG_089 (volatile uint32_t *)((0x40dd9 << 2) + 0xffd00000)
1516 #define EMMC_A_GPONG_090 (0x40dda)
1517 #define P_EMMC_A_GPONG_090 (volatile uint32_t *)((0x40dda << 2) + 0xffd00000)
1518 #define EMMC_A_GPONG_091 (0x40ddb)
1519 #define P_EMMC_A_GPONG_091 (volatile uint32_t *)((0x40ddb << 2) + 0xffd00000)
1520 #define EMMC_A_GPONG_092 (0x40ddc)
1521 #define P_EMMC_A_GPONG_092 (volatile uint32_t *)((0x40ddc << 2) + 0xffd00000)
1522 #define EMMC_A_GPONG_093 (0x40ddd)
1523 #define P_EMMC_A_GPONG_093 (volatile uint32_t *)((0x40ddd << 2) + 0xffd00000)
1524 #define EMMC_A_GPONG_094 (0x40dde)
1525 #define P_EMMC_A_GPONG_094 (volatile uint32_t *)((0x40dde << 2) + 0xffd00000)
1526 #define EMMC_A_GPONG_095 (0x40ddf)
1527 #define P_EMMC_A_GPONG_095 (volatile uint32_t *)((0x40ddf << 2) + 0xffd00000)
1528 #define EMMC_A_GPONG_096 (0x40de0)
1529 #define P_EMMC_A_GPONG_096 (volatile uint32_t *)((0x40de0 << 2) + 0xffd00000)
1530 #define EMMC_A_GPONG_097 (0x40de1)
1531 #define P_EMMC_A_GPONG_097 (volatile uint32_t *)((0x40de1 << 2) + 0xffd00000)
1532 #define EMMC_A_GPONG_098 (0x40de2)
1533 #define P_EMMC_A_GPONG_098 (volatile uint32_t *)((0x40de2 << 2) + 0xffd00000)
1534 #define EMMC_A_GPONG_099 (0x40de3)
1535 #define P_EMMC_A_GPONG_099 (volatile uint32_t *)((0x40de3 << 2) + 0xffd00000)
1536 #define EMMC_A_GPONG_100 (0x40de4)
1537 #define P_EMMC_A_GPONG_100 (volatile uint32_t *)((0x40de4 << 2) + 0xffd00000)
1538 #define EMMC_A_GPONG_101 (0x40de5)
1539 #define P_EMMC_A_GPONG_101 (volatile uint32_t *)((0x40de5 << 2) + 0xffd00000)
1540 #define EMMC_A_GPONG_102 (0x40de6)
1541 #define P_EMMC_A_GPONG_102 (volatile uint32_t *)((0x40de6 << 2) + 0xffd00000)
1542 #define EMMC_A_GPONG_103 (0x40de7)
1543 #define P_EMMC_A_GPONG_103 (volatile uint32_t *)((0x40de7 << 2) + 0xffd00000)
1544 #define EMMC_A_GPONG_104 (0x40de8)
1545 #define P_EMMC_A_GPONG_104 (volatile uint32_t *)((0x40de8 << 2) + 0xffd00000)
1546 #define EMMC_A_GPONG_105 (0x40de9)
1547 #define P_EMMC_A_GPONG_105 (volatile uint32_t *)((0x40de9 << 2) + 0xffd00000)
1548 #define EMMC_A_GPONG_106 (0x40dea)
1549 #define P_EMMC_A_GPONG_106 (volatile uint32_t *)((0x40dea << 2) + 0xffd00000)
1550 #define EMMC_A_GPONG_107 (0x40deb)
1551 #define P_EMMC_A_GPONG_107 (volatile uint32_t *)((0x40deb << 2) + 0xffd00000)
1552 #define EMMC_A_GPONG_108 (0x40dec)
1553 #define P_EMMC_A_GPONG_108 (volatile uint32_t *)((0x40dec << 2) + 0xffd00000)
1554 #define EMMC_A_GPONG_109 (0x40ded)
1555 #define P_EMMC_A_GPONG_109 (volatile uint32_t *)((0x40ded << 2) + 0xffd00000)
1556 #define EMMC_A_GPONG_110 (0x40dee)
1557 #define P_EMMC_A_GPONG_110 (volatile uint32_t *)((0x40dee << 2) + 0xffd00000)
1558 #define EMMC_A_GPONG_111 (0x40def)
1559 #define P_EMMC_A_GPONG_111 (volatile uint32_t *)((0x40def << 2) + 0xffd00000)
1560 #define EMMC_A_GPONG_112 (0x40df0)
1561 #define P_EMMC_A_GPONG_112 (volatile uint32_t *)((0x40df0 << 2) + 0xffd00000)
1562 #define EMMC_A_GPONG_113 (0x40df1)
1563 #define P_EMMC_A_GPONG_113 (volatile uint32_t *)((0x40df1 << 2) + 0xffd00000)
1564 #define EMMC_A_GPONG_114 (0x40df2)
1565 #define P_EMMC_A_GPONG_114 (volatile uint32_t *)((0x40df2 << 2) + 0xffd00000)
1566 #define EMMC_A_GPONG_115 (0x40df3)
1567 #define P_EMMC_A_GPONG_115 (volatile uint32_t *)((0x40df3 << 2) + 0xffd00000)
1568 #define EMMC_A_GPONG_116 (0x40df4)
1569 #define P_EMMC_A_GPONG_116 (volatile uint32_t *)((0x40df4 << 2) + 0xffd00000)
1570 #define EMMC_A_GPONG_117 (0x40df5)
1571 #define P_EMMC_A_GPONG_117 (volatile uint32_t *)((0x40df5 << 2) + 0xffd00000)
1572 #define EMMC_A_GPONG_118 (0x40df6)
1573 #define P_EMMC_A_GPONG_118 (volatile uint32_t *)((0x40df6 << 2) + 0xffd00000)
1574 #define EMMC_A_GPONG_119 (0x40df7)
1575 #define P_EMMC_A_GPONG_119 (volatile uint32_t *)((0x40df7 << 2) + 0xffd00000)
1576 #define EMMC_A_GPONG_120 (0x40df8)
1577 #define P_EMMC_A_GPONG_120 (volatile uint32_t *)((0x40df8 << 2) + 0xffd00000)
1578 #define EMMC_A_GPONG_121 (0x40df9)
1579 #define P_EMMC_A_GPONG_121 (volatile uint32_t *)((0x40df9 << 2) + 0xffd00000)
1580 #define EMMC_A_GPONG_122 (0x40dfa)
1581 #define P_EMMC_A_GPONG_122 (volatile uint32_t *)((0x40dfa << 2) + 0xffd00000)
1582 #define EMMC_A_GPONG_123 (0x40dfb)
1583 #define P_EMMC_A_GPONG_123 (volatile uint32_t *)((0x40dfb << 2) + 0xffd00000)
1584 #define EMMC_A_GPONG_124 (0x40dfc)
1585 #define P_EMMC_A_GPONG_124 (volatile uint32_t *)((0x40dfc << 2) + 0xffd00000)
1586 #define EMMC_A_GPONG_125 (0x40dfd)
1587 #define P_EMMC_A_GPONG_125 (volatile uint32_t *)((0x40dfd << 2) + 0xffd00000)
1588 #define EMMC_A_GPONG_126 (0x40dfe)
1589 #define P_EMMC_A_GPONG_126 (volatile uint32_t *)((0x40dfe << 2) + 0xffd00000)
1590 #define EMMC_A_GPONG_127 (0x40dff)
1591 #define P_EMMC_A_GPONG_127 (volatile uint32_t *)((0x40dff << 2) + 0xffd00000)
1592 // -----------------------------------------------
1593 // CBUS_BASE: EMMCB_CBUS_BASE = 0x414
1594 // -----------------------------------------------
1595 #define EMMC_B_GCLOCK (0x41400)
1596 #define P_EMMC_B_GCLOCK (volatile uint32_t *)((0x41400 << 2) + 0xffd00000)
1597 #define EMMC_B_GDELAY0 (0x41401)
1598 #define P_EMMC_B_GDELAY0 (volatile uint32_t *)((0x41401 << 2) + 0xffd00000)
1599 #define EMMC_B_GDELAY1 (0x41402)
1600 #define P_EMMC_B_GDELAY1 (volatile uint32_t *)((0x41402 << 2) + 0xffd00000)
1601 #define EMMC_B_GADJUST (0x41403)
1602 #define P_EMMC_B_GADJUST (volatile uint32_t *)((0x41403 << 2) + 0xffd00000)
1603 #define EMMC_B_GCALOUT0 (0x41404)
1604 #define P_EMMC_B_GCALOUT0 (volatile uint32_t *)((0x41404 << 2) + 0xffd00000)
1605 #define EMMC_B_GCALOUT1 (0x41405)
1606 #define P_EMMC_B_GCALOUT1 (volatile uint32_t *)((0x41405 << 2) + 0xffd00000)
1607 #define EMMC_B_GCALOUT2 (0x41406)
1608 #define P_EMMC_B_GCALOUT2 (volatile uint32_t *)((0x41406 << 2) + 0xffd00000)
1609 #define EMMC_B_GCALOUT3 (0x41407)
1610 #define P_EMMC_B_GCALOUT3 (volatile uint32_t *)((0x41407 << 2) + 0xffd00000)
1611 #define EMMC_B_GADJ_LOG (0x41408)
1612 #define P_EMMC_B_GADJ_LOG (volatile uint32_t *)((0x41408 << 2) + 0xffd00000)
1613 #define EMMC_B_GCLKTEST_LOG (0x41409)
1614 #define P_EMMC_B_GCLKTEST_LOG (volatile uint32_t *)((0x41409 << 2) + 0xffd00000)
1615 #define EMMC_B_GCLKTEST_OUT (0x4140a)
1616 #define P_EMMC_B_GCLKTEST_OUT (volatile uint32_t *)((0x4140a << 2) + 0xffd00000)
1617 #define EMMC_B_GEYETEST_LOG (0x4140b)
1618 #define P_EMMC_B_GEYETEST_LOG (volatile uint32_t *)((0x4140b << 2) + 0xffd00000)
1619 #define EMMC_B_GEYETEST_OUT0 (0x4140c)
1620 #define P_EMMC_B_GEYETEST_OUT0 (volatile uint32_t *)((0x4140c << 2) + 0xffd00000)
1621 #define EMMC_B_GEYETEST_OUT1 (0x4140d)
1622 #define P_EMMC_B_GEYETEST_OUT1 (volatile uint32_t *)((0x4140d << 2) + 0xffd00000)
1623 #define EMMC_B_GINTF3 (0x4140e)
1624 #define P_EMMC_B_GINTF3 (volatile uint32_t *)((0x4140e << 2) + 0xffd00000)
1625 #define EMMC_B_GRESERVE (0x4140f)
1626 #define P_EMMC_B_GRESERVE (volatile uint32_t *)((0x4140f << 2) + 0xffd00000)
1627 #define EMMC_B_GSTART (0x41410)
1628 #define P_EMMC_B_GSTART (volatile uint32_t *)((0x41410 << 2) + 0xffd00000)
1629 #define EMMC_B_GCFG (0x41411)
1630 #define P_EMMC_B_GCFG (volatile uint32_t *)((0x41411 << 2) + 0xffd00000)
1631 #define EMMC_B_GSTATUS (0x41412)
1632 #define P_EMMC_B_GSTATUS (volatile uint32_t *)((0x41412 << 2) + 0xffd00000)
1633 #define EMMC_B_GIRQ_EN (0x41413)
1634 #define P_EMMC_B_GIRQ_EN (volatile uint32_t *)((0x41413 << 2) + 0xffd00000)
1635 #define EMMC_B_GCMD_CFG (0x41414)
1636 #define P_EMMC_B_GCMD_CFG (volatile uint32_t *)((0x41414 << 2) + 0xffd00000)
1637 #define EMMC_B_GCMD_ARG (0x41415)
1638 #define P_EMMC_B_GCMD_ARG (volatile uint32_t *)((0x41415 << 2) + 0xffd00000)
1639 #define EMMC_B_GCMD_DAT (0x41416)
1640 #define P_EMMC_B_GCMD_DAT (volatile uint32_t *)((0x41416 << 2) + 0xffd00000)
1641 #define EMMC_B_GCMD_RSP (0x41417)
1642 #define P_EMMC_B_GCMD_RSP (volatile uint32_t *)((0x41417 << 2) + 0xffd00000)
1643 #define EMMC_B_GCMD_RSP1 (0x41418)
1644 #define P_EMMC_B_GCMD_RSP1 (volatile uint32_t *)((0x41418 << 2) + 0xffd00000)
1645 #define EMMC_B_GCMD_RSP2 (0x41419)
1646 #define P_EMMC_B_GCMD_RSP2 (volatile uint32_t *)((0x41419 << 2) + 0xffd00000)
1647 #define EMMC_B_GCMD_RSP3 (0x4141a)
1648 #define P_EMMC_B_GCMD_RSP3 (volatile uint32_t *)((0x4141a << 2) + 0xffd00000)
1649 #define EMMC_B_RESERVED_6C (0x4141b)
1650 #define P_EMMC_B_RESERVED_6C (volatile uint32_t *)((0x4141b << 2) + 0xffd00000)
1651 #define EMMC_B_GCURR_CFG (0x4141c)
1652 #define P_EMMC_B_GCURR_CFG (volatile uint32_t *)((0x4141c << 2) + 0xffd00000)
1653 #define EMMC_B_GCURR_ARG (0x4141d)
1654 #define P_EMMC_B_GCURR_ARG (volatile uint32_t *)((0x4141d << 2) + 0xffd00000)
1655 #define EMMC_B_GCURR_DAT (0x4141e)
1656 #define P_EMMC_B_GCURR_DAT (volatile uint32_t *)((0x4141e << 2) + 0xffd00000)
1657 #define EMMC_B_GCURR_RSP (0x4141f)
1658 #define P_EMMC_B_GCURR_RSP (volatile uint32_t *)((0x4141f << 2) + 0xffd00000)
1659 #define EMMC_B_GNEXT_CFG (0x41420)
1660 #define P_EMMC_B_GNEXT_CFG (volatile uint32_t *)((0x41420 << 2) + 0xffd00000)
1661 #define EMMC_B_GNEXT_ARG (0x41421)
1662 #define P_EMMC_B_GNEXT_ARG (volatile uint32_t *)((0x41421 << 2) + 0xffd00000)
1663 #define EMMC_B_GNEXT_DAT (0x41422)
1664 #define P_EMMC_B_GNEXT_DAT (volatile uint32_t *)((0x41422 << 2) + 0xffd00000)
1665 #define EMMC_B_GNEXT_RSP (0x41423)
1666 #define P_EMMC_B_GNEXT_RSP (volatile uint32_t *)((0x41423 << 2) + 0xffd00000)
1667 #define EMMC_B_GRXD (0x41424)
1668 #define P_EMMC_B_GRXD (volatile uint32_t *)((0x41424 << 2) + 0xffd00000)
1669 #define EMMC_B_GTXD (0x41425)
1670 #define P_EMMC_B_GTXD (volatile uint32_t *)((0x41425 << 2) + 0xffd00000)
1671 #define EMMC_B_RESERVED_98_00 (0x41426)
1672 #define P_EMMC_B_RESERVED_98_00 (volatile uint32_t *)((0x41426 << 2) + 0xffd00000)
1673 #define EMMC_B_RESERVED_98_01 (0x41427)
1674 #define P_EMMC_B_RESERVED_98_01 (volatile uint32_t *)((0x41427 << 2) + 0xffd00000)
1675 #define EMMC_B_RESERVED_98_02 (0x41428)
1676 #define P_EMMC_B_RESERVED_98_02 (volatile uint32_t *)((0x41428 << 2) + 0xffd00000)
1677 #define EMMC_B_RESERVED_98_03 (0x41429)
1678 #define P_EMMC_B_RESERVED_98_03 (volatile uint32_t *)((0x41429 << 2) + 0xffd00000)
1679 #define EMMC_B_RESERVED_98_04 (0x4142a)
1680 #define P_EMMC_B_RESERVED_98_04 (volatile uint32_t *)((0x4142a << 2) + 0xffd00000)
1681 #define EMMC_B_RESERVED_98_05 (0x4142b)
1682 #define P_EMMC_B_RESERVED_98_05 (volatile uint32_t *)((0x4142b << 2) + 0xffd00000)
1683 #define EMMC_B_RESERVED_98_06 (0x4142c)
1684 #define P_EMMC_B_RESERVED_98_06 (volatile uint32_t *)((0x4142c << 2) + 0xffd00000)
1685 #define EMMC_B_RESERVED_98_07 (0x4142d)
1686 #define P_EMMC_B_RESERVED_98_07 (volatile uint32_t *)((0x4142d << 2) + 0xffd00000)
1687 #define EMMC_B_RESERVED_98_08 (0x4142e)
1688 #define P_EMMC_B_RESERVED_98_08 (volatile uint32_t *)((0x4142e << 2) + 0xffd00000)
1689 #define EMMC_B_RESERVED_98_09 (0x4142f)
1690 #define P_EMMC_B_RESERVED_98_09 (volatile uint32_t *)((0x4142f << 2) + 0xffd00000)
1691 #define EMMC_B_RESERVED_98_10 (0x41430)
1692 #define P_EMMC_B_RESERVED_98_10 (volatile uint32_t *)((0x41430 << 2) + 0xffd00000)
1693 #define EMMC_B_RESERVED_98_11 (0x41431)
1694 #define P_EMMC_B_RESERVED_98_11 (volatile uint32_t *)((0x41431 << 2) + 0xffd00000)
1695 #define EMMC_B_RESERVED_98_12 (0x41432)
1696 #define P_EMMC_B_RESERVED_98_12 (volatile uint32_t *)((0x41432 << 2) + 0xffd00000)
1697 #define EMMC_B_RESERVED_98_13 (0x41433)
1698 #define P_EMMC_B_RESERVED_98_13 (volatile uint32_t *)((0x41433 << 2) + 0xffd00000)
1699 #define EMMC_B_RESERVED_98_14 (0x41434)
1700 #define P_EMMC_B_RESERVED_98_14 (volatile uint32_t *)((0x41434 << 2) + 0xffd00000)
1701 #define EMMC_B_RESERVED_98_15 (0x41435)
1702 #define P_EMMC_B_RESERVED_98_15 (volatile uint32_t *)((0x41435 << 2) + 0xffd00000)
1703 #define EMMC_B_RESERVED_98_16 (0x41436)
1704 #define P_EMMC_B_RESERVED_98_16 (volatile uint32_t *)((0x41436 << 2) + 0xffd00000)
1705 #define EMMC_B_RESERVED_98_17 (0x41437)
1706 #define P_EMMC_B_RESERVED_98_17 (volatile uint32_t *)((0x41437 << 2) + 0xffd00000)
1707 #define EMMC_B_RESERVED_98_18 (0x41438)
1708 #define P_EMMC_B_RESERVED_98_18 (volatile uint32_t *)((0x41438 << 2) + 0xffd00000)
1709 #define EMMC_B_RESERVED_98_19 (0x41439)
1710 #define P_EMMC_B_RESERVED_98_19 (volatile uint32_t *)((0x41439 << 2) + 0xffd00000)
1711 #define EMMC_B_RESERVED_98_20 (0x4143a)
1712 #define P_EMMC_B_RESERVED_98_20 (volatile uint32_t *)((0x4143a << 2) + 0xffd00000)
1713 #define EMMC_B_RESERVED_98_21 (0x4143b)
1714 #define P_EMMC_B_RESERVED_98_21 (volatile uint32_t *)((0x4143b << 2) + 0xffd00000)
1715 #define EMMC_B_RESERVED_98_22 (0x4143c)
1716 #define P_EMMC_B_RESERVED_98_22 (volatile uint32_t *)((0x4143c << 2) + 0xffd00000)
1717 #define EMMC_B_RESERVED_98_23 (0x4143d)
1718 #define P_EMMC_B_RESERVED_98_23 (volatile uint32_t *)((0x4143d << 2) + 0xffd00000)
1719 #define EMMC_B_RESERVED_98_24 (0x4143e)
1720 #define P_EMMC_B_RESERVED_98_24 (volatile uint32_t *)((0x4143e << 2) + 0xffd00000)
1721 #define EMMC_B_RESERVED_98_25 (0x4143f)
1722 #define P_EMMC_B_RESERVED_98_25 (volatile uint32_t *)((0x4143f << 2) + 0xffd00000)
1723 #define EMMC_B_RESERVED_98_26 (0x41440)
1724 #define P_EMMC_B_RESERVED_98_26 (volatile uint32_t *)((0x41440 << 2) + 0xffd00000)
1725 #define EMMC_B_RESERVED_98_27 (0x41441)
1726 #define P_EMMC_B_RESERVED_98_27 (volatile uint32_t *)((0x41441 << 2) + 0xffd00000)
1727 #define EMMC_B_RESERVED_98_28 (0x41442)
1728 #define P_EMMC_B_RESERVED_98_28 (volatile uint32_t *)((0x41442 << 2) + 0xffd00000)
1729 #define EMMC_B_RESERVED_98_29 (0x41443)
1730 #define P_EMMC_B_RESERVED_98_29 (volatile uint32_t *)((0x41443 << 2) + 0xffd00000)
1731 #define EMMC_B_RESERVED_98_30 (0x41444)
1732 #define P_EMMC_B_RESERVED_98_30 (volatile uint32_t *)((0x41444 << 2) + 0xffd00000)
1733 #define EMMC_B_RESERVED_98_31 (0x41445)
1734 #define P_EMMC_B_RESERVED_98_31 (volatile uint32_t *)((0x41445 << 2) + 0xffd00000)
1735 #define EMMC_B_RESERVED_98_32 (0x41446)
1736 #define P_EMMC_B_RESERVED_98_32 (volatile uint32_t *)((0x41446 << 2) + 0xffd00000)
1737 #define EMMC_B_RESERVED_98_33 (0x41447)
1738 #define P_EMMC_B_RESERVED_98_33 (volatile uint32_t *)((0x41447 << 2) + 0xffd00000)
1739 #define EMMC_B_RESERVED_98_34 (0x41448)
1740 #define P_EMMC_B_RESERVED_98_34 (volatile uint32_t *)((0x41448 << 2) + 0xffd00000)
1741 #define EMMC_B_RESERVED_98_35 (0x41449)
1742 #define P_EMMC_B_RESERVED_98_35 (volatile uint32_t *)((0x41449 << 2) + 0xffd00000)
1743 #define EMMC_B_RESERVED_98_36 (0x4144a)
1744 #define P_EMMC_B_RESERVED_98_36 (volatile uint32_t *)((0x4144a << 2) + 0xffd00000)
1745 #define EMMC_B_RESERVED_98_37 (0x4144b)
1746 #define P_EMMC_B_RESERVED_98_37 (volatile uint32_t *)((0x4144b << 2) + 0xffd00000)
1747 #define EMMC_B_RESERVED_98_38 (0x4144c)
1748 #define P_EMMC_B_RESERVED_98_38 (volatile uint32_t *)((0x4144c << 2) + 0xffd00000)
1749 #define EMMC_B_RESERVED_98_39 (0x4144d)
1750 #define P_EMMC_B_RESERVED_98_39 (volatile uint32_t *)((0x4144d << 2) + 0xffd00000)
1751 #define EMMC_B_RESERVED_98_40 (0x4144e)
1752 #define P_EMMC_B_RESERVED_98_40 (volatile uint32_t *)((0x4144e << 2) + 0xffd00000)
1753 #define EMMC_B_RESERVED_98_41 (0x4144f)
1754 #define P_EMMC_B_RESERVED_98_41 (volatile uint32_t *)((0x4144f << 2) + 0xffd00000)
1755 #define EMMC_B_RESERVED_98_42 (0x41450)
1756 #define P_EMMC_B_RESERVED_98_42 (volatile uint32_t *)((0x41450 << 2) + 0xffd00000)
1757 #define EMMC_B_RESERVED_98_43 (0x41451)
1758 #define P_EMMC_B_RESERVED_98_43 (volatile uint32_t *)((0x41451 << 2) + 0xffd00000)
1759 #define EMMC_B_RESERVED_98_44 (0x41452)
1760 #define P_EMMC_B_RESERVED_98_44 (volatile uint32_t *)((0x41452 << 2) + 0xffd00000)
1761 #define EMMC_B_RESERVED_98_45 (0x41453)
1762 #define P_EMMC_B_RESERVED_98_45 (volatile uint32_t *)((0x41453 << 2) + 0xffd00000)
1763 #define EMMC_B_RESERVED_98_46 (0x41454)
1764 #define P_EMMC_B_RESERVED_98_46 (volatile uint32_t *)((0x41454 << 2) + 0xffd00000)
1765 #define EMMC_B_RESERVED_98_47 (0x41455)
1766 #define P_EMMC_B_RESERVED_98_47 (volatile uint32_t *)((0x41455 << 2) + 0xffd00000)
1767 #define EMMC_B_RESERVED_98_48 (0x41456)
1768 #define P_EMMC_B_RESERVED_98_48 (volatile uint32_t *)((0x41456 << 2) + 0xffd00000)
1769 #define EMMC_B_RESERVED_98_49 (0x41457)
1770 #define P_EMMC_B_RESERVED_98_49 (volatile uint32_t *)((0x41457 << 2) + 0xffd00000)
1771 #define EMMC_B_RESERVED_98_50 (0x41458)
1772 #define P_EMMC_B_RESERVED_98_50 (volatile uint32_t *)((0x41458 << 2) + 0xffd00000)
1773 #define EMMC_B_RESERVED_98_51 (0x41459)
1774 #define P_EMMC_B_RESERVED_98_51 (volatile uint32_t *)((0x41459 << 2) + 0xffd00000)
1775 #define EMMC_B_RESERVED_98_52 (0x4145a)
1776 #define P_EMMC_B_RESERVED_98_52 (volatile uint32_t *)((0x4145a << 2) + 0xffd00000)
1777 #define EMMC_B_RESERVED_98_53 (0x4145b)
1778 #define P_EMMC_B_RESERVED_98_53 (volatile uint32_t *)((0x4145b << 2) + 0xffd00000)
1779 #define EMMC_B_RESERVED_98_54 (0x4145c)
1780 #define P_EMMC_B_RESERVED_98_54 (volatile uint32_t *)((0x4145c << 2) + 0xffd00000)
1781 #define EMMC_B_RESERVED_98_55 (0x4145d)
1782 #define P_EMMC_B_RESERVED_98_55 (volatile uint32_t *)((0x4145d << 2) + 0xffd00000)
1783 #define EMMC_B_RESERVED_98_56 (0x4145e)
1784 #define P_EMMC_B_RESERVED_98_56 (volatile uint32_t *)((0x4145e << 2) + 0xffd00000)
1785 #define EMMC_B_RESERVED_98_57 (0x4145f)
1786 #define P_EMMC_B_RESERVED_98_57 (volatile uint32_t *)((0x4145f << 2) + 0xffd00000)
1787 #define EMMC_B_RESERVED_98_58 (0x41460)
1788 #define P_EMMC_B_RESERVED_98_58 (volatile uint32_t *)((0x41460 << 2) + 0xffd00000)
1789 #define EMMC_B_RESERVED_98_59 (0x41461)
1790 #define P_EMMC_B_RESERVED_98_59 (volatile uint32_t *)((0x41461 << 2) + 0xffd00000)
1791 #define EMMC_B_RESERVED_98_60 (0x41462)
1792 #define P_EMMC_B_RESERVED_98_60 (volatile uint32_t *)((0x41462 << 2) + 0xffd00000)
1793 #define EMMC_B_RESERVED_98_61 (0x41463)
1794 #define P_EMMC_B_RESERVED_98_61 (volatile uint32_t *)((0x41463 << 2) + 0xffd00000)
1795 #define EMMC_B_RESERVED_98_62 (0x41464)
1796 #define P_EMMC_B_RESERVED_98_62 (volatile uint32_t *)((0x41464 << 2) + 0xffd00000)
1797 #define EMMC_B_RESERVED_98_63 (0x41465)
1798 #define P_EMMC_B_RESERVED_98_63 (volatile uint32_t *)((0x41465 << 2) + 0xffd00000)
1799 #define EMMC_B_RESERVED_98_64 (0x41466)
1800 #define P_EMMC_B_RESERVED_98_64 (volatile uint32_t *)((0x41466 << 2) + 0xffd00000)
1801 #define EMMC_B_RESERVED_98_65 (0x41467)
1802 #define P_EMMC_B_RESERVED_98_65 (volatile uint32_t *)((0x41467 << 2) + 0xffd00000)
1803 #define EMMC_B_RESERVED_98_66 (0x41468)
1804 #define P_EMMC_B_RESERVED_98_66 (volatile uint32_t *)((0x41468 << 2) + 0xffd00000)
1805 #define EMMC_B_RESERVED_98_67 (0x41469)
1806 #define P_EMMC_B_RESERVED_98_67 (volatile uint32_t *)((0x41469 << 2) + 0xffd00000)
1807 #define EMMC_B_RESERVED_98_68 (0x4146a)
1808 #define P_EMMC_B_RESERVED_98_68 (volatile uint32_t *)((0x4146a << 2) + 0xffd00000)
1809 #define EMMC_B_RESERVED_98_69 (0x4146b)
1810 #define P_EMMC_B_RESERVED_98_69 (volatile uint32_t *)((0x4146b << 2) + 0xffd00000)
1811 #define EMMC_B_RESERVED_98_70 (0x4146c)
1812 #define P_EMMC_B_RESERVED_98_70 (volatile uint32_t *)((0x4146c << 2) + 0xffd00000)
1813 #define EMMC_B_RESERVED_98_71 (0x4146d)
1814 #define P_EMMC_B_RESERVED_98_71 (volatile uint32_t *)((0x4146d << 2) + 0xffd00000)
1815 #define EMMC_B_RESERVED_98_72 (0x4146e)
1816 #define P_EMMC_B_RESERVED_98_72 (volatile uint32_t *)((0x4146e << 2) + 0xffd00000)
1817 #define EMMC_B_RESERVED_98_73 (0x4146f)
1818 #define P_EMMC_B_RESERVED_98_73 (volatile uint32_t *)((0x4146f << 2) + 0xffd00000)
1819 #define EMMC_B_RESERVED_98_74 (0x41470)
1820 #define P_EMMC_B_RESERVED_98_74 (volatile uint32_t *)((0x41470 << 2) + 0xffd00000)
1821 #define EMMC_B_RESERVED_98_75 (0x41471)
1822 #define P_EMMC_B_RESERVED_98_75 (volatile uint32_t *)((0x41471 << 2) + 0xffd00000)
1823 #define EMMC_B_RESERVED_98_76 (0x41472)
1824 #define P_EMMC_B_RESERVED_98_76 (volatile uint32_t *)((0x41472 << 2) + 0xffd00000)
1825 #define EMMC_B_RESERVED_98_77 (0x41473)
1826 #define P_EMMC_B_RESERVED_98_77 (volatile uint32_t *)((0x41473 << 2) + 0xffd00000)
1827 #define EMMC_B_RESERVED_98_78 (0x41474)
1828 #define P_EMMC_B_RESERVED_98_78 (volatile uint32_t *)((0x41474 << 2) + 0xffd00000)
1829 #define EMMC_B_RESERVED_98_79 (0x41475)
1830 #define P_EMMC_B_RESERVED_98_79 (volatile uint32_t *)((0x41475 << 2) + 0xffd00000)
1831 #define EMMC_B_RESERVED_98_80 (0x41476)
1832 #define P_EMMC_B_RESERVED_98_80 (volatile uint32_t *)((0x41476 << 2) + 0xffd00000)
1833 #define EMMC_B_RESERVED_98_81 (0x41477)
1834 #define P_EMMC_B_RESERVED_98_81 (volatile uint32_t *)((0x41477 << 2) + 0xffd00000)
1835 #define EMMC_B_RESERVED_98_82 (0x41478)
1836 #define P_EMMC_B_RESERVED_98_82 (volatile uint32_t *)((0x41478 << 2) + 0xffd00000)
1837 #define EMMC_B_RESERVED_98_83 (0x41479)
1838 #define P_EMMC_B_RESERVED_98_83 (volatile uint32_t *)((0x41479 << 2) + 0xffd00000)
1839 #define EMMC_B_RESERVED_98_84 (0x4147a)
1840 #define P_EMMC_B_RESERVED_98_84 (volatile uint32_t *)((0x4147a << 2) + 0xffd00000)
1841 #define EMMC_B_RESERVED_98_85 (0x4147b)
1842 #define P_EMMC_B_RESERVED_98_85 (volatile uint32_t *)((0x4147b << 2) + 0xffd00000)
1843 #define EMMC_B_RESERVED_98_86 (0x4147c)
1844 #define P_EMMC_B_RESERVED_98_86 (volatile uint32_t *)((0x4147c << 2) + 0xffd00000)
1845 #define EMMC_B_RESERVED_98_87 (0x4147d)
1846 #define P_EMMC_B_RESERVED_98_87 (volatile uint32_t *)((0x4147d << 2) + 0xffd00000)
1847 #define EMMC_B_RESERVED_98_88 (0x4147e)
1848 #define P_EMMC_B_RESERVED_98_88 (volatile uint32_t *)((0x4147e << 2) + 0xffd00000)
1849 #define EMMC_B_RESERVED_98_89 (0x4147f)
1850 #define P_EMMC_B_RESERVED_98_89 (volatile uint32_t *)((0x4147f << 2) + 0xffd00000)
1851 #define EMMC_B_GDESC_000 (0x41480)
1852 #define P_EMMC_B_GDESC_000 (volatile uint32_t *)((0x41480 << 2) + 0xffd00000)
1853 #define EMMC_B_GDESC_001 (0x41481)
1854 #define P_EMMC_B_GDESC_001 (volatile uint32_t *)((0x41481 << 2) + 0xffd00000)
1855 #define EMMC_B_GDESC_002 (0x41482)
1856 #define P_EMMC_B_GDESC_002 (volatile uint32_t *)((0x41482 << 2) + 0xffd00000)
1857 #define EMMC_B_GDESC_003 (0x41483)
1858 #define P_EMMC_B_GDESC_003 (volatile uint32_t *)((0x41483 << 2) + 0xffd00000)
1859 #define EMMC_B_GDESC_004 (0x41484)
1860 #define P_EMMC_B_GDESC_004 (volatile uint32_t *)((0x41484 << 2) + 0xffd00000)
1861 #define EMMC_B_GDESC_005 (0x41485)
1862 #define P_EMMC_B_GDESC_005 (volatile uint32_t *)((0x41485 << 2) + 0xffd00000)
1863 #define EMMC_B_GDESC_006 (0x41486)
1864 #define P_EMMC_B_GDESC_006 (volatile uint32_t *)((0x41486 << 2) + 0xffd00000)
1865 #define EMMC_B_GDESC_007 (0x41487)
1866 #define P_EMMC_B_GDESC_007 (volatile uint32_t *)((0x41487 << 2) + 0xffd00000)
1867 #define EMMC_B_GDESC_008 (0x41488)
1868 #define P_EMMC_B_GDESC_008 (volatile uint32_t *)((0x41488 << 2) + 0xffd00000)
1869 #define EMMC_B_GDESC_009 (0x41489)
1870 #define P_EMMC_B_GDESC_009 (volatile uint32_t *)((0x41489 << 2) + 0xffd00000)
1871 #define EMMC_B_GDESC_010 (0x4148a)
1872 #define P_EMMC_B_GDESC_010 (volatile uint32_t *)((0x4148a << 2) + 0xffd00000)
1873 #define EMMC_B_GDESC_011 (0x4148b)
1874 #define P_EMMC_B_GDESC_011 (volatile uint32_t *)((0x4148b << 2) + 0xffd00000)
1875 #define EMMC_B_GDESC_012 (0x4148c)
1876 #define P_EMMC_B_GDESC_012 (volatile uint32_t *)((0x4148c << 2) + 0xffd00000)
1877 #define EMMC_B_GDESC_013 (0x4148d)
1878 #define P_EMMC_B_GDESC_013 (volatile uint32_t *)((0x4148d << 2) + 0xffd00000)
1879 #define EMMC_B_GDESC_014 (0x4148e)
1880 #define P_EMMC_B_GDESC_014 (volatile uint32_t *)((0x4148e << 2) + 0xffd00000)
1881 #define EMMC_B_GDESC_015 (0x4148f)
1882 #define P_EMMC_B_GDESC_015 (volatile uint32_t *)((0x4148f << 2) + 0xffd00000)
1883 #define EMMC_B_GDESC_016 (0x41490)
1884 #define P_EMMC_B_GDESC_016 (volatile uint32_t *)((0x41490 << 2) + 0xffd00000)
1885 #define EMMC_B_GDESC_017 (0x41491)
1886 #define P_EMMC_B_GDESC_017 (volatile uint32_t *)((0x41491 << 2) + 0xffd00000)
1887 #define EMMC_B_GDESC_018 (0x41492)
1888 #define P_EMMC_B_GDESC_018 (volatile uint32_t *)((0x41492 << 2) + 0xffd00000)
1889 #define EMMC_B_GDESC_019 (0x41493)
1890 #define P_EMMC_B_GDESC_019 (volatile uint32_t *)((0x41493 << 2) + 0xffd00000)
1891 #define EMMC_B_GDESC_020 (0x41494)
1892 #define P_EMMC_B_GDESC_020 (volatile uint32_t *)((0x41494 << 2) + 0xffd00000)
1893 #define EMMC_B_GDESC_021 (0x41495)
1894 #define P_EMMC_B_GDESC_021 (volatile uint32_t *)((0x41495 << 2) + 0xffd00000)
1895 #define EMMC_B_GDESC_022 (0x41496)
1896 #define P_EMMC_B_GDESC_022 (volatile uint32_t *)((0x41496 << 2) + 0xffd00000)
1897 #define EMMC_B_GDESC_023 (0x41497)
1898 #define P_EMMC_B_GDESC_023 (volatile uint32_t *)((0x41497 << 2) + 0xffd00000)
1899 #define EMMC_B_GDESC_024 (0x41498)
1900 #define P_EMMC_B_GDESC_024 (volatile uint32_t *)((0x41498 << 2) + 0xffd00000)
1901 #define EMMC_B_GDESC_025 (0x41499)
1902 #define P_EMMC_B_GDESC_025 (volatile uint32_t *)((0x41499 << 2) + 0xffd00000)
1903 #define EMMC_B_GDESC_026 (0x4149a)
1904 #define P_EMMC_B_GDESC_026 (volatile uint32_t *)((0x4149a << 2) + 0xffd00000)
1905 #define EMMC_B_GDESC_027 (0x4149b)
1906 #define P_EMMC_B_GDESC_027 (volatile uint32_t *)((0x4149b << 2) + 0xffd00000)
1907 #define EMMC_B_GDESC_028 (0x4149c)
1908 #define P_EMMC_B_GDESC_028 (volatile uint32_t *)((0x4149c << 2) + 0xffd00000)
1909 #define EMMC_B_GDESC_029 (0x4149d)
1910 #define P_EMMC_B_GDESC_029 (volatile uint32_t *)((0x4149d << 2) + 0xffd00000)
1911 #define EMMC_B_GDESC_030 (0x4149e)
1912 #define P_EMMC_B_GDESC_030 (volatile uint32_t *)((0x4149e << 2) + 0xffd00000)
1913 #define EMMC_B_GDESC_031 (0x4149f)
1914 #define P_EMMC_B_GDESC_031 (volatile uint32_t *)((0x4149f << 2) + 0xffd00000)
1915 #define EMMC_B_GDESC_032 (0x414a0)
1916 #define P_EMMC_B_GDESC_032 (volatile uint32_t *)((0x414a0 << 2) + 0xffd00000)
1917 #define EMMC_B_GDESC_033 (0x414a1)
1918 #define P_EMMC_B_GDESC_033 (volatile uint32_t *)((0x414a1 << 2) + 0xffd00000)
1919 #define EMMC_B_GDESC_034 (0x414a2)
1920 #define P_EMMC_B_GDESC_034 (volatile uint32_t *)((0x414a2 << 2) + 0xffd00000)
1921 #define EMMC_B_GDESC_035 (0x414a3)
1922 #define P_EMMC_B_GDESC_035 (volatile uint32_t *)((0x414a3 << 2) + 0xffd00000)
1923 #define EMMC_B_GDESC_036 (0x414a4)
1924 #define P_EMMC_B_GDESC_036 (volatile uint32_t *)((0x414a4 << 2) + 0xffd00000)
1925 #define EMMC_B_GDESC_037 (0x414a5)
1926 #define P_EMMC_B_GDESC_037 (volatile uint32_t *)((0x414a5 << 2) + 0xffd00000)
1927 #define EMMC_B_GDESC_038 (0x414a6)
1928 #define P_EMMC_B_GDESC_038 (volatile uint32_t *)((0x414a6 << 2) + 0xffd00000)
1929 #define EMMC_B_GDESC_039 (0x414a7)
1930 #define P_EMMC_B_GDESC_039 (volatile uint32_t *)((0x414a7 << 2) + 0xffd00000)
1931 #define EMMC_B_GDESC_040 (0x414a8)
1932 #define P_EMMC_B_GDESC_040 (volatile uint32_t *)((0x414a8 << 2) + 0xffd00000)
1933 #define EMMC_B_GDESC_041 (0x414a9)
1934 #define P_EMMC_B_GDESC_041 (volatile uint32_t *)((0x414a9 << 2) + 0xffd00000)
1935 #define EMMC_B_GDESC_042 (0x414aa)
1936 #define P_EMMC_B_GDESC_042 (volatile uint32_t *)((0x414aa << 2) + 0xffd00000)
1937 #define EMMC_B_GDESC_043 (0x414ab)
1938 #define P_EMMC_B_GDESC_043 (volatile uint32_t *)((0x414ab << 2) + 0xffd00000)
1939 #define EMMC_B_GDESC_044 (0x414ac)
1940 #define P_EMMC_B_GDESC_044 (volatile uint32_t *)((0x414ac << 2) + 0xffd00000)
1941 #define EMMC_B_GDESC_045 (0x414ad)
1942 #define P_EMMC_B_GDESC_045 (volatile uint32_t *)((0x414ad << 2) + 0xffd00000)
1943 #define EMMC_B_GDESC_046 (0x414ae)
1944 #define P_EMMC_B_GDESC_046 (volatile uint32_t *)((0x414ae << 2) + 0xffd00000)
1945 #define EMMC_B_GDESC_047 (0x414af)
1946 #define P_EMMC_B_GDESC_047 (volatile uint32_t *)((0x414af << 2) + 0xffd00000)
1947 #define EMMC_B_GDESC_048 (0x414b0)
1948 #define P_EMMC_B_GDESC_048 (volatile uint32_t *)((0x414b0 << 2) + 0xffd00000)
1949 #define EMMC_B_GDESC_049 (0x414b1)
1950 #define P_EMMC_B_GDESC_049 (volatile uint32_t *)((0x414b1 << 2) + 0xffd00000)
1951 #define EMMC_B_GDESC_050 (0x414b2)
1952 #define P_EMMC_B_GDESC_050 (volatile uint32_t *)((0x414b2 << 2) + 0xffd00000)
1953 #define EMMC_B_GDESC_051 (0x414b3)
1954 #define P_EMMC_B_GDESC_051 (volatile uint32_t *)((0x414b3 << 2) + 0xffd00000)
1955 #define EMMC_B_GDESC_052 (0x414b4)
1956 #define P_EMMC_B_GDESC_052 (volatile uint32_t *)((0x414b4 << 2) + 0xffd00000)
1957 #define EMMC_B_GDESC_053 (0x414b5)
1958 #define P_EMMC_B_GDESC_053 (volatile uint32_t *)((0x414b5 << 2) + 0xffd00000)
1959 #define EMMC_B_GDESC_054 (0x414b6)
1960 #define P_EMMC_B_GDESC_054 (volatile uint32_t *)((0x414b6 << 2) + 0xffd00000)
1961 #define EMMC_B_GDESC_055 (0x414b7)
1962 #define P_EMMC_B_GDESC_055 (volatile uint32_t *)((0x414b7 << 2) + 0xffd00000)
1963 #define EMMC_B_GDESC_056 (0x414b8)
1964 #define P_EMMC_B_GDESC_056 (volatile uint32_t *)((0x414b8 << 2) + 0xffd00000)
1965 #define EMMC_B_GDESC_057 (0x414b9)
1966 #define P_EMMC_B_GDESC_057 (volatile uint32_t *)((0x414b9 << 2) + 0xffd00000)
1967 #define EMMC_B_GDESC_058 (0x414ba)
1968 #define P_EMMC_B_GDESC_058 (volatile uint32_t *)((0x414ba << 2) + 0xffd00000)
1969 #define EMMC_B_GDESC_059 (0x414bb)
1970 #define P_EMMC_B_GDESC_059 (volatile uint32_t *)((0x414bb << 2) + 0xffd00000)
1971 #define EMMC_B_GDESC_060 (0x414bc)
1972 #define P_EMMC_B_GDESC_060 (volatile uint32_t *)((0x414bc << 2) + 0xffd00000)
1973 #define EMMC_B_GDESC_061 (0x414bd)
1974 #define P_EMMC_B_GDESC_061 (volatile uint32_t *)((0x414bd << 2) + 0xffd00000)
1975 #define EMMC_B_GDESC_062 (0x414be)
1976 #define P_EMMC_B_GDESC_062 (volatile uint32_t *)((0x414be << 2) + 0xffd00000)
1977 #define EMMC_B_GDESC_063 (0x414bf)
1978 #define P_EMMC_B_GDESC_063 (volatile uint32_t *)((0x414bf << 2) + 0xffd00000)
1979 #define EMMC_B_GDESC_064 (0x414c0)
1980 #define P_EMMC_B_GDESC_064 (volatile uint32_t *)((0x414c0 << 2) + 0xffd00000)
1981 #define EMMC_B_GDESC_065 (0x414c1)
1982 #define P_EMMC_B_GDESC_065 (volatile uint32_t *)((0x414c1 << 2) + 0xffd00000)
1983 #define EMMC_B_GDESC_066 (0x414c2)
1984 #define P_EMMC_B_GDESC_066 (volatile uint32_t *)((0x414c2 << 2) + 0xffd00000)
1985 #define EMMC_B_GDESC_067 (0x414c3)
1986 #define P_EMMC_B_GDESC_067 (volatile uint32_t *)((0x414c3 << 2) + 0xffd00000)
1987 #define EMMC_B_GDESC_068 (0x414c4)
1988 #define P_EMMC_B_GDESC_068 (volatile uint32_t *)((0x414c4 << 2) + 0xffd00000)
1989 #define EMMC_B_GDESC_069 (0x414c5)
1990 #define P_EMMC_B_GDESC_069 (volatile uint32_t *)((0x414c5 << 2) + 0xffd00000)
1991 #define EMMC_B_GDESC_070 (0x414c6)
1992 #define P_EMMC_B_GDESC_070 (volatile uint32_t *)((0x414c6 << 2) + 0xffd00000)
1993 #define EMMC_B_GDESC_071 (0x414c7)
1994 #define P_EMMC_B_GDESC_071 (volatile uint32_t *)((0x414c7 << 2) + 0xffd00000)
1995 #define EMMC_B_GDESC_072 (0x414c8)
1996 #define P_EMMC_B_GDESC_072 (volatile uint32_t *)((0x414c8 << 2) + 0xffd00000)
1997 #define EMMC_B_GDESC_073 (0x414c9)
1998 #define P_EMMC_B_GDESC_073 (volatile uint32_t *)((0x414c9 << 2) + 0xffd00000)
1999 #define EMMC_B_GDESC_074 (0x414ca)
2000 #define P_EMMC_B_GDESC_074 (volatile uint32_t *)((0x414ca << 2) + 0xffd00000)
2001 #define EMMC_B_GDESC_075 (0x414cb)
2002 #define P_EMMC_B_GDESC_075 (volatile uint32_t *)((0x414cb << 2) + 0xffd00000)
2003 #define EMMC_B_GDESC_076 (0x414cc)
2004 #define P_EMMC_B_GDESC_076 (volatile uint32_t *)((0x414cc << 2) + 0xffd00000)
2005 #define EMMC_B_GDESC_077 (0x414cd)
2006 #define P_EMMC_B_GDESC_077 (volatile uint32_t *)((0x414cd << 2) + 0xffd00000)
2007 #define EMMC_B_GDESC_078 (0x414ce)
2008 #define P_EMMC_B_GDESC_078 (volatile uint32_t *)((0x414ce << 2) + 0xffd00000)
2009 #define EMMC_B_GDESC_079 (0x414cf)
2010 #define P_EMMC_B_GDESC_079 (volatile uint32_t *)((0x414cf << 2) + 0xffd00000)
2011 #define EMMC_B_GDESC_080 (0x414d0)
2012 #define P_EMMC_B_GDESC_080 (volatile uint32_t *)((0x414d0 << 2) + 0xffd00000)
2013 #define EMMC_B_GDESC_081 (0x414d1)
2014 #define P_EMMC_B_GDESC_081 (volatile uint32_t *)((0x414d1 << 2) + 0xffd00000)
2015 #define EMMC_B_GDESC_082 (0x414d2)
2016 #define P_EMMC_B_GDESC_082 (volatile uint32_t *)((0x414d2 << 2) + 0xffd00000)
2017 #define EMMC_B_GDESC_083 (0x414d3)
2018 #define P_EMMC_B_GDESC_083 (volatile uint32_t *)((0x414d3 << 2) + 0xffd00000)
2019 #define EMMC_B_GDESC_084 (0x414d4)
2020 #define P_EMMC_B_GDESC_084 (volatile uint32_t *)((0x414d4 << 2) + 0xffd00000)
2021 #define EMMC_B_GDESC_085 (0x414d5)
2022 #define P_EMMC_B_GDESC_085 (volatile uint32_t *)((0x414d5 << 2) + 0xffd00000)
2023 #define EMMC_B_GDESC_086 (0x414d6)
2024 #define P_EMMC_B_GDESC_086 (volatile uint32_t *)((0x414d6 << 2) + 0xffd00000)
2025 #define EMMC_B_GDESC_087 (0x414d7)
2026 #define P_EMMC_B_GDESC_087 (volatile uint32_t *)((0x414d7 << 2) + 0xffd00000)
2027 #define EMMC_B_GDESC_088 (0x414d8)
2028 #define P_EMMC_B_GDESC_088 (volatile uint32_t *)((0x414d8 << 2) + 0xffd00000)
2029 #define EMMC_B_GDESC_089 (0x414d9)
2030 #define P_EMMC_B_GDESC_089 (volatile uint32_t *)((0x414d9 << 2) + 0xffd00000)
2031 #define EMMC_B_GDESC_090 (0x414da)
2032 #define P_EMMC_B_GDESC_090 (volatile uint32_t *)((0x414da << 2) + 0xffd00000)
2033 #define EMMC_B_GDESC_091 (0x414db)
2034 #define P_EMMC_B_GDESC_091 (volatile uint32_t *)((0x414db << 2) + 0xffd00000)
2035 #define EMMC_B_GDESC_092 (0x414dc)
2036 #define P_EMMC_B_GDESC_092 (volatile uint32_t *)((0x414dc << 2) + 0xffd00000)
2037 #define EMMC_B_GDESC_093 (0x414dd)
2038 #define P_EMMC_B_GDESC_093 (volatile uint32_t *)((0x414dd << 2) + 0xffd00000)
2039 #define EMMC_B_GDESC_094 (0x414de)
2040 #define P_EMMC_B_GDESC_094 (volatile uint32_t *)((0x414de << 2) + 0xffd00000)
2041 #define EMMC_B_GDESC_095 (0x414df)
2042 #define P_EMMC_B_GDESC_095 (volatile uint32_t *)((0x414df << 2) + 0xffd00000)
2043 #define EMMC_B_GDESC_096 (0x414e0)
2044 #define P_EMMC_B_GDESC_096 (volatile uint32_t *)((0x414e0 << 2) + 0xffd00000)
2045 #define EMMC_B_GDESC_097 (0x414e1)
2046 #define P_EMMC_B_GDESC_097 (volatile uint32_t *)((0x414e1 << 2) + 0xffd00000)
2047 #define EMMC_B_GDESC_098 (0x414e2)
2048 #define P_EMMC_B_GDESC_098 (volatile uint32_t *)((0x414e2 << 2) + 0xffd00000)
2049 #define EMMC_B_GDESC_099 (0x414e3)
2050 #define P_EMMC_B_GDESC_099 (volatile uint32_t *)((0x414e3 << 2) + 0xffd00000)
2051 #define EMMC_B_GDESC_100 (0x414e4)
2052 #define P_EMMC_B_GDESC_100 (volatile uint32_t *)((0x414e4 << 2) + 0xffd00000)
2053 #define EMMC_B_GDESC_101 (0x414e5)
2054 #define P_EMMC_B_GDESC_101 (volatile uint32_t *)((0x414e5 << 2) + 0xffd00000)
2055 #define EMMC_B_GDESC_102 (0x414e6)
2056 #define P_EMMC_B_GDESC_102 (volatile uint32_t *)((0x414e6 << 2) + 0xffd00000)
2057 #define EMMC_B_GDESC_103 (0x414e7)
2058 #define P_EMMC_B_GDESC_103 (volatile uint32_t *)((0x414e7 << 2) + 0xffd00000)
2059 #define EMMC_B_GDESC_104 (0x414e8)
2060 #define P_EMMC_B_GDESC_104 (volatile uint32_t *)((0x414e8 << 2) + 0xffd00000)
2061 #define EMMC_B_GDESC_105 (0x414e9)
2062 #define P_EMMC_B_GDESC_105 (volatile uint32_t *)((0x414e9 << 2) + 0xffd00000)
2063 #define EMMC_B_GDESC_106 (0x414ea)
2064 #define P_EMMC_B_GDESC_106 (volatile uint32_t *)((0x414ea << 2) + 0xffd00000)
2065 #define EMMC_B_GDESC_107 (0x414eb)
2066 #define P_EMMC_B_GDESC_107 (volatile uint32_t *)((0x414eb << 2) + 0xffd00000)
2067 #define EMMC_B_GDESC_108 (0x414ec)
2068 #define P_EMMC_B_GDESC_108 (volatile uint32_t *)((0x414ec << 2) + 0xffd00000)
2069 #define EMMC_B_GDESC_109 (0x414ed)
2070 #define P_EMMC_B_GDESC_109 (volatile uint32_t *)((0x414ed << 2) + 0xffd00000)
2071 #define EMMC_B_GDESC_110 (0x414ee)
2072 #define P_EMMC_B_GDESC_110 (volatile uint32_t *)((0x414ee << 2) + 0xffd00000)
2073 #define EMMC_B_GDESC_111 (0x414ef)
2074 #define P_EMMC_B_GDESC_111 (volatile uint32_t *)((0x414ef << 2) + 0xffd00000)
2075 #define EMMC_B_GDESC_112 (0x414f0)
2076 #define P_EMMC_B_GDESC_112 (volatile uint32_t *)((0x414f0 << 2) + 0xffd00000)
2077 #define EMMC_B_GDESC_113 (0x414f1)
2078 #define P_EMMC_B_GDESC_113 (volatile uint32_t *)((0x414f1 << 2) + 0xffd00000)
2079 #define EMMC_B_GDESC_114 (0x414f2)
2080 #define P_EMMC_B_GDESC_114 (volatile uint32_t *)((0x414f2 << 2) + 0xffd00000)
2081 #define EMMC_B_GDESC_115 (0x414f3)
2082 #define P_EMMC_B_GDESC_115 (volatile uint32_t *)((0x414f3 << 2) + 0xffd00000)
2083 #define EMMC_B_GDESC_116 (0x414f4)
2084 #define P_EMMC_B_GDESC_116 (volatile uint32_t *)((0x414f4 << 2) + 0xffd00000)
2085 #define EMMC_B_GDESC_117 (0x414f5)
2086 #define P_EMMC_B_GDESC_117 (volatile uint32_t *)((0x414f5 << 2) + 0xffd00000)
2087 #define EMMC_B_GDESC_118 (0x414f6)
2088 #define P_EMMC_B_GDESC_118 (volatile uint32_t *)((0x414f6 << 2) + 0xffd00000)
2089 #define EMMC_B_GDESC_119 (0x414f7)
2090 #define P_EMMC_B_GDESC_119 (volatile uint32_t *)((0x414f7 << 2) + 0xffd00000)
2091 #define EMMC_B_GDESC_120 (0x414f8)
2092 #define P_EMMC_B_GDESC_120 (volatile uint32_t *)((0x414f8 << 2) + 0xffd00000)
2093 #define EMMC_B_GDESC_121 (0x414f9)
2094 #define P_EMMC_B_GDESC_121 (volatile uint32_t *)((0x414f9 << 2) + 0xffd00000)
2095 #define EMMC_B_GDESC_122 (0x414fa)
2096 #define P_EMMC_B_GDESC_122 (volatile uint32_t *)((0x414fa << 2) + 0xffd00000)
2097 #define EMMC_B_GDESC_123 (0x414fb)
2098 #define P_EMMC_B_GDESC_123 (volatile uint32_t *)((0x414fb << 2) + 0xffd00000)
2099 #define EMMC_B_GDESC_124 (0x414fc)
2100 #define P_EMMC_B_GDESC_124 (volatile uint32_t *)((0x414fc << 2) + 0xffd00000)
2101 #define EMMC_B_GDESC_125 (0x414fd)
2102 #define P_EMMC_B_GDESC_125 (volatile uint32_t *)((0x414fd << 2) + 0xffd00000)
2103 #define EMMC_B_GDESC_126 (0x414fe)
2104 #define P_EMMC_B_GDESC_126 (volatile uint32_t *)((0x414fe << 2) + 0xffd00000)
2105 #define EMMC_B_GDESC_127 (0x414ff)
2106 #define P_EMMC_B_GDESC_127 (volatile uint32_t *)((0x414ff << 2) + 0xffd00000)
2107 #define EMMC_B_GPING_000 (0x41500)
2108 #define P_EMMC_B_GPING_000 (volatile uint32_t *)((0x41500 << 2) + 0xffd00000)
2109 #define EMMC_B_GPING_001 (0x41501)
2110 #define P_EMMC_B_GPING_001 (volatile uint32_t *)((0x41501 << 2) + 0xffd00000)
2111 #define EMMC_B_GPING_002 (0x41502)
2112 #define P_EMMC_B_GPING_002 (volatile uint32_t *)((0x41502 << 2) + 0xffd00000)
2113 #define EMMC_B_GPING_003 (0x41503)
2114 #define P_EMMC_B_GPING_003 (volatile uint32_t *)((0x41503 << 2) + 0xffd00000)
2115 #define EMMC_B_GPING_004 (0x41504)
2116 #define P_EMMC_B_GPING_004 (volatile uint32_t *)((0x41504 << 2) + 0xffd00000)
2117 #define EMMC_B_GPING_005 (0x41505)
2118 #define P_EMMC_B_GPING_005 (volatile uint32_t *)((0x41505 << 2) + 0xffd00000)
2119 #define EMMC_B_GPING_006 (0x41506)
2120 #define P_EMMC_B_GPING_006 (volatile uint32_t *)((0x41506 << 2) + 0xffd00000)
2121 #define EMMC_B_GPING_007 (0x41507)
2122 #define P_EMMC_B_GPING_007 (volatile uint32_t *)((0x41507 << 2) + 0xffd00000)
2123 #define EMMC_B_GPING_008 (0x41508)
2124 #define P_EMMC_B_GPING_008 (volatile uint32_t *)((0x41508 << 2) + 0xffd00000)
2125 #define EMMC_B_GPING_009 (0x41509)
2126 #define P_EMMC_B_GPING_009 (volatile uint32_t *)((0x41509 << 2) + 0xffd00000)
2127 #define EMMC_B_GPING_010 (0x4150a)
2128 #define P_EMMC_B_GPING_010 (volatile uint32_t *)((0x4150a << 2) + 0xffd00000)
2129 #define EMMC_B_GPING_011 (0x4150b)
2130 #define P_EMMC_B_GPING_011 (volatile uint32_t *)((0x4150b << 2) + 0xffd00000)
2131 #define EMMC_B_GPING_012 (0x4150c)
2132 #define P_EMMC_B_GPING_012 (volatile uint32_t *)((0x4150c << 2) + 0xffd00000)
2133 #define EMMC_B_GPING_013 (0x4150d)
2134 #define P_EMMC_B_GPING_013 (volatile uint32_t *)((0x4150d << 2) + 0xffd00000)
2135 #define EMMC_B_GPING_014 (0x4150e)
2136 #define P_EMMC_B_GPING_014 (volatile uint32_t *)((0x4150e << 2) + 0xffd00000)
2137 #define EMMC_B_GPING_015 (0x4150f)
2138 #define P_EMMC_B_GPING_015 (volatile uint32_t *)((0x4150f << 2) + 0xffd00000)
2139 #define EMMC_B_GPING_016 (0x41510)
2140 #define P_EMMC_B_GPING_016 (volatile uint32_t *)((0x41510 << 2) + 0xffd00000)
2141 #define EMMC_B_GPING_017 (0x41511)
2142 #define P_EMMC_B_GPING_017 (volatile uint32_t *)((0x41511 << 2) + 0xffd00000)
2143 #define EMMC_B_GPING_018 (0x41512)
2144 #define P_EMMC_B_GPING_018 (volatile uint32_t *)((0x41512 << 2) + 0xffd00000)
2145 #define EMMC_B_GPING_019 (0x41513)
2146 #define P_EMMC_B_GPING_019 (volatile uint32_t *)((0x41513 << 2) + 0xffd00000)
2147 #define EMMC_B_GPING_020 (0x41514)
2148 #define P_EMMC_B_GPING_020 (volatile uint32_t *)((0x41514 << 2) + 0xffd00000)
2149 #define EMMC_B_GPING_021 (0x41515)
2150 #define P_EMMC_B_GPING_021 (volatile uint32_t *)((0x41515 << 2) + 0xffd00000)
2151 #define EMMC_B_GPING_022 (0x41516)
2152 #define P_EMMC_B_GPING_022 (volatile uint32_t *)((0x41516 << 2) + 0xffd00000)
2153 #define EMMC_B_GPING_023 (0x41517)
2154 #define P_EMMC_B_GPING_023 (volatile uint32_t *)((0x41517 << 2) + 0xffd00000)
2155 #define EMMC_B_GPING_024 (0x41518)
2156 #define P_EMMC_B_GPING_024 (volatile uint32_t *)((0x41518 << 2) + 0xffd00000)
2157 #define EMMC_B_GPING_025 (0x41519)
2158 #define P_EMMC_B_GPING_025 (volatile uint32_t *)((0x41519 << 2) + 0xffd00000)
2159 #define EMMC_B_GPING_026 (0x4151a)
2160 #define P_EMMC_B_GPING_026 (volatile uint32_t *)((0x4151a << 2) + 0xffd00000)
2161 #define EMMC_B_GPING_027 (0x4151b)
2162 #define P_EMMC_B_GPING_027 (volatile uint32_t *)((0x4151b << 2) + 0xffd00000)
2163 #define EMMC_B_GPING_028 (0x4151c)
2164 #define P_EMMC_B_GPING_028 (volatile uint32_t *)((0x4151c << 2) + 0xffd00000)
2165 #define EMMC_B_GPING_029 (0x4151d)
2166 #define P_EMMC_B_GPING_029 (volatile uint32_t *)((0x4151d << 2) + 0xffd00000)
2167 #define EMMC_B_GPING_030 (0x4151e)
2168 #define P_EMMC_B_GPING_030 (volatile uint32_t *)((0x4151e << 2) + 0xffd00000)
2169 #define EMMC_B_GPING_031 (0x4151f)
2170 #define P_EMMC_B_GPING_031 (volatile uint32_t *)((0x4151f << 2) + 0xffd00000)
2171 #define EMMC_B_GPING_032 (0x41520)
2172 #define P_EMMC_B_GPING_032 (volatile uint32_t *)((0x41520 << 2) + 0xffd00000)
2173 #define EMMC_B_GPING_033 (0x41521)
2174 #define P_EMMC_B_GPING_033 (volatile uint32_t *)((0x41521 << 2) + 0xffd00000)
2175 #define EMMC_B_GPING_034 (0x41522)
2176 #define P_EMMC_B_GPING_034 (volatile uint32_t *)((0x41522 << 2) + 0xffd00000)
2177 #define EMMC_B_GPING_035 (0x41523)
2178 #define P_EMMC_B_GPING_035 (volatile uint32_t *)((0x41523 << 2) + 0xffd00000)
2179 #define EMMC_B_GPING_036 (0x41524)
2180 #define P_EMMC_B_GPING_036 (volatile uint32_t *)((0x41524 << 2) + 0xffd00000)
2181 #define EMMC_B_GPING_037 (0x41525)
2182 #define P_EMMC_B_GPING_037 (volatile uint32_t *)((0x41525 << 2) + 0xffd00000)
2183 #define EMMC_B_GPING_038 (0x41526)
2184 #define P_EMMC_B_GPING_038 (volatile uint32_t *)((0x41526 << 2) + 0xffd00000)
2185 #define EMMC_B_GPING_039 (0x41527)
2186 #define P_EMMC_B_GPING_039 (volatile uint32_t *)((0x41527 << 2) + 0xffd00000)
2187 #define EMMC_B_GPING_040 (0x41528)
2188 #define P_EMMC_B_GPING_040 (volatile uint32_t *)((0x41528 << 2) + 0xffd00000)
2189 #define EMMC_B_GPING_041 (0x41529)
2190 #define P_EMMC_B_GPING_041 (volatile uint32_t *)((0x41529 << 2) + 0xffd00000)
2191 #define EMMC_B_GPING_042 (0x4152a)
2192 #define P_EMMC_B_GPING_042 (volatile uint32_t *)((0x4152a << 2) + 0xffd00000)
2193 #define EMMC_B_GPING_043 (0x4152b)
2194 #define P_EMMC_B_GPING_043 (volatile uint32_t *)((0x4152b << 2) + 0xffd00000)
2195 #define EMMC_B_GPING_044 (0x4152c)
2196 #define P_EMMC_B_GPING_044 (volatile uint32_t *)((0x4152c << 2) + 0xffd00000)
2197 #define EMMC_B_GPING_045 (0x4152d)
2198 #define P_EMMC_B_GPING_045 (volatile uint32_t *)((0x4152d << 2) + 0xffd00000)
2199 #define EMMC_B_GPING_046 (0x4152e)
2200 #define P_EMMC_B_GPING_046 (volatile uint32_t *)((0x4152e << 2) + 0xffd00000)
2201 #define EMMC_B_GPING_047 (0x4152f)
2202 #define P_EMMC_B_GPING_047 (volatile uint32_t *)((0x4152f << 2) + 0xffd00000)
2203 #define EMMC_B_GPING_048 (0x41530)
2204 #define P_EMMC_B_GPING_048 (volatile uint32_t *)((0x41530 << 2) + 0xffd00000)
2205 #define EMMC_B_GPING_049 (0x41531)
2206 #define P_EMMC_B_GPING_049 (volatile uint32_t *)((0x41531 << 2) + 0xffd00000)
2207 #define EMMC_B_GPING_050 (0x41532)
2208 #define P_EMMC_B_GPING_050 (volatile uint32_t *)((0x41532 << 2) + 0xffd00000)
2209 #define EMMC_B_GPING_051 (0x41533)
2210 #define P_EMMC_B_GPING_051 (volatile uint32_t *)((0x41533 << 2) + 0xffd00000)
2211 #define EMMC_B_GPING_052 (0x41534)
2212 #define P_EMMC_B_GPING_052 (volatile uint32_t *)((0x41534 << 2) + 0xffd00000)
2213 #define EMMC_B_GPING_053 (0x41535)
2214 #define P_EMMC_B_GPING_053 (volatile uint32_t *)((0x41535 << 2) + 0xffd00000)
2215 #define EMMC_B_GPING_054 (0x41536)
2216 #define P_EMMC_B_GPING_054 (volatile uint32_t *)((0x41536 << 2) + 0xffd00000)
2217 #define EMMC_B_GPING_055 (0x41537)
2218 #define P_EMMC_B_GPING_055 (volatile uint32_t *)((0x41537 << 2) + 0xffd00000)
2219 #define EMMC_B_GPING_056 (0x41538)
2220 #define P_EMMC_B_GPING_056 (volatile uint32_t *)((0x41538 << 2) + 0xffd00000)
2221 #define EMMC_B_GPING_057 (0x41539)
2222 #define P_EMMC_B_GPING_057 (volatile uint32_t *)((0x41539 << 2) + 0xffd00000)
2223 #define EMMC_B_GPING_058 (0x4153a)
2224 #define P_EMMC_B_GPING_058 (volatile uint32_t *)((0x4153a << 2) + 0xffd00000)
2225 #define EMMC_B_GPING_059 (0x4153b)
2226 #define P_EMMC_B_GPING_059 (volatile uint32_t *)((0x4153b << 2) + 0xffd00000)
2227 #define EMMC_B_GPING_060 (0x4153c)
2228 #define P_EMMC_B_GPING_060 (volatile uint32_t *)((0x4153c << 2) + 0xffd00000)
2229 #define EMMC_B_GPING_061 (0x4153d)
2230 #define P_EMMC_B_GPING_061 (volatile uint32_t *)((0x4153d << 2) + 0xffd00000)
2231 #define EMMC_B_GPING_062 (0x4153e)
2232 #define P_EMMC_B_GPING_062 (volatile uint32_t *)((0x4153e << 2) + 0xffd00000)
2233 #define EMMC_B_GPING_063 (0x4153f)
2234 #define P_EMMC_B_GPING_063 (volatile uint32_t *)((0x4153f << 2) + 0xffd00000)
2235 #define EMMC_B_GPING_064 (0x41540)
2236 #define P_EMMC_B_GPING_064 (volatile uint32_t *)((0x41540 << 2) + 0xffd00000)
2237 #define EMMC_B_GPING_065 (0x41541)
2238 #define P_EMMC_B_GPING_065 (volatile uint32_t *)((0x41541 << 2) + 0xffd00000)
2239 #define EMMC_B_GPING_066 (0x41542)
2240 #define P_EMMC_B_GPING_066 (volatile uint32_t *)((0x41542 << 2) + 0xffd00000)
2241 #define EMMC_B_GPING_067 (0x41543)
2242 #define P_EMMC_B_GPING_067 (volatile uint32_t *)((0x41543 << 2) + 0xffd00000)
2243 #define EMMC_B_GPING_068 (0x41544)
2244 #define P_EMMC_B_GPING_068 (volatile uint32_t *)((0x41544 << 2) + 0xffd00000)
2245 #define EMMC_B_GPING_069 (0x41545)
2246 #define P_EMMC_B_GPING_069 (volatile uint32_t *)((0x41545 << 2) + 0xffd00000)
2247 #define EMMC_B_GPING_070 (0x41546)
2248 #define P_EMMC_B_GPING_070 (volatile uint32_t *)((0x41546 << 2) + 0xffd00000)
2249 #define EMMC_B_GPING_071 (0x41547)
2250 #define P_EMMC_B_GPING_071 (volatile uint32_t *)((0x41547 << 2) + 0xffd00000)
2251 #define EMMC_B_GPING_072 (0x41548)
2252 #define P_EMMC_B_GPING_072 (volatile uint32_t *)((0x41548 << 2) + 0xffd00000)
2253 #define EMMC_B_GPING_073 (0x41549)
2254 #define P_EMMC_B_GPING_073 (volatile uint32_t *)((0x41549 << 2) + 0xffd00000)
2255 #define EMMC_B_GPING_074 (0x4154a)
2256 #define P_EMMC_B_GPING_074 (volatile uint32_t *)((0x4154a << 2) + 0xffd00000)
2257 #define EMMC_B_GPING_075 (0x4154b)
2258 #define P_EMMC_B_GPING_075 (volatile uint32_t *)((0x4154b << 2) + 0xffd00000)
2259 #define EMMC_B_GPING_076 (0x4154c)
2260 #define P_EMMC_B_GPING_076 (volatile uint32_t *)((0x4154c << 2) + 0xffd00000)
2261 #define EMMC_B_GPING_077 (0x4154d)
2262 #define P_EMMC_B_GPING_077 (volatile uint32_t *)((0x4154d << 2) + 0xffd00000)
2263 #define EMMC_B_GPING_078 (0x4154e)
2264 #define P_EMMC_B_GPING_078 (volatile uint32_t *)((0x4154e << 2) + 0xffd00000)
2265 #define EMMC_B_GPING_079 (0x4154f)
2266 #define P_EMMC_B_GPING_079 (volatile uint32_t *)((0x4154f << 2) + 0xffd00000)
2267 #define EMMC_B_GPING_080 (0x41550)
2268 #define P_EMMC_B_GPING_080 (volatile uint32_t *)((0x41550 << 2) + 0xffd00000)
2269 #define EMMC_B_GPING_081 (0x41551)
2270 #define P_EMMC_B_GPING_081 (volatile uint32_t *)((0x41551 << 2) + 0xffd00000)
2271 #define EMMC_B_GPING_082 (0x41552)
2272 #define P_EMMC_B_GPING_082 (volatile uint32_t *)((0x41552 << 2) + 0xffd00000)
2273 #define EMMC_B_GPING_083 (0x41553)
2274 #define P_EMMC_B_GPING_083 (volatile uint32_t *)((0x41553 << 2) + 0xffd00000)
2275 #define EMMC_B_GPING_084 (0x41554)
2276 #define P_EMMC_B_GPING_084 (volatile uint32_t *)((0x41554 << 2) + 0xffd00000)
2277 #define EMMC_B_GPING_085 (0x41555)
2278 #define P_EMMC_B_GPING_085 (volatile uint32_t *)((0x41555 << 2) + 0xffd00000)
2279 #define EMMC_B_GPING_086 (0x41556)
2280 #define P_EMMC_B_GPING_086 (volatile uint32_t *)((0x41556 << 2) + 0xffd00000)
2281 #define EMMC_B_GPING_087 (0x41557)
2282 #define P_EMMC_B_GPING_087 (volatile uint32_t *)((0x41557 << 2) + 0xffd00000)
2283 #define EMMC_B_GPING_088 (0x41558)
2284 #define P_EMMC_B_GPING_088 (volatile uint32_t *)((0x41558 << 2) + 0xffd00000)
2285 #define EMMC_B_GPING_089 (0x41559)
2286 #define P_EMMC_B_GPING_089 (volatile uint32_t *)((0x41559 << 2) + 0xffd00000)
2287 #define EMMC_B_GPING_090 (0x4155a)
2288 #define P_EMMC_B_GPING_090 (volatile uint32_t *)((0x4155a << 2) + 0xffd00000)
2289 #define EMMC_B_GPING_091 (0x4155b)
2290 #define P_EMMC_B_GPING_091 (volatile uint32_t *)((0x4155b << 2) + 0xffd00000)
2291 #define EMMC_B_GPING_092 (0x4155c)
2292 #define P_EMMC_B_GPING_092 (volatile uint32_t *)((0x4155c << 2) + 0xffd00000)
2293 #define EMMC_B_GPING_093 (0x4155d)
2294 #define P_EMMC_B_GPING_093 (volatile uint32_t *)((0x4155d << 2) + 0xffd00000)
2295 #define EMMC_B_GPING_094 (0x4155e)
2296 #define P_EMMC_B_GPING_094 (volatile uint32_t *)((0x4155e << 2) + 0xffd00000)
2297 #define EMMC_B_GPING_095 (0x4155f)
2298 #define P_EMMC_B_GPING_095 (volatile uint32_t *)((0x4155f << 2) + 0xffd00000)
2299 #define EMMC_B_GPING_096 (0x41560)
2300 #define P_EMMC_B_GPING_096 (volatile uint32_t *)((0x41560 << 2) + 0xffd00000)
2301 #define EMMC_B_GPING_097 (0x41561)
2302 #define P_EMMC_B_GPING_097 (volatile uint32_t *)((0x41561 << 2) + 0xffd00000)
2303 #define EMMC_B_GPING_098 (0x41562)
2304 #define P_EMMC_B_GPING_098 (volatile uint32_t *)((0x41562 << 2) + 0xffd00000)
2305 #define EMMC_B_GPING_099 (0x41563)
2306 #define P_EMMC_B_GPING_099 (volatile uint32_t *)((0x41563 << 2) + 0xffd00000)
2307 #define EMMC_B_GPING_100 (0x41564)
2308 #define P_EMMC_B_GPING_100 (volatile uint32_t *)((0x41564 << 2) + 0xffd00000)
2309 #define EMMC_B_GPING_101 (0x41565)
2310 #define P_EMMC_B_GPING_101 (volatile uint32_t *)((0x41565 << 2) + 0xffd00000)
2311 #define EMMC_B_GPING_102 (0x41566)
2312 #define P_EMMC_B_GPING_102 (volatile uint32_t *)((0x41566 << 2) + 0xffd00000)
2313 #define EMMC_B_GPING_103 (0x41567)
2314 #define P_EMMC_B_GPING_103 (volatile uint32_t *)((0x41567 << 2) + 0xffd00000)
2315 #define EMMC_B_GPING_104 (0x41568)
2316 #define P_EMMC_B_GPING_104 (volatile uint32_t *)((0x41568 << 2) + 0xffd00000)
2317 #define EMMC_B_GPING_105 (0x41569)
2318 #define P_EMMC_B_GPING_105 (volatile uint32_t *)((0x41569 << 2) + 0xffd00000)
2319 #define EMMC_B_GPING_106 (0x4156a)
2320 #define P_EMMC_B_GPING_106 (volatile uint32_t *)((0x4156a << 2) + 0xffd00000)
2321 #define EMMC_B_GPING_107 (0x4156b)
2322 #define P_EMMC_B_GPING_107 (volatile uint32_t *)((0x4156b << 2) + 0xffd00000)
2323 #define EMMC_B_GPING_108 (0x4156c)
2324 #define P_EMMC_B_GPING_108 (volatile uint32_t *)((0x4156c << 2) + 0xffd00000)
2325 #define EMMC_B_GPING_109 (0x4156d)
2326 #define P_EMMC_B_GPING_109 (volatile uint32_t *)((0x4156d << 2) + 0xffd00000)
2327 #define EMMC_B_GPING_110 (0x4156e)
2328 #define P_EMMC_B_GPING_110 (volatile uint32_t *)((0x4156e << 2) + 0xffd00000)
2329 #define EMMC_B_GPING_111 (0x4156f)
2330 #define P_EMMC_B_GPING_111 (volatile uint32_t *)((0x4156f << 2) + 0xffd00000)
2331 #define EMMC_B_GPING_112 (0x41570)
2332 #define P_EMMC_B_GPING_112 (volatile uint32_t *)((0x41570 << 2) + 0xffd00000)
2333 #define EMMC_B_GPING_113 (0x41571)
2334 #define P_EMMC_B_GPING_113 (volatile uint32_t *)((0x41571 << 2) + 0xffd00000)
2335 #define EMMC_B_GPING_114 (0x41572)
2336 #define P_EMMC_B_GPING_114 (volatile uint32_t *)((0x41572 << 2) + 0xffd00000)
2337 #define EMMC_B_GPING_115 (0x41573)
2338 #define P_EMMC_B_GPING_115 (volatile uint32_t *)((0x41573 << 2) + 0xffd00000)
2339 #define EMMC_B_GPING_116 (0x41574)
2340 #define P_EMMC_B_GPING_116 (volatile uint32_t *)((0x41574 << 2) + 0xffd00000)
2341 #define EMMC_B_GPING_117 (0x41575)
2342 #define P_EMMC_B_GPING_117 (volatile uint32_t *)((0x41575 << 2) + 0xffd00000)
2343 #define EMMC_B_GPING_118 (0x41576)
2344 #define P_EMMC_B_GPING_118 (volatile uint32_t *)((0x41576 << 2) + 0xffd00000)
2345 #define EMMC_B_GPING_119 (0x41577)
2346 #define P_EMMC_B_GPING_119 (volatile uint32_t *)((0x41577 << 2) + 0xffd00000)
2347 #define EMMC_B_GPING_120 (0x41578)
2348 #define P_EMMC_B_GPING_120 (volatile uint32_t *)((0x41578 << 2) + 0xffd00000)
2349 #define EMMC_B_GPING_121 (0x41579)
2350 #define P_EMMC_B_GPING_121 (volatile uint32_t *)((0x41579 << 2) + 0xffd00000)
2351 #define EMMC_B_GPING_122 (0x4157a)
2352 #define P_EMMC_B_GPING_122 (volatile uint32_t *)((0x4157a << 2) + 0xffd00000)
2353 #define EMMC_B_GPING_123 (0x4157b)
2354 #define P_EMMC_B_GPING_123 (volatile uint32_t *)((0x4157b << 2) + 0xffd00000)
2355 #define EMMC_B_GPING_124 (0x4157c)
2356 #define P_EMMC_B_GPING_124 (volatile uint32_t *)((0x4157c << 2) + 0xffd00000)
2357 #define EMMC_B_GPING_125 (0x4157d)
2358 #define P_EMMC_B_GPING_125 (volatile uint32_t *)((0x4157d << 2) + 0xffd00000)
2359 #define EMMC_B_GPING_126 (0x4157e)
2360 #define P_EMMC_B_GPING_126 (volatile uint32_t *)((0x4157e << 2) + 0xffd00000)
2361 #define EMMC_B_GPING_127 (0x4157f)
2362 #define P_EMMC_B_GPING_127 (volatile uint32_t *)((0x4157f << 2) + 0xffd00000)
2363 #define EMMC_B_GPONG_000 (0x41580)
2364 #define P_EMMC_B_GPONG_000 (volatile uint32_t *)((0x41580 << 2) + 0xffd00000)
2365 #define EMMC_B_GPONG_001 (0x41581)
2366 #define P_EMMC_B_GPONG_001 (volatile uint32_t *)((0x41581 << 2) + 0xffd00000)
2367 #define EMMC_B_GPONG_002 (0x41582)
2368 #define P_EMMC_B_GPONG_002 (volatile uint32_t *)((0x41582 << 2) + 0xffd00000)
2369 #define EMMC_B_GPONG_003 (0x41583)
2370 #define P_EMMC_B_GPONG_003 (volatile uint32_t *)((0x41583 << 2) + 0xffd00000)
2371 #define EMMC_B_GPONG_004 (0x41584)
2372 #define P_EMMC_B_GPONG_004 (volatile uint32_t *)((0x41584 << 2) + 0xffd00000)
2373 #define EMMC_B_GPONG_005 (0x41585)
2374 #define P_EMMC_B_GPONG_005 (volatile uint32_t *)((0x41585 << 2) + 0xffd00000)
2375 #define EMMC_B_GPONG_006 (0x41586)
2376 #define P_EMMC_B_GPONG_006 (volatile uint32_t *)((0x41586 << 2) + 0xffd00000)
2377 #define EMMC_B_GPONG_007 (0x41587)
2378 #define P_EMMC_B_GPONG_007 (volatile uint32_t *)((0x41587 << 2) + 0xffd00000)
2379 #define EMMC_B_GPONG_008 (0x41588)
2380 #define P_EMMC_B_GPONG_008 (volatile uint32_t *)((0x41588 << 2) + 0xffd00000)
2381 #define EMMC_B_GPONG_009 (0x41589)
2382 #define P_EMMC_B_GPONG_009 (volatile uint32_t *)((0x41589 << 2) + 0xffd00000)
2383 #define EMMC_B_GPONG_010 (0x4158a)
2384 #define P_EMMC_B_GPONG_010 (volatile uint32_t *)((0x4158a << 2) + 0xffd00000)
2385 #define EMMC_B_GPONG_011 (0x4158b)
2386 #define P_EMMC_B_GPONG_011 (volatile uint32_t *)((0x4158b << 2) + 0xffd00000)
2387 #define EMMC_B_GPONG_012 (0x4158c)
2388 #define P_EMMC_B_GPONG_012 (volatile uint32_t *)((0x4158c << 2) + 0xffd00000)
2389 #define EMMC_B_GPONG_013 (0x4158d)
2390 #define P_EMMC_B_GPONG_013 (volatile uint32_t *)((0x4158d << 2) + 0xffd00000)
2391 #define EMMC_B_GPONG_014 (0x4158e)
2392 #define P_EMMC_B_GPONG_014 (volatile uint32_t *)((0x4158e << 2) + 0xffd00000)
2393 #define EMMC_B_GPONG_015 (0x4158f)
2394 #define P_EMMC_B_GPONG_015 (volatile uint32_t *)((0x4158f << 2) + 0xffd00000)
2395 #define EMMC_B_GPONG_016 (0x41590)
2396 #define P_EMMC_B_GPONG_016 (volatile uint32_t *)((0x41590 << 2) + 0xffd00000)
2397 #define EMMC_B_GPONG_017 (0x41591)
2398 #define P_EMMC_B_GPONG_017 (volatile uint32_t *)((0x41591 << 2) + 0xffd00000)
2399 #define EMMC_B_GPONG_018 (0x41592)
2400 #define P_EMMC_B_GPONG_018 (volatile uint32_t *)((0x41592 << 2) + 0xffd00000)
2401 #define EMMC_B_GPONG_019 (0x41593)
2402 #define P_EMMC_B_GPONG_019 (volatile uint32_t *)((0x41593 << 2) + 0xffd00000)
2403 #define EMMC_B_GPONG_020 (0x41594)
2404 #define P_EMMC_B_GPONG_020 (volatile uint32_t *)((0x41594 << 2) + 0xffd00000)
2405 #define EMMC_B_GPONG_021 (0x41595)
2406 #define P_EMMC_B_GPONG_021 (volatile uint32_t *)((0x41595 << 2) + 0xffd00000)
2407 #define EMMC_B_GPONG_022 (0x41596)
2408 #define P_EMMC_B_GPONG_022 (volatile uint32_t *)((0x41596 << 2) + 0xffd00000)
2409 #define EMMC_B_GPONG_023 (0x41597)
2410 #define P_EMMC_B_GPONG_023 (volatile uint32_t *)((0x41597 << 2) + 0xffd00000)
2411 #define EMMC_B_GPONG_024 (0x41598)
2412 #define P_EMMC_B_GPONG_024 (volatile uint32_t *)((0x41598 << 2) + 0xffd00000)
2413 #define EMMC_B_GPONG_025 (0x41599)
2414 #define P_EMMC_B_GPONG_025 (volatile uint32_t *)((0x41599 << 2) + 0xffd00000)
2415 #define EMMC_B_GPONG_026 (0x4159a)
2416 #define P_EMMC_B_GPONG_026 (volatile uint32_t *)((0x4159a << 2) + 0xffd00000)
2417 #define EMMC_B_GPONG_027 (0x4159b)
2418 #define P_EMMC_B_GPONG_027 (volatile uint32_t *)((0x4159b << 2) + 0xffd00000)
2419 #define EMMC_B_GPONG_028 (0x4159c)
2420 #define P_EMMC_B_GPONG_028 (volatile uint32_t *)((0x4159c << 2) + 0xffd00000)
2421 #define EMMC_B_GPONG_029 (0x4159d)
2422 #define P_EMMC_B_GPONG_029 (volatile uint32_t *)((0x4159d << 2) + 0xffd00000)
2423 #define EMMC_B_GPONG_030 (0x4159e)
2424 #define P_EMMC_B_GPONG_030 (volatile uint32_t *)((0x4159e << 2) + 0xffd00000)
2425 #define EMMC_B_GPONG_031 (0x4159f)
2426 #define P_EMMC_B_GPONG_031 (volatile uint32_t *)((0x4159f << 2) + 0xffd00000)
2427 #define EMMC_B_GPONG_032 (0x415a0)
2428 #define P_EMMC_B_GPONG_032 (volatile uint32_t *)((0x415a0 << 2) + 0xffd00000)
2429 #define EMMC_B_GPONG_033 (0x415a1)
2430 #define P_EMMC_B_GPONG_033 (volatile uint32_t *)((0x415a1 << 2) + 0xffd00000)
2431 #define EMMC_B_GPONG_034 (0x415a2)
2432 #define P_EMMC_B_GPONG_034 (volatile uint32_t *)((0x415a2 << 2) + 0xffd00000)
2433 #define EMMC_B_GPONG_035 (0x415a3)
2434 #define P_EMMC_B_GPONG_035 (volatile uint32_t *)((0x415a3 << 2) + 0xffd00000)
2435 #define EMMC_B_GPONG_036 (0x415a4)
2436 #define P_EMMC_B_GPONG_036 (volatile uint32_t *)((0x415a4 << 2) + 0xffd00000)
2437 #define EMMC_B_GPONG_037 (0x415a5)
2438 #define P_EMMC_B_GPONG_037 (volatile uint32_t *)((0x415a5 << 2) + 0xffd00000)
2439 #define EMMC_B_GPONG_038 (0x415a6)
2440 #define P_EMMC_B_GPONG_038 (volatile uint32_t *)((0x415a6 << 2) + 0xffd00000)
2441 #define EMMC_B_GPONG_039 (0x415a7)
2442 #define P_EMMC_B_GPONG_039 (volatile uint32_t *)((0x415a7 << 2) + 0xffd00000)
2443 #define EMMC_B_GPONG_040 (0x415a8)
2444 #define P_EMMC_B_GPONG_040 (volatile uint32_t *)((0x415a8 << 2) + 0xffd00000)
2445 #define EMMC_B_GPONG_041 (0x415a9)
2446 #define P_EMMC_B_GPONG_041 (volatile uint32_t *)((0x415a9 << 2) + 0xffd00000)
2447 #define EMMC_B_GPONG_042 (0x415aa)
2448 #define P_EMMC_B_GPONG_042 (volatile uint32_t *)((0x415aa << 2) + 0xffd00000)
2449 #define EMMC_B_GPONG_043 (0x415ab)
2450 #define P_EMMC_B_GPONG_043 (volatile uint32_t *)((0x415ab << 2) + 0xffd00000)
2451 #define EMMC_B_GPONG_044 (0x415ac)
2452 #define P_EMMC_B_GPONG_044 (volatile uint32_t *)((0x415ac << 2) + 0xffd00000)
2453 #define EMMC_B_GPONG_045 (0x415ad)
2454 #define P_EMMC_B_GPONG_045 (volatile uint32_t *)((0x415ad << 2) + 0xffd00000)
2455 #define EMMC_B_GPONG_046 (0x415ae)
2456 #define P_EMMC_B_GPONG_046 (volatile uint32_t *)((0x415ae << 2) + 0xffd00000)
2457 #define EMMC_B_GPONG_047 (0x415af)
2458 #define P_EMMC_B_GPONG_047 (volatile uint32_t *)((0x415af << 2) + 0xffd00000)
2459 #define EMMC_B_GPONG_048 (0x415b0)
2460 #define P_EMMC_B_GPONG_048 (volatile uint32_t *)((0x415b0 << 2) + 0xffd00000)
2461 #define EMMC_B_GPONG_049 (0x415b1)
2462 #define P_EMMC_B_GPONG_049 (volatile uint32_t *)((0x415b1 << 2) + 0xffd00000)
2463 #define EMMC_B_GPONG_050 (0x415b2)
2464 #define P_EMMC_B_GPONG_050 (volatile uint32_t *)((0x415b2 << 2) + 0xffd00000)
2465 #define EMMC_B_GPONG_051 (0x415b3)
2466 #define P_EMMC_B_GPONG_051 (volatile uint32_t *)((0x415b3 << 2) + 0xffd00000)
2467 #define EMMC_B_GPONG_052 (0x415b4)
2468 #define P_EMMC_B_GPONG_052 (volatile uint32_t *)((0x415b4 << 2) + 0xffd00000)
2469 #define EMMC_B_GPONG_053 (0x415b5)
2470 #define P_EMMC_B_GPONG_053 (volatile uint32_t *)((0x415b5 << 2) + 0xffd00000)
2471 #define EMMC_B_GPONG_054 (0x415b6)
2472 #define P_EMMC_B_GPONG_054 (volatile uint32_t *)((0x415b6 << 2) + 0xffd00000)
2473 #define EMMC_B_GPONG_055 (0x415b7)
2474 #define P_EMMC_B_GPONG_055 (volatile uint32_t *)((0x415b7 << 2) + 0xffd00000)
2475 #define EMMC_B_GPONG_056 (0x415b8)
2476 #define P_EMMC_B_GPONG_056 (volatile uint32_t *)((0x415b8 << 2) + 0xffd00000)
2477 #define EMMC_B_GPONG_057 (0x415b9)
2478 #define P_EMMC_B_GPONG_057 (volatile uint32_t *)((0x415b9 << 2) + 0xffd00000)
2479 #define EMMC_B_GPONG_058 (0x415ba)
2480 #define P_EMMC_B_GPONG_058 (volatile uint32_t *)((0x415ba << 2) + 0xffd00000)
2481 #define EMMC_B_GPONG_059 (0x415bb)
2482 #define P_EMMC_B_GPONG_059 (volatile uint32_t *)((0x415bb << 2) + 0xffd00000)
2483 #define EMMC_B_GPONG_060 (0x415bc)
2484 #define P_EMMC_B_GPONG_060 (volatile uint32_t *)((0x415bc << 2) + 0xffd00000)
2485 #define EMMC_B_GPONG_061 (0x415bd)
2486 #define P_EMMC_B_GPONG_061 (volatile uint32_t *)((0x415bd << 2) + 0xffd00000)
2487 #define EMMC_B_GPONG_062 (0x415be)
2488 #define P_EMMC_B_GPONG_062 (volatile uint32_t *)((0x415be << 2) + 0xffd00000)
2489 #define EMMC_B_GPONG_063 (0x415bf)
2490 #define P_EMMC_B_GPONG_063 (volatile uint32_t *)((0x415bf << 2) + 0xffd00000)
2491 #define EMMC_B_GPONG_064 (0x415c0)
2492 #define P_EMMC_B_GPONG_064 (volatile uint32_t *)((0x415c0 << 2) + 0xffd00000)
2493 #define EMMC_B_GPONG_065 (0x415c1)
2494 #define P_EMMC_B_GPONG_065 (volatile uint32_t *)((0x415c1 << 2) + 0xffd00000)
2495 #define EMMC_B_GPONG_066 (0x415c2)
2496 #define P_EMMC_B_GPONG_066 (volatile uint32_t *)((0x415c2 << 2) + 0xffd00000)
2497 #define EMMC_B_GPONG_067 (0x415c3)
2498 #define P_EMMC_B_GPONG_067 (volatile uint32_t *)((0x415c3 << 2) + 0xffd00000)
2499 #define EMMC_B_GPONG_068 (0x415c4)
2500 #define P_EMMC_B_GPONG_068 (volatile uint32_t *)((0x415c4 << 2) + 0xffd00000)
2501 #define EMMC_B_GPONG_069 (0x415c5)
2502 #define P_EMMC_B_GPONG_069 (volatile uint32_t *)((0x415c5 << 2) + 0xffd00000)
2503 #define EMMC_B_GPONG_070 (0x415c6)
2504 #define P_EMMC_B_GPONG_070 (volatile uint32_t *)((0x415c6 << 2) + 0xffd00000)
2505 #define EMMC_B_GPONG_071 (0x415c7)
2506 #define P_EMMC_B_GPONG_071 (volatile uint32_t *)((0x415c7 << 2) + 0xffd00000)
2507 #define EMMC_B_GPONG_072 (0x415c8)
2508 #define P_EMMC_B_GPONG_072 (volatile uint32_t *)((0x415c8 << 2) + 0xffd00000)
2509 #define EMMC_B_GPONG_073 (0x415c9)
2510 #define P_EMMC_B_GPONG_073 (volatile uint32_t *)((0x415c9 << 2) + 0xffd00000)
2511 #define EMMC_B_GPONG_074 (0x415ca)
2512 #define P_EMMC_B_GPONG_074 (volatile uint32_t *)((0x415ca << 2) + 0xffd00000)
2513 #define EMMC_B_GPONG_075 (0x415cb)
2514 #define P_EMMC_B_GPONG_075 (volatile uint32_t *)((0x415cb << 2) + 0xffd00000)
2515 #define EMMC_B_GPONG_076 (0x415cc)
2516 #define P_EMMC_B_GPONG_076 (volatile uint32_t *)((0x415cc << 2) + 0xffd00000)
2517 #define EMMC_B_GPONG_077 (0x415cd)
2518 #define P_EMMC_B_GPONG_077 (volatile uint32_t *)((0x415cd << 2) + 0xffd00000)
2519 #define EMMC_B_GPONG_078 (0x415ce)
2520 #define P_EMMC_B_GPONG_078 (volatile uint32_t *)((0x415ce << 2) + 0xffd00000)
2521 #define EMMC_B_GPONG_079 (0x415cf)
2522 #define P_EMMC_B_GPONG_079 (volatile uint32_t *)((0x415cf << 2) + 0xffd00000)
2523 #define EMMC_B_GPONG_080 (0x415d0)
2524 #define P_EMMC_B_GPONG_080 (volatile uint32_t *)((0x415d0 << 2) + 0xffd00000)
2525 #define EMMC_B_GPONG_081 (0x415d1)
2526 #define P_EMMC_B_GPONG_081 (volatile uint32_t *)((0x415d1 << 2) + 0xffd00000)
2527 #define EMMC_B_GPONG_082 (0x415d2)
2528 #define P_EMMC_B_GPONG_082 (volatile uint32_t *)((0x415d2 << 2) + 0xffd00000)
2529 #define EMMC_B_GPONG_083 (0x415d3)
2530 #define P_EMMC_B_GPONG_083 (volatile uint32_t *)((0x415d3 << 2) + 0xffd00000)
2531 #define EMMC_B_GPONG_084 (0x415d4)
2532 #define P_EMMC_B_GPONG_084 (volatile uint32_t *)((0x415d4 << 2) + 0xffd00000)
2533 #define EMMC_B_GPONG_085 (0x415d5)
2534 #define P_EMMC_B_GPONG_085 (volatile uint32_t *)((0x415d5 << 2) + 0xffd00000)
2535 #define EMMC_B_GPONG_086 (0x415d6)
2536 #define P_EMMC_B_GPONG_086 (volatile uint32_t *)((0x415d6 << 2) + 0xffd00000)
2537 #define EMMC_B_GPONG_087 (0x415d7)
2538 #define P_EMMC_B_GPONG_087 (volatile uint32_t *)((0x415d7 << 2) + 0xffd00000)
2539 #define EMMC_B_GPONG_088 (0x415d8)
2540 #define P_EMMC_B_GPONG_088 (volatile uint32_t *)((0x415d8 << 2) + 0xffd00000)
2541 #define EMMC_B_GPONG_089 (0x415d9)
2542 #define P_EMMC_B_GPONG_089 (volatile uint32_t *)((0x415d9 << 2) + 0xffd00000)
2543 #define EMMC_B_GPONG_090 (0x415da)
2544 #define P_EMMC_B_GPONG_090 (volatile uint32_t *)((0x415da << 2) + 0xffd00000)
2545 #define EMMC_B_GPONG_091 (0x415db)
2546 #define P_EMMC_B_GPONG_091 (volatile uint32_t *)((0x415db << 2) + 0xffd00000)
2547 #define EMMC_B_GPONG_092 (0x415dc)
2548 #define P_EMMC_B_GPONG_092 (volatile uint32_t *)((0x415dc << 2) + 0xffd00000)
2549 #define EMMC_B_GPONG_093 (0x415dd)
2550 #define P_EMMC_B_GPONG_093 (volatile uint32_t *)((0x415dd << 2) + 0xffd00000)
2551 #define EMMC_B_GPONG_094 (0x415de)
2552 #define P_EMMC_B_GPONG_094 (volatile uint32_t *)((0x415de << 2) + 0xffd00000)
2553 #define EMMC_B_GPONG_095 (0x415df)
2554 #define P_EMMC_B_GPONG_095 (volatile uint32_t *)((0x415df << 2) + 0xffd00000)
2555 #define EMMC_B_GPONG_096 (0x415e0)
2556 #define P_EMMC_B_GPONG_096 (volatile uint32_t *)((0x415e0 << 2) + 0xffd00000)
2557 #define EMMC_B_GPONG_097 (0x415e1)
2558 #define P_EMMC_B_GPONG_097 (volatile uint32_t *)((0x415e1 << 2) + 0xffd00000)
2559 #define EMMC_B_GPONG_098 (0x415e2)
2560 #define P_EMMC_B_GPONG_098 (volatile uint32_t *)((0x415e2 << 2) + 0xffd00000)
2561 #define EMMC_B_GPONG_099 (0x415e3)
2562 #define P_EMMC_B_GPONG_099 (volatile uint32_t *)((0x415e3 << 2) + 0xffd00000)
2563 #define EMMC_B_GPONG_100 (0x415e4)
2564 #define P_EMMC_B_GPONG_100 (volatile uint32_t *)((0x415e4 << 2) + 0xffd00000)
2565 #define EMMC_B_GPONG_101 (0x415e5)
2566 #define P_EMMC_B_GPONG_101 (volatile uint32_t *)((0x415e5 << 2) + 0xffd00000)
2567 #define EMMC_B_GPONG_102 (0x415e6)
2568 #define P_EMMC_B_GPONG_102 (volatile uint32_t *)((0x415e6 << 2) + 0xffd00000)
2569 #define EMMC_B_GPONG_103 (0x415e7)
2570 #define P_EMMC_B_GPONG_103 (volatile uint32_t *)((0x415e7 << 2) + 0xffd00000)
2571 #define EMMC_B_GPONG_104 (0x415e8)
2572 #define P_EMMC_B_GPONG_104 (volatile uint32_t *)((0x415e8 << 2) + 0xffd00000)
2573 #define EMMC_B_GPONG_105 (0x415e9)
2574 #define P_EMMC_B_GPONG_105 (volatile uint32_t *)((0x415e9 << 2) + 0xffd00000)
2575 #define EMMC_B_GPONG_106 (0x415ea)
2576 #define P_EMMC_B_GPONG_106 (volatile uint32_t *)((0x415ea << 2) + 0xffd00000)
2577 #define EMMC_B_GPONG_107 (0x415eb)
2578 #define P_EMMC_B_GPONG_107 (volatile uint32_t *)((0x415eb << 2) + 0xffd00000)
2579 #define EMMC_B_GPONG_108 (0x415ec)
2580 #define P_EMMC_B_GPONG_108 (volatile uint32_t *)((0x415ec << 2) + 0xffd00000)
2581 #define EMMC_B_GPONG_109 (0x415ed)
2582 #define P_EMMC_B_GPONG_109 (volatile uint32_t *)((0x415ed << 2) + 0xffd00000)
2583 #define EMMC_B_GPONG_110 (0x415ee)
2584 #define P_EMMC_B_GPONG_110 (volatile uint32_t *)((0x415ee << 2) + 0xffd00000)
2585 #define EMMC_B_GPONG_111 (0x415ef)
2586 #define P_EMMC_B_GPONG_111 (volatile uint32_t *)((0x415ef << 2) + 0xffd00000)
2587 #define EMMC_B_GPONG_112 (0x415f0)
2588 #define P_EMMC_B_GPONG_112 (volatile uint32_t *)((0x415f0 << 2) + 0xffd00000)
2589 #define EMMC_B_GPONG_113 (0x415f1)
2590 #define P_EMMC_B_GPONG_113 (volatile uint32_t *)((0x415f1 << 2) + 0xffd00000)
2591 #define EMMC_B_GPONG_114 (0x415f2)
2592 #define P_EMMC_B_GPONG_114 (volatile uint32_t *)((0x415f2 << 2) + 0xffd00000)
2593 #define EMMC_B_GPONG_115 (0x415f3)
2594 #define P_EMMC_B_GPONG_115 (volatile uint32_t *)((0x415f3 << 2) + 0xffd00000)
2595 #define EMMC_B_GPONG_116 (0x415f4)
2596 #define P_EMMC_B_GPONG_116 (volatile uint32_t *)((0x415f4 << 2) + 0xffd00000)
2597 #define EMMC_B_GPONG_117 (0x415f5)
2598 #define P_EMMC_B_GPONG_117 (volatile uint32_t *)((0x415f5 << 2) + 0xffd00000)
2599 #define EMMC_B_GPONG_118 (0x415f6)
2600 #define P_EMMC_B_GPONG_118 (volatile uint32_t *)((0x415f6 << 2) + 0xffd00000)
2601 #define EMMC_B_GPONG_119 (0x415f7)
2602 #define P_EMMC_B_GPONG_119 (volatile uint32_t *)((0x415f7 << 2) + 0xffd00000)
2603 #define EMMC_B_GPONG_120 (0x415f8)
2604 #define P_EMMC_B_GPONG_120 (volatile uint32_t *)((0x415f8 << 2) + 0xffd00000)
2605 #define EMMC_B_GPONG_121 (0x415f9)
2606 #define P_EMMC_B_GPONG_121 (volatile uint32_t *)((0x415f9 << 2) + 0xffd00000)
2607 #define EMMC_B_GPONG_122 (0x415fa)
2608 #define P_EMMC_B_GPONG_122 (volatile uint32_t *)((0x415fa << 2) + 0xffd00000)
2609 #define EMMC_B_GPONG_123 (0x415fb)
2610 #define P_EMMC_B_GPONG_123 (volatile uint32_t *)((0x415fb << 2) + 0xffd00000)
2611 #define EMMC_B_GPONG_124 (0x415fc)
2612 #define P_EMMC_B_GPONG_124 (volatile uint32_t *)((0x415fc << 2) + 0xffd00000)
2613 #define EMMC_B_GPONG_125 (0x415fd)
2614 #define P_EMMC_B_GPONG_125 (volatile uint32_t *)((0x415fd << 2) + 0xffd00000)
2615 #define EMMC_B_GPONG_126 (0x415fe)
2616 #define P_EMMC_B_GPONG_126 (volatile uint32_t *)((0x415fe << 2) + 0xffd00000)
2617 #define EMMC_B_GPONG_127 (0x415ff)
2618 #define P_EMMC_B_GPONG_127 (volatile uint32_t *)((0x415ff << 2) + 0xffd00000)
2619 // -----------------------------------------------
2620 // CBUS_BASE: EMMCC_CBUS_BASE = 0x40c
2621 // -----------------------------------------------
2622 #define EMMC_C_GCLOCK (0x40c00)
2623 #define P_EMMC_C_GCLOCK (volatile uint32_t *)((0x40c00 << 2) + 0xffd00000)
2624 #define EMMC_C_GDELAY0 (0x40c01)
2625 #define P_EMMC_C_GDELAY0 (volatile uint32_t *)((0x40c01 << 2) + 0xffd00000)
2626 #define EMMC_C_GDELAY1 (0x40c02)
2627 #define P_EMMC_C_GDELAY1 (volatile uint32_t *)((0x40c02 << 2) + 0xffd00000)
2628 #define EMMC_C_GADJUST (0x40c03)
2629 #define P_EMMC_C_GADJUST (volatile uint32_t *)((0x40c03 << 2) + 0xffd00000)
2630 #define EMMC_C_GCALOUT0 (0x40c04)
2631 #define P_EMMC_C_GCALOUT0 (volatile uint32_t *)((0x40c04 << 2) + 0xffd00000)
2632 #define EMMC_C_GCALOUT1 (0x40c05)
2633 #define P_EMMC_C_GCALOUT1 (volatile uint32_t *)((0x40c05 << 2) + 0xffd00000)
2634 #define EMMC_C_GCALOUT2 (0x40c06)
2635 #define P_EMMC_C_GCALOUT2 (volatile uint32_t *)((0x40c06 << 2) + 0xffd00000)
2636 #define EMMC_C_GCALOUT3 (0x40c07)
2637 #define P_EMMC_C_GCALOUT3 (volatile uint32_t *)((0x40c07 << 2) + 0xffd00000)
2638 #define EMMC_C_GADJ_LOG (0x40c08)
2639 #define P_EMMC_C_GADJ_LOG (volatile uint32_t *)((0x40c08 << 2) + 0xffd00000)
2640 #define EMMC_C_GCLKTEST_LOG (0x40c09)
2641 #define P_EMMC_C_GCLKTEST_LOG (volatile uint32_t *)((0x40c09 << 2) + 0xffd00000)
2642 #define EMMC_C_GCLKTEST_OUT (0x40c0a)
2643 #define P_EMMC_C_GCLKTEST_OUT (volatile uint32_t *)((0x40c0a << 2) + 0xffd00000)
2644 #define EMMC_C_GEYETEST_LOG (0x40c0b)
2645 #define P_EMMC_C_GEYETEST_LOG (volatile uint32_t *)((0x40c0b << 2) + 0xffd00000)
2646 #define EMMC_C_GEYETEST_OUT0 (0x40c0c)
2647 #define P_EMMC_C_GEYETEST_OUT0 (volatile uint32_t *)((0x40c0c << 2) + 0xffd00000)
2648 #define EMMC_C_GEYETEST_OUT1 (0x40c0d)
2649 #define P_EMMC_C_GEYETEST_OUT1 (volatile uint32_t *)((0x40c0d << 2) + 0xffd00000)
2650 #define EMMC_C_GINTF3 (0x40c0e)
2651 #define P_EMMC_C_GINTF3 (volatile uint32_t *)((0x40c0e << 2) + 0xffd00000)
2652 #define EMMC_C_GRESERVE (0x40c0f)
2653 #define P_EMMC_C_GRESERVE (volatile uint32_t *)((0x40c0f << 2) + 0xffd00000)
2654 #define EMMC_C_GSTART (0x40c10)
2655 #define P_EMMC_C_GSTART (volatile uint32_t *)((0x40c10 << 2) + 0xffd00000)
2656 #define EMMC_C_GCFG (0x40c11)
2657 #define P_EMMC_C_GCFG (volatile uint32_t *)((0x40c11 << 2) + 0xffd00000)
2658 #define EMMC_C_GSTATUS (0x40c12)
2659 #define P_EMMC_C_GSTATUS (volatile uint32_t *)((0x40c12 << 2) + 0xffd00000)
2660 #define EMMC_C_GIRQ_EN (0x40c13)
2661 #define P_EMMC_C_GIRQ_EN (volatile uint32_t *)((0x40c13 << 2) + 0xffd00000)
2662 #define EMMC_C_GCMD_CFG (0x40c14)
2663 #define P_EMMC_C_GCMD_CFG (volatile uint32_t *)((0x40c14 << 2) + 0xffd00000)
2664 #define EMMC_C_GCMD_ARG (0x40c15)
2665 #define P_EMMC_C_GCMD_ARG (volatile uint32_t *)((0x40c15 << 2) + 0xffd00000)
2666 #define EMMC_C_GCMD_DAT (0x40c16)
2667 #define P_EMMC_C_GCMD_DAT (volatile uint32_t *)((0x40c16 << 2) + 0xffd00000)
2668 #define EMMC_C_GCMD_RSP (0x40c17)
2669 #define P_EMMC_C_GCMD_RSP (volatile uint32_t *)((0x40c17 << 2) + 0xffd00000)
2670 #define EMMC_C_GCMD_RSP1 (0x40c18)
2671 #define P_EMMC_C_GCMD_RSP1 (volatile uint32_t *)((0x40c18 << 2) + 0xffd00000)
2672 #define EMMC_C_GCMD_RSP2 (0x40c19)
2673 #define P_EMMC_C_GCMD_RSP2 (volatile uint32_t *)((0x40c19 << 2) + 0xffd00000)
2674 #define EMMC_C_GCMD_RSP3 (0x40c1a)
2675 #define P_EMMC_C_GCMD_RSP3 (volatile uint32_t *)((0x40c1a << 2) + 0xffd00000)
2676 #define EMMC_C_RESERVED_6C (0x40c1b)
2677 #define P_EMMC_C_RESERVED_6C (volatile uint32_t *)((0x40c1b << 2) + 0xffd00000)
2678 #define EMMC_C_GCURR_CFG (0x40c1c)
2679 #define P_EMMC_C_GCURR_CFG (volatile uint32_t *)((0x40c1c << 2) + 0xffd00000)
2680 #define EMMC_C_GCURR_ARG (0x40c1d)
2681 #define P_EMMC_C_GCURR_ARG (volatile uint32_t *)((0x40c1d << 2) + 0xffd00000)
2682 #define EMMC_C_GCURR_DAT (0x40c1e)
2683 #define P_EMMC_C_GCURR_DAT (volatile uint32_t *)((0x40c1e << 2) + 0xffd00000)
2684 #define EMMC_C_GCURR_RSP (0x40c1f)
2685 #define P_EMMC_C_GCURR_RSP (volatile uint32_t *)((0x40c1f << 2) + 0xffd00000)
2686 #define EMMC_C_GNEXT_CFG (0x40c20)
2687 #define P_EMMC_C_GNEXT_CFG (volatile uint32_t *)((0x40c20 << 2) + 0xffd00000)
2688 #define EMMC_C_GNEXT_ARG (0x40c21)
2689 #define P_EMMC_C_GNEXT_ARG (volatile uint32_t *)((0x40c21 << 2) + 0xffd00000)
2690 #define EMMC_C_GNEXT_DAT (0x40c22)
2691 #define P_EMMC_C_GNEXT_DAT (volatile uint32_t *)((0x40c22 << 2) + 0xffd00000)
2692 #define EMMC_C_GNEXT_RSP (0x40c23)
2693 #define P_EMMC_C_GNEXT_RSP (volatile uint32_t *)((0x40c23 << 2) + 0xffd00000)
2694 #define EMMC_C_GRXD (0x40c24)
2695 #define P_EMMC_C_GRXD (volatile uint32_t *)((0x40c24 << 2) + 0xffd00000)
2696 #define EMMC_C_GTXD (0x40c25)
2697 #define P_EMMC_C_GTXD (volatile uint32_t *)((0x40c25 << 2) + 0xffd00000)
2698 #define EMMC_C_RESERVED_98_00 (0x40c26)
2699 #define P_EMMC_C_RESERVED_98_00 (volatile uint32_t *)((0x40c26 << 2) + 0xffd00000)
2700 #define EMMC_C_RESERVED_98_01 (0x40c27)
2701 #define P_EMMC_C_RESERVED_98_01 (volatile uint32_t *)((0x40c27 << 2) + 0xffd00000)
2702 #define EMMC_C_RESERVED_98_02 (0x40c28)
2703 #define P_EMMC_C_RESERVED_98_02 (volatile uint32_t *)((0x40c28 << 2) + 0xffd00000)
2704 #define EMMC_C_RESERVED_98_03 (0x40c29)
2705 #define P_EMMC_C_RESERVED_98_03 (volatile uint32_t *)((0x40c29 << 2) + 0xffd00000)
2706 #define EMMC_C_RESERVED_98_04 (0x40c2a)
2707 #define P_EMMC_C_RESERVED_98_04 (volatile uint32_t *)((0x40c2a << 2) + 0xffd00000)
2708 #define EMMC_C_RESERVED_98_05 (0x40c2b)
2709 #define P_EMMC_C_RESERVED_98_05 (volatile uint32_t *)((0x40c2b << 2) + 0xffd00000)
2710 #define EMMC_C_RESERVED_98_06 (0x40c2c)
2711 #define P_EMMC_C_RESERVED_98_06 (volatile uint32_t *)((0x40c2c << 2) + 0xffd00000)
2712 #define EMMC_C_RESERVED_98_07 (0x40c2d)
2713 #define P_EMMC_C_RESERVED_98_07 (volatile uint32_t *)((0x40c2d << 2) + 0xffd00000)
2714 #define EMMC_C_RESERVED_98_08 (0x40c2e)
2715 #define P_EMMC_C_RESERVED_98_08 (volatile uint32_t *)((0x40c2e << 2) + 0xffd00000)
2716 #define EMMC_C_RESERVED_98_09 (0x40c2f)
2717 #define P_EMMC_C_RESERVED_98_09 (volatile uint32_t *)((0x40c2f << 2) + 0xffd00000)
2718 #define EMMC_C_RESERVED_98_10 (0x40c30)
2719 #define P_EMMC_C_RESERVED_98_10 (volatile uint32_t *)((0x40c30 << 2) + 0xffd00000)
2720 #define EMMC_C_RESERVED_98_11 (0x40c31)
2721 #define P_EMMC_C_RESERVED_98_11 (volatile uint32_t *)((0x40c31 << 2) + 0xffd00000)
2722 #define EMMC_C_RESERVED_98_12 (0x40c32)
2723 #define P_EMMC_C_RESERVED_98_12 (volatile uint32_t *)((0x40c32 << 2) + 0xffd00000)
2724 #define EMMC_C_RESERVED_98_13 (0x40c33)
2725 #define P_EMMC_C_RESERVED_98_13 (volatile uint32_t *)((0x40c33 << 2) + 0xffd00000)
2726 #define EMMC_C_RESERVED_98_14 (0x40c34)
2727 #define P_EMMC_C_RESERVED_98_14 (volatile uint32_t *)((0x40c34 << 2) + 0xffd00000)
2728 #define EMMC_C_RESERVED_98_15 (0x40c35)
2729 #define P_EMMC_C_RESERVED_98_15 (volatile uint32_t *)((0x40c35 << 2) + 0xffd00000)
2730 #define EMMC_C_RESERVED_98_16 (0x40c36)
2731 #define P_EMMC_C_RESERVED_98_16 (volatile uint32_t *)((0x40c36 << 2) + 0xffd00000)
2732 #define EMMC_C_RESERVED_98_17 (0x40c37)
2733 #define P_EMMC_C_RESERVED_98_17 (volatile uint32_t *)((0x40c37 << 2) + 0xffd00000)
2734 #define EMMC_C_RESERVED_98_18 (0x40c38)
2735 #define P_EMMC_C_RESERVED_98_18 (volatile uint32_t *)((0x40c38 << 2) + 0xffd00000)
2736 #define EMMC_C_RESERVED_98_19 (0x40c39)
2737 #define P_EMMC_C_RESERVED_98_19 (volatile uint32_t *)((0x40c39 << 2) + 0xffd00000)
2738 #define EMMC_C_RESERVED_98_20 (0x40c3a)
2739 #define P_EMMC_C_RESERVED_98_20 (volatile uint32_t *)((0x40c3a << 2) + 0xffd00000)
2740 #define EMMC_C_RESERVED_98_21 (0x40c3b)
2741 #define P_EMMC_C_RESERVED_98_21 (volatile uint32_t *)((0x40c3b << 2) + 0xffd00000)
2742 #define EMMC_C_RESERVED_98_22 (0x40c3c)
2743 #define P_EMMC_C_RESERVED_98_22 (volatile uint32_t *)((0x40c3c << 2) + 0xffd00000)
2744 #define EMMC_C_RESERVED_98_23 (0x40c3d)
2745 #define P_EMMC_C_RESERVED_98_23 (volatile uint32_t *)((0x40c3d << 2) + 0xffd00000)
2746 #define EMMC_C_RESERVED_98_24 (0x40c3e)
2747 #define P_EMMC_C_RESERVED_98_24 (volatile uint32_t *)((0x40c3e << 2) + 0xffd00000)
2748 #define EMMC_C_RESERVED_98_25 (0x40c3f)
2749 #define P_EMMC_C_RESERVED_98_25 (volatile uint32_t *)((0x40c3f << 2) + 0xffd00000)
2750 #define EMMC_C_RESERVED_98_26 (0x40c40)
2751 #define P_EMMC_C_RESERVED_98_26 (volatile uint32_t *)((0x40c40 << 2) + 0xffd00000)
2752 #define EMMC_C_RESERVED_98_27 (0x40c41)
2753 #define P_EMMC_C_RESERVED_98_27 (volatile uint32_t *)((0x40c41 << 2) + 0xffd00000)
2754 #define EMMC_C_RESERVED_98_28 (0x40c42)
2755 #define P_EMMC_C_RESERVED_98_28 (volatile uint32_t *)((0x40c42 << 2) + 0xffd00000)
2756 #define EMMC_C_RESERVED_98_29 (0x40c43)
2757 #define P_EMMC_C_RESERVED_98_29 (volatile uint32_t *)((0x40c43 << 2) + 0xffd00000)
2758 #define EMMC_C_RESERVED_98_30 (0x40c44)
2759 #define P_EMMC_C_RESERVED_98_30 (volatile uint32_t *)((0x40c44 << 2) + 0xffd00000)
2760 #define EMMC_C_RESERVED_98_31 (0x40c45)
2761 #define P_EMMC_C_RESERVED_98_31 (volatile uint32_t *)((0x40c45 << 2) + 0xffd00000)
2762 #define EMMC_C_RESERVED_98_32 (0x40c46)
2763 #define P_EMMC_C_RESERVED_98_32 (volatile uint32_t *)((0x40c46 << 2) + 0xffd00000)
2764 #define EMMC_C_RESERVED_98_33 (0x40c47)
2765 #define P_EMMC_C_RESERVED_98_33 (volatile uint32_t *)((0x40c47 << 2) + 0xffd00000)
2766 #define EMMC_C_RESERVED_98_34 (0x40c48)
2767 #define P_EMMC_C_RESERVED_98_34 (volatile uint32_t *)((0x40c48 << 2) + 0xffd00000)
2768 #define EMMC_C_RESERVED_98_35 (0x40c49)
2769 #define P_EMMC_C_RESERVED_98_35 (volatile uint32_t *)((0x40c49 << 2) + 0xffd00000)
2770 #define EMMC_C_RESERVED_98_36 (0x40c4a)
2771 #define P_EMMC_C_RESERVED_98_36 (volatile uint32_t *)((0x40c4a << 2) + 0xffd00000)
2772 #define EMMC_C_RESERVED_98_37 (0x40c4b)
2773 #define P_EMMC_C_RESERVED_98_37 (volatile uint32_t *)((0x40c4b << 2) + 0xffd00000)
2774 #define EMMC_C_RESERVED_98_38 (0x40c4c)
2775 #define P_EMMC_C_RESERVED_98_38 (volatile uint32_t *)((0x40c4c << 2) + 0xffd00000)
2776 #define EMMC_C_RESERVED_98_39 (0x40c4d)
2777 #define P_EMMC_C_RESERVED_98_39 (volatile uint32_t *)((0x40c4d << 2) + 0xffd00000)
2778 #define EMMC_C_RESERVED_98_40 (0x40c4e)
2779 #define P_EMMC_C_RESERVED_98_40 (volatile uint32_t *)((0x40c4e << 2) + 0xffd00000)
2780 #define EMMC_C_RESERVED_98_41 (0x40c4f)
2781 #define P_EMMC_C_RESERVED_98_41 (volatile uint32_t *)((0x40c4f << 2) + 0xffd00000)
2782 #define EMMC_C_RESERVED_98_42 (0x40c50)
2783 #define P_EMMC_C_RESERVED_98_42 (volatile uint32_t *)((0x40c50 << 2) + 0xffd00000)
2784 #define EMMC_C_RESERVED_98_43 (0x40c51)
2785 #define P_EMMC_C_RESERVED_98_43 (volatile uint32_t *)((0x40c51 << 2) + 0xffd00000)
2786 #define EMMC_C_RESERVED_98_44 (0x40c52)
2787 #define P_EMMC_C_RESERVED_98_44 (volatile uint32_t *)((0x40c52 << 2) + 0xffd00000)
2788 #define EMMC_C_RESERVED_98_45 (0x40c53)
2789 #define P_EMMC_C_RESERVED_98_45 (volatile uint32_t *)((0x40c53 << 2) + 0xffd00000)
2790 #define EMMC_C_RESERVED_98_46 (0x40c54)
2791 #define P_EMMC_C_RESERVED_98_46 (volatile uint32_t *)((0x40c54 << 2) + 0xffd00000)
2792 #define EMMC_C_RESERVED_98_47 (0x40c55)
2793 #define P_EMMC_C_RESERVED_98_47 (volatile uint32_t *)((0x40c55 << 2) + 0xffd00000)
2794 #define EMMC_C_RESERVED_98_48 (0x40c56)
2795 #define P_EMMC_C_RESERVED_98_48 (volatile uint32_t *)((0x40c56 << 2) + 0xffd00000)
2796 #define EMMC_C_RESERVED_98_49 (0x40c57)
2797 #define P_EMMC_C_RESERVED_98_49 (volatile uint32_t *)((0x40c57 << 2) + 0xffd00000)
2798 #define EMMC_C_RESERVED_98_50 (0x40c58)
2799 #define P_EMMC_C_RESERVED_98_50 (volatile uint32_t *)((0x40c58 << 2) + 0xffd00000)
2800 #define EMMC_C_RESERVED_98_51 (0x40c59)
2801 #define P_EMMC_C_RESERVED_98_51 (volatile uint32_t *)((0x40c59 << 2) + 0xffd00000)
2802 #define EMMC_C_RESERVED_98_52 (0x40c5a)
2803 #define P_EMMC_C_RESERVED_98_52 (volatile uint32_t *)((0x40c5a << 2) + 0xffd00000)
2804 #define EMMC_C_RESERVED_98_53 (0x40c5b)
2805 #define P_EMMC_C_RESERVED_98_53 (volatile uint32_t *)((0x40c5b << 2) + 0xffd00000)
2806 #define EMMC_C_RESERVED_98_54 (0x40c5c)
2807 #define P_EMMC_C_RESERVED_98_54 (volatile uint32_t *)((0x40c5c << 2) + 0xffd00000)
2808 #define EMMC_C_RESERVED_98_55 (0x40c5d)
2809 #define P_EMMC_C_RESERVED_98_55 (volatile uint32_t *)((0x40c5d << 2) + 0xffd00000)
2810 #define EMMC_C_RESERVED_98_56 (0x40c5e)
2811 #define P_EMMC_C_RESERVED_98_56 (volatile uint32_t *)((0x40c5e << 2) + 0xffd00000)
2812 #define EMMC_C_RESERVED_98_57 (0x40c5f)
2813 #define P_EMMC_C_RESERVED_98_57 (volatile uint32_t *)((0x40c5f << 2) + 0xffd00000)
2814 #define EMMC_C_RESERVED_98_58 (0x40c60)
2815 #define P_EMMC_C_RESERVED_98_58 (volatile uint32_t *)((0x40c60 << 2) + 0xffd00000)
2816 #define EMMC_C_RESERVED_98_59 (0x40c61)
2817 #define P_EMMC_C_RESERVED_98_59 (volatile uint32_t *)((0x40c61 << 2) + 0xffd00000)
2818 #define EMMC_C_RESERVED_98_60 (0x40c62)
2819 #define P_EMMC_C_RESERVED_98_60 (volatile uint32_t *)((0x40c62 << 2) + 0xffd00000)
2820 #define EMMC_C_RESERVED_98_61 (0x40c63)
2821 #define P_EMMC_C_RESERVED_98_61 (volatile uint32_t *)((0x40c63 << 2) + 0xffd00000)
2822 #define EMMC_C_RESERVED_98_62 (0x40c64)
2823 #define P_EMMC_C_RESERVED_98_62 (volatile uint32_t *)((0x40c64 << 2) + 0xffd00000)
2824 #define EMMC_C_RESERVED_98_63 (0x40c65)
2825 #define P_EMMC_C_RESERVED_98_63 (volatile uint32_t *)((0x40c65 << 2) + 0xffd00000)
2826 #define EMMC_C_RESERVED_98_64 (0x40c66)
2827 #define P_EMMC_C_RESERVED_98_64 (volatile uint32_t *)((0x40c66 << 2) + 0xffd00000)
2828 #define EMMC_C_RESERVED_98_65 (0x40c67)
2829 #define P_EMMC_C_RESERVED_98_65 (volatile uint32_t *)((0x40c67 << 2) + 0xffd00000)
2830 #define EMMC_C_RESERVED_98_66 (0x40c68)
2831 #define P_EMMC_C_RESERVED_98_66 (volatile uint32_t *)((0x40c68 << 2) + 0xffd00000)
2832 #define EMMC_C_RESERVED_98_67 (0x40c69)
2833 #define P_EMMC_C_RESERVED_98_67 (volatile uint32_t *)((0x40c69 << 2) + 0xffd00000)
2834 #define EMMC_C_RESERVED_98_68 (0x40c6a)
2835 #define P_EMMC_C_RESERVED_98_68 (volatile uint32_t *)((0x40c6a << 2) + 0xffd00000)
2836 #define EMMC_C_RESERVED_98_69 (0x40c6b)
2837 #define P_EMMC_C_RESERVED_98_69 (volatile uint32_t *)((0x40c6b << 2) + 0xffd00000)
2838 #define EMMC_C_RESERVED_98_70 (0x40c6c)
2839 #define P_EMMC_C_RESERVED_98_70 (volatile uint32_t *)((0x40c6c << 2) + 0xffd00000)
2840 #define EMMC_C_RESERVED_98_71 (0x40c6d)
2841 #define P_EMMC_C_RESERVED_98_71 (volatile uint32_t *)((0x40c6d << 2) + 0xffd00000)
2842 #define EMMC_C_RESERVED_98_72 (0x40c6e)
2843 #define P_EMMC_C_RESERVED_98_72 (volatile uint32_t *)((0x40c6e << 2) + 0xffd00000)
2844 #define EMMC_C_RESERVED_98_73 (0x40c6f)
2845 #define P_EMMC_C_RESERVED_98_73 (volatile uint32_t *)((0x40c6f << 2) + 0xffd00000)
2846 #define EMMC_C_RESERVED_98_74 (0x40c70)
2847 #define P_EMMC_C_RESERVED_98_74 (volatile uint32_t *)((0x40c70 << 2) + 0xffd00000)
2848 #define EMMC_C_RESERVED_98_75 (0x40c71)
2849 #define P_EMMC_C_RESERVED_98_75 (volatile uint32_t *)((0x40c71 << 2) + 0xffd00000)
2850 #define EMMC_C_RESERVED_98_76 (0x40c72)
2851 #define P_EMMC_C_RESERVED_98_76 (volatile uint32_t *)((0x40c72 << 2) + 0xffd00000)
2852 #define EMMC_C_RESERVED_98_77 (0x40c73)
2853 #define P_EMMC_C_RESERVED_98_77 (volatile uint32_t *)((0x40c73 << 2) + 0xffd00000)
2854 #define EMMC_C_RESERVED_98_78 (0x40c74)
2855 #define P_EMMC_C_RESERVED_98_78 (volatile uint32_t *)((0x40c74 << 2) + 0xffd00000)
2856 #define EMMC_C_RESERVED_98_79 (0x40c75)
2857 #define P_EMMC_C_RESERVED_98_79 (volatile uint32_t *)((0x40c75 << 2) + 0xffd00000)
2858 #define EMMC_C_RESERVED_98_80 (0x40c76)
2859 #define P_EMMC_C_RESERVED_98_80 (volatile uint32_t *)((0x40c76 << 2) + 0xffd00000)
2860 #define EMMC_C_RESERVED_98_81 (0x40c77)
2861 #define P_EMMC_C_RESERVED_98_81 (volatile uint32_t *)((0x40c77 << 2) + 0xffd00000)
2862 #define EMMC_C_RESERVED_98_82 (0x40c78)
2863 #define P_EMMC_C_RESERVED_98_82 (volatile uint32_t *)((0x40c78 << 2) + 0xffd00000)
2864 #define EMMC_C_RESERVED_98_83 (0x40c79)
2865 #define P_EMMC_C_RESERVED_98_83 (volatile uint32_t *)((0x40c79 << 2) + 0xffd00000)
2866 #define EMMC_C_RESERVED_98_84 (0x40c7a)
2867 #define P_EMMC_C_RESERVED_98_84 (volatile uint32_t *)((0x40c7a << 2) + 0xffd00000)
2868 #define EMMC_C_RESERVED_98_85 (0x40c7b)
2869 #define P_EMMC_C_RESERVED_98_85 (volatile uint32_t *)((0x40c7b << 2) + 0xffd00000)
2870 #define EMMC_C_RESERVED_98_86 (0x40c7c)
2871 #define P_EMMC_C_RESERVED_98_86 (volatile uint32_t *)((0x40c7c << 2) + 0xffd00000)
2872 #define EMMC_C_RESERVED_98_87 (0x40c7d)
2873 #define P_EMMC_C_RESERVED_98_87 (volatile uint32_t *)((0x40c7d << 2) + 0xffd00000)
2874 #define EMMC_C_RESERVED_98_88 (0x40c7e)
2875 #define P_EMMC_C_RESERVED_98_88 (volatile uint32_t *)((0x40c7e << 2) + 0xffd00000)
2876 #define EMMC_C_RESERVED_98_89 (0x40c7f)
2877 #define P_EMMC_C_RESERVED_98_89 (volatile uint32_t *)((0x40c7f << 2) + 0xffd00000)
2878 #define EMMC_C_GDESC_000 (0x40c80)
2879 #define P_EMMC_C_GDESC_000 (volatile uint32_t *)((0x40c80 << 2) + 0xffd00000)
2880 #define EMMC_C_GDESC_001 (0x40c81)
2881 #define P_EMMC_C_GDESC_001 (volatile uint32_t *)((0x40c81 << 2) + 0xffd00000)
2882 #define EMMC_C_GDESC_002 (0x40c82)
2883 #define P_EMMC_C_GDESC_002 (volatile uint32_t *)((0x40c82 << 2) + 0xffd00000)
2884 #define EMMC_C_GDESC_003 (0x40c83)
2885 #define P_EMMC_C_GDESC_003 (volatile uint32_t *)((0x40c83 << 2) + 0xffd00000)
2886 #define EMMC_C_GDESC_004 (0x40c84)
2887 #define P_EMMC_C_GDESC_004 (volatile uint32_t *)((0x40c84 << 2) + 0xffd00000)
2888 #define EMMC_C_GDESC_005 (0x40c85)
2889 #define P_EMMC_C_GDESC_005 (volatile uint32_t *)((0x40c85 << 2) + 0xffd00000)
2890 #define EMMC_C_GDESC_006 (0x40c86)
2891 #define P_EMMC_C_GDESC_006 (volatile uint32_t *)((0x40c86 << 2) + 0xffd00000)
2892 #define EMMC_C_GDESC_007 (0x40c87)
2893 #define P_EMMC_C_GDESC_007 (volatile uint32_t *)((0x40c87 << 2) + 0xffd00000)
2894 #define EMMC_C_GDESC_008 (0x40c88)
2895 #define P_EMMC_C_GDESC_008 (volatile uint32_t *)((0x40c88 << 2) + 0xffd00000)
2896 #define EMMC_C_GDESC_009 (0x40c89)
2897 #define P_EMMC_C_GDESC_009 (volatile uint32_t *)((0x40c89 << 2) + 0xffd00000)
2898 #define EMMC_C_GDESC_010 (0x40c8a)
2899 #define P_EMMC_C_GDESC_010 (volatile uint32_t *)((0x40c8a << 2) + 0xffd00000)
2900 #define EMMC_C_GDESC_011 (0x40c8b)
2901 #define P_EMMC_C_GDESC_011 (volatile uint32_t *)((0x40c8b << 2) + 0xffd00000)
2902 #define EMMC_C_GDESC_012 (0x40c8c)
2903 #define P_EMMC_C_GDESC_012 (volatile uint32_t *)((0x40c8c << 2) + 0xffd00000)
2904 #define EMMC_C_GDESC_013 (0x40c8d)
2905 #define P_EMMC_C_GDESC_013 (volatile uint32_t *)((0x40c8d << 2) + 0xffd00000)
2906 #define EMMC_C_GDESC_014 (0x40c8e)
2907 #define P_EMMC_C_GDESC_014 (volatile uint32_t *)((0x40c8e << 2) + 0xffd00000)
2908 #define EMMC_C_GDESC_015 (0x40c8f)
2909 #define P_EMMC_C_GDESC_015 (volatile uint32_t *)((0x40c8f << 2) + 0xffd00000)
2910 #define EMMC_C_GDESC_016 (0x40c90)
2911 #define P_EMMC_C_GDESC_016 (volatile uint32_t *)((0x40c90 << 2) + 0xffd00000)
2912 #define EMMC_C_GDESC_017 (0x40c91)
2913 #define P_EMMC_C_GDESC_017 (volatile uint32_t *)((0x40c91 << 2) + 0xffd00000)
2914 #define EMMC_C_GDESC_018 (0x40c92)
2915 #define P_EMMC_C_GDESC_018 (volatile uint32_t *)((0x40c92 << 2) + 0xffd00000)
2916 #define EMMC_C_GDESC_019 (0x40c93)
2917 #define P_EMMC_C_GDESC_019 (volatile uint32_t *)((0x40c93 << 2) + 0xffd00000)
2918 #define EMMC_C_GDESC_020 (0x40c94)
2919 #define P_EMMC_C_GDESC_020 (volatile uint32_t *)((0x40c94 << 2) + 0xffd00000)
2920 #define EMMC_C_GDESC_021 (0x40c95)
2921 #define P_EMMC_C_GDESC_021 (volatile uint32_t *)((0x40c95 << 2) + 0xffd00000)
2922 #define EMMC_C_GDESC_022 (0x40c96)
2923 #define P_EMMC_C_GDESC_022 (volatile uint32_t *)((0x40c96 << 2) + 0xffd00000)
2924 #define EMMC_C_GDESC_023 (0x40c97)
2925 #define P_EMMC_C_GDESC_023 (volatile uint32_t *)((0x40c97 << 2) + 0xffd00000)
2926 #define EMMC_C_GDESC_024 (0x40c98)
2927 #define P_EMMC_C_GDESC_024 (volatile uint32_t *)((0x40c98 << 2) + 0xffd00000)
2928 #define EMMC_C_GDESC_025 (0x40c99)
2929 #define P_EMMC_C_GDESC_025 (volatile uint32_t *)((0x40c99 << 2) + 0xffd00000)
2930 #define EMMC_C_GDESC_026 (0x40c9a)
2931 #define P_EMMC_C_GDESC_026 (volatile uint32_t *)((0x40c9a << 2) + 0xffd00000)
2932 #define EMMC_C_GDESC_027 (0x40c9b)
2933 #define P_EMMC_C_GDESC_027 (volatile uint32_t *)((0x40c9b << 2) + 0xffd00000)
2934 #define EMMC_C_GDESC_028 (0x40c9c)
2935 #define P_EMMC_C_GDESC_028 (volatile uint32_t *)((0x40c9c << 2) + 0xffd00000)
2936 #define EMMC_C_GDESC_029 (0x40c9d)
2937 #define P_EMMC_C_GDESC_029 (volatile uint32_t *)((0x40c9d << 2) + 0xffd00000)
2938 #define EMMC_C_GDESC_030 (0x40c9e)
2939 #define P_EMMC_C_GDESC_030 (volatile uint32_t *)((0x40c9e << 2) + 0xffd00000)
2940 #define EMMC_C_GDESC_031 (0x40c9f)
2941 #define P_EMMC_C_GDESC_031 (volatile uint32_t *)((0x40c9f << 2) + 0xffd00000)
2942 #define EMMC_C_GDESC_032 (0x40ca0)
2943 #define P_EMMC_C_GDESC_032 (volatile uint32_t *)((0x40ca0 << 2) + 0xffd00000)
2944 #define EMMC_C_GDESC_033 (0x40ca1)
2945 #define P_EMMC_C_GDESC_033 (volatile uint32_t *)((0x40ca1 << 2) + 0xffd00000)
2946 #define EMMC_C_GDESC_034 (0x40ca2)
2947 #define P_EMMC_C_GDESC_034 (volatile uint32_t *)((0x40ca2 << 2) + 0xffd00000)
2948 #define EMMC_C_GDESC_035 (0x40ca3)
2949 #define P_EMMC_C_GDESC_035 (volatile uint32_t *)((0x40ca3 << 2) + 0xffd00000)
2950 #define EMMC_C_GDESC_036 (0x40ca4)
2951 #define P_EMMC_C_GDESC_036 (volatile uint32_t *)((0x40ca4 << 2) + 0xffd00000)
2952 #define EMMC_C_GDESC_037 (0x40ca5)
2953 #define P_EMMC_C_GDESC_037 (volatile uint32_t *)((0x40ca5 << 2) + 0xffd00000)
2954 #define EMMC_C_GDESC_038 (0x40ca6)
2955 #define P_EMMC_C_GDESC_038 (volatile uint32_t *)((0x40ca6 << 2) + 0xffd00000)
2956 #define EMMC_C_GDESC_039 (0x40ca7)
2957 #define P_EMMC_C_GDESC_039 (volatile uint32_t *)((0x40ca7 << 2) + 0xffd00000)
2958 #define EMMC_C_GDESC_040 (0x40ca8)
2959 #define P_EMMC_C_GDESC_040 (volatile uint32_t *)((0x40ca8 << 2) + 0xffd00000)
2960 #define EMMC_C_GDESC_041 (0x40ca9)
2961 #define P_EMMC_C_GDESC_041 (volatile uint32_t *)((0x40ca9 << 2) + 0xffd00000)
2962 #define EMMC_C_GDESC_042 (0x40caa)
2963 #define P_EMMC_C_GDESC_042 (volatile uint32_t *)((0x40caa << 2) + 0xffd00000)
2964 #define EMMC_C_GDESC_043 (0x40cab)
2965 #define P_EMMC_C_GDESC_043 (volatile uint32_t *)((0x40cab << 2) + 0xffd00000)
2966 #define EMMC_C_GDESC_044 (0x40cac)
2967 #define P_EMMC_C_GDESC_044 (volatile uint32_t *)((0x40cac << 2) + 0xffd00000)
2968 #define EMMC_C_GDESC_045 (0x40cad)
2969 #define P_EMMC_C_GDESC_045 (volatile uint32_t *)((0x40cad << 2) + 0xffd00000)
2970 #define EMMC_C_GDESC_046 (0x40cae)
2971 #define P_EMMC_C_GDESC_046 (volatile uint32_t *)((0x40cae << 2) + 0xffd00000)
2972 #define EMMC_C_GDESC_047 (0x40caf)
2973 #define P_EMMC_C_GDESC_047 (volatile uint32_t *)((0x40caf << 2) + 0xffd00000)
2974 #define EMMC_C_GDESC_048 (0x40cb0)
2975 #define P_EMMC_C_GDESC_048 (volatile uint32_t *)((0x40cb0 << 2) + 0xffd00000)
2976 #define EMMC_C_GDESC_049 (0x40cb1)
2977 #define P_EMMC_C_GDESC_049 (volatile uint32_t *)((0x40cb1 << 2) + 0xffd00000)
2978 #define EMMC_C_GDESC_050 (0x40cb2)
2979 #define P_EMMC_C_GDESC_050 (volatile uint32_t *)((0x40cb2 << 2) + 0xffd00000)
2980 #define EMMC_C_GDESC_051 (0x40cb3)
2981 #define P_EMMC_C_GDESC_051 (volatile uint32_t *)((0x40cb3 << 2) + 0xffd00000)
2982 #define EMMC_C_GDESC_052 (0x40cb4)
2983 #define P_EMMC_C_GDESC_052 (volatile uint32_t *)((0x40cb4 << 2) + 0xffd00000)
2984 #define EMMC_C_GDESC_053 (0x40cb5)
2985 #define P_EMMC_C_GDESC_053 (volatile uint32_t *)((0x40cb5 << 2) + 0xffd00000)
2986 #define EMMC_C_GDESC_054 (0x40cb6)
2987 #define P_EMMC_C_GDESC_054 (volatile uint32_t *)((0x40cb6 << 2) + 0xffd00000)
2988 #define EMMC_C_GDESC_055 (0x40cb7)
2989 #define P_EMMC_C_GDESC_055 (volatile uint32_t *)((0x40cb7 << 2) + 0xffd00000)
2990 #define EMMC_C_GDESC_056 (0x40cb8)
2991 #define P_EMMC_C_GDESC_056 (volatile uint32_t *)((0x40cb8 << 2) + 0xffd00000)
2992 #define EMMC_C_GDESC_057 (0x40cb9)
2993 #define P_EMMC_C_GDESC_057 (volatile uint32_t *)((0x40cb9 << 2) + 0xffd00000)
2994 #define EMMC_C_GDESC_058 (0x40cba)
2995 #define P_EMMC_C_GDESC_058 (volatile uint32_t *)((0x40cba << 2) + 0xffd00000)
2996 #define EMMC_C_GDESC_059 (0x40cbb)
2997 #define P_EMMC_C_GDESC_059 (volatile uint32_t *)((0x40cbb << 2) + 0xffd00000)
2998 #define EMMC_C_GDESC_060 (0x40cbc)
2999 #define P_EMMC_C_GDESC_060 (volatile uint32_t *)((0x40cbc << 2) + 0xffd00000)
3000 #define EMMC_C_GDESC_061 (0x40cbd)
3001 #define P_EMMC_C_GDESC_061 (volatile uint32_t *)((0x40cbd << 2) + 0xffd00000)
3002 #define EMMC_C_GDESC_062 (0x40cbe)
3003 #define P_EMMC_C_GDESC_062 (volatile uint32_t *)((0x40cbe << 2) + 0xffd00000)
3004 #define EMMC_C_GDESC_063 (0x40cbf)
3005 #define P_EMMC_C_GDESC_063 (volatile uint32_t *)((0x40cbf << 2) + 0xffd00000)
3006 #define EMMC_C_GDESC_064 (0x40cc0)
3007 #define P_EMMC_C_GDESC_064 (volatile uint32_t *)((0x40cc0 << 2) + 0xffd00000)
3008 #define EMMC_C_GDESC_065 (0x40cc1)
3009 #define P_EMMC_C_GDESC_065 (volatile uint32_t *)((0x40cc1 << 2) + 0xffd00000)
3010 #define EMMC_C_GDESC_066 (0x40cc2)
3011 #define P_EMMC_C_GDESC_066 (volatile uint32_t *)((0x40cc2 << 2) + 0xffd00000)
3012 #define EMMC_C_GDESC_067 (0x40cc3)
3013 #define P_EMMC_C_GDESC_067 (volatile uint32_t *)((0x40cc3 << 2) + 0xffd00000)
3014 #define EMMC_C_GDESC_068 (0x40cc4)
3015 #define P_EMMC_C_GDESC_068 (volatile uint32_t *)((0x40cc4 << 2) + 0xffd00000)
3016 #define EMMC_C_GDESC_069 (0x40cc5)
3017 #define P_EMMC_C_GDESC_069 (volatile uint32_t *)((0x40cc5 << 2) + 0xffd00000)
3018 #define EMMC_C_GDESC_070 (0x40cc6)
3019 #define P_EMMC_C_GDESC_070 (volatile uint32_t *)((0x40cc6 << 2) + 0xffd00000)
3020 #define EMMC_C_GDESC_071 (0x40cc7)
3021 #define P_EMMC_C_GDESC_071 (volatile uint32_t *)((0x40cc7 << 2) + 0xffd00000)
3022 #define EMMC_C_GDESC_072 (0x40cc8)
3023 #define P_EMMC_C_GDESC_072 (volatile uint32_t *)((0x40cc8 << 2) + 0xffd00000)
3024 #define EMMC_C_GDESC_073 (0x40cc9)
3025 #define P_EMMC_C_GDESC_073 (volatile uint32_t *)((0x40cc9 << 2) + 0xffd00000)
3026 #define EMMC_C_GDESC_074 (0x40cca)
3027 #define P_EMMC_C_GDESC_074 (volatile uint32_t *)((0x40cca << 2) + 0xffd00000)
3028 #define EMMC_C_GDESC_075 (0x40ccb)
3029 #define P_EMMC_C_GDESC_075 (volatile uint32_t *)((0x40ccb << 2) + 0xffd00000)
3030 #define EMMC_C_GDESC_076 (0x40ccc)
3031 #define P_EMMC_C_GDESC_076 (volatile uint32_t *)((0x40ccc << 2) + 0xffd00000)
3032 #define EMMC_C_GDESC_077 (0x40ccd)
3033 #define P_EMMC_C_GDESC_077 (volatile uint32_t *)((0x40ccd << 2) + 0xffd00000)
3034 #define EMMC_C_GDESC_078 (0x40cce)
3035 #define P_EMMC_C_GDESC_078 (volatile uint32_t *)((0x40cce << 2) + 0xffd00000)
3036 #define EMMC_C_GDESC_079 (0x40ccf)
3037 #define P_EMMC_C_GDESC_079 (volatile uint32_t *)((0x40ccf << 2) + 0xffd00000)
3038 #define EMMC_C_GDESC_080 (0x40cd0)
3039 #define P_EMMC_C_GDESC_080 (volatile uint32_t *)((0x40cd0 << 2) + 0xffd00000)
3040 #define EMMC_C_GDESC_081 (0x40cd1)
3041 #define P_EMMC_C_GDESC_081 (volatile uint32_t *)((0x40cd1 << 2) + 0xffd00000)
3042 #define EMMC_C_GDESC_082 (0x40cd2)
3043 #define P_EMMC_C_GDESC_082 (volatile uint32_t *)((0x40cd2 << 2) + 0xffd00000)
3044 #define EMMC_C_GDESC_083 (0x40cd3)
3045 #define P_EMMC_C_GDESC_083 (volatile uint32_t *)((0x40cd3 << 2) + 0xffd00000)
3046 #define EMMC_C_GDESC_084 (0x40cd4)
3047 #define P_EMMC_C_GDESC_084 (volatile uint32_t *)((0x40cd4 << 2) + 0xffd00000)
3048 #define EMMC_C_GDESC_085 (0x40cd5)
3049 #define P_EMMC_C_GDESC_085 (volatile uint32_t *)((0x40cd5 << 2) + 0xffd00000)
3050 #define EMMC_C_GDESC_086 (0x40cd6)
3051 #define P_EMMC_C_GDESC_086 (volatile uint32_t *)((0x40cd6 << 2) + 0xffd00000)
3052 #define EMMC_C_GDESC_087 (0x40cd7)
3053 #define P_EMMC_C_GDESC_087 (volatile uint32_t *)((0x40cd7 << 2) + 0xffd00000)
3054 #define EMMC_C_GDESC_088 (0x40cd8)
3055 #define P_EMMC_C_GDESC_088 (volatile uint32_t *)((0x40cd8 << 2) + 0xffd00000)
3056 #define EMMC_C_GDESC_089 (0x40cd9)
3057 #define P_EMMC_C_GDESC_089 (volatile uint32_t *)((0x40cd9 << 2) + 0xffd00000)
3058 #define EMMC_C_GDESC_090 (0x40cda)
3059 #define P_EMMC_C_GDESC_090 (volatile uint32_t *)((0x40cda << 2) + 0xffd00000)
3060 #define EMMC_C_GDESC_091 (0x40cdb)
3061 #define P_EMMC_C_GDESC_091 (volatile uint32_t *)((0x40cdb << 2) + 0xffd00000)
3062 #define EMMC_C_GDESC_092 (0x40cdc)
3063 #define P_EMMC_C_GDESC_092 (volatile uint32_t *)((0x40cdc << 2) + 0xffd00000)
3064 #define EMMC_C_GDESC_093 (0x40cdd)
3065 #define P_EMMC_C_GDESC_093 (volatile uint32_t *)((0x40cdd << 2) + 0xffd00000)
3066 #define EMMC_C_GDESC_094 (0x40cde)
3067 #define P_EMMC_C_GDESC_094 (volatile uint32_t *)((0x40cde << 2) + 0xffd00000)
3068 #define EMMC_C_GDESC_095 (0x40cdf)
3069 #define P_EMMC_C_GDESC_095 (volatile uint32_t *)((0x40cdf << 2) + 0xffd00000)
3070 #define EMMC_C_GDESC_096 (0x40ce0)
3071 #define P_EMMC_C_GDESC_096 (volatile uint32_t *)((0x40ce0 << 2) + 0xffd00000)
3072 #define EMMC_C_GDESC_097 (0x40ce1)
3073 #define P_EMMC_C_GDESC_097 (volatile uint32_t *)((0x40ce1 << 2) + 0xffd00000)
3074 #define EMMC_C_GDESC_098 (0x40ce2)
3075 #define P_EMMC_C_GDESC_098 (volatile uint32_t *)((0x40ce2 << 2) + 0xffd00000)
3076 #define EMMC_C_GDESC_099 (0x40ce3)
3077 #define P_EMMC_C_GDESC_099 (volatile uint32_t *)((0x40ce3 << 2) + 0xffd00000)
3078 #define EMMC_C_GDESC_100 (0x40ce4)
3079 #define P_EMMC_C_GDESC_100 (volatile uint32_t *)((0x40ce4 << 2) + 0xffd00000)
3080 #define EMMC_C_GDESC_101 (0x40ce5)
3081 #define P_EMMC_C_GDESC_101 (volatile uint32_t *)((0x40ce5 << 2) + 0xffd00000)
3082 #define EMMC_C_GDESC_102 (0x40ce6)
3083 #define P_EMMC_C_GDESC_102 (volatile uint32_t *)((0x40ce6 << 2) + 0xffd00000)
3084 #define EMMC_C_GDESC_103 (0x40ce7)
3085 #define P_EMMC_C_GDESC_103 (volatile uint32_t *)((0x40ce7 << 2) + 0xffd00000)
3086 #define EMMC_C_GDESC_104 (0x40ce8)
3087 #define P_EMMC_C_GDESC_104 (volatile uint32_t *)((0x40ce8 << 2) + 0xffd00000)
3088 #define EMMC_C_GDESC_105 (0x40ce9)
3089 #define P_EMMC_C_GDESC_105 (volatile uint32_t *)((0x40ce9 << 2) + 0xffd00000)
3090 #define EMMC_C_GDESC_106 (0x40cea)
3091 #define P_EMMC_C_GDESC_106 (volatile uint32_t *)((0x40cea << 2) + 0xffd00000)
3092 #define EMMC_C_GDESC_107 (0x40ceb)
3093 #define P_EMMC_C_GDESC_107 (volatile uint32_t *)((0x40ceb << 2) + 0xffd00000)
3094 #define EMMC_C_GDESC_108 (0x40cec)
3095 #define P_EMMC_C_GDESC_108 (volatile uint32_t *)((0x40cec << 2) + 0xffd00000)
3096 #define EMMC_C_GDESC_109 (0x40ced)
3097 #define P_EMMC_C_GDESC_109 (volatile uint32_t *)((0x40ced << 2) + 0xffd00000)
3098 #define EMMC_C_GDESC_110 (0x40cee)
3099 #define P_EMMC_C_GDESC_110 (volatile uint32_t *)((0x40cee << 2) + 0xffd00000)
3100 #define EMMC_C_GDESC_111 (0x40cef)
3101 #define P_EMMC_C_GDESC_111 (volatile uint32_t *)((0x40cef << 2) + 0xffd00000)
3102 #define EMMC_C_GDESC_112 (0x40cf0)
3103 #define P_EMMC_C_GDESC_112 (volatile uint32_t *)((0x40cf0 << 2) + 0xffd00000)
3104 #define EMMC_C_GDESC_113 (0x40cf1)
3105 #define P_EMMC_C_GDESC_113 (volatile uint32_t *)((0x40cf1 << 2) + 0xffd00000)
3106 #define EMMC_C_GDESC_114 (0x40cf2)
3107 #define P_EMMC_C_GDESC_114 (volatile uint32_t *)((0x40cf2 << 2) + 0xffd00000)
3108 #define EMMC_C_GDESC_115 (0x40cf3)
3109 #define P_EMMC_C_GDESC_115 (volatile uint32_t *)((0x40cf3 << 2) + 0xffd00000)
3110 #define EMMC_C_GDESC_116 (0x40cf4)
3111 #define P_EMMC_C_GDESC_116 (volatile uint32_t *)((0x40cf4 << 2) + 0xffd00000)
3112 #define EMMC_C_GDESC_117 (0x40cf5)
3113 #define P_EMMC_C_GDESC_117 (volatile uint32_t *)((0x40cf5 << 2) + 0xffd00000)
3114 #define EMMC_C_GDESC_118 (0x40cf6)
3115 #define P_EMMC_C_GDESC_118 (volatile uint32_t *)((0x40cf6 << 2) + 0xffd00000)
3116 #define EMMC_C_GDESC_119 (0x40cf7)
3117 #define P_EMMC_C_GDESC_119 (volatile uint32_t *)((0x40cf7 << 2) + 0xffd00000)
3118 #define EMMC_C_GDESC_120 (0x40cf8)
3119 #define P_EMMC_C_GDESC_120 (volatile uint32_t *)((0x40cf8 << 2) + 0xffd00000)
3120 #define EMMC_C_GDESC_121 (0x40cf9)
3121 #define P_EMMC_C_GDESC_121 (volatile uint32_t *)((0x40cf9 << 2) + 0xffd00000)
3122 #define EMMC_C_GDESC_122 (0x40cfa)
3123 #define P_EMMC_C_GDESC_122 (volatile uint32_t *)((0x40cfa << 2) + 0xffd00000)
3124 #define EMMC_C_GDESC_123 (0x40cfb)
3125 #define P_EMMC_C_GDESC_123 (volatile uint32_t *)((0x40cfb << 2) + 0xffd00000)
3126 #define EMMC_C_GDESC_124 (0x40cfc)
3127 #define P_EMMC_C_GDESC_124 (volatile uint32_t *)((0x40cfc << 2) + 0xffd00000)
3128 #define EMMC_C_GDESC_125 (0x40cfd)
3129 #define P_EMMC_C_GDESC_125 (volatile uint32_t *)((0x40cfd << 2) + 0xffd00000)
3130 #define EMMC_C_GDESC_126 (0x40cfe)
3131 #define P_EMMC_C_GDESC_126 (volatile uint32_t *)((0x40cfe << 2) + 0xffd00000)
3132 #define EMMC_C_GDESC_127 (0x40cff)
3133 #define P_EMMC_C_GDESC_127 (volatile uint32_t *)((0x40cff << 2) + 0xffd00000)
3134 #define EMMC_C_GPING_000 (0x40d00)
3135 #define P_EMMC_C_GPING_000 (volatile uint32_t *)((0x40d00 << 2) + 0xffd00000)
3136 #define EMMC_C_GPING_001 (0x40d01)
3137 #define P_EMMC_C_GPING_001 (volatile uint32_t *)((0x40d01 << 2) + 0xffd00000)
3138 #define EMMC_C_GPING_002 (0x40d02)
3139 #define P_EMMC_C_GPING_002 (volatile uint32_t *)((0x40d02 << 2) + 0xffd00000)
3140 #define EMMC_C_GPING_003 (0x40d03)
3141 #define P_EMMC_C_GPING_003 (volatile uint32_t *)((0x40d03 << 2) + 0xffd00000)
3142 #define EMMC_C_GPING_004 (0x40d04)
3143 #define P_EMMC_C_GPING_004 (volatile uint32_t *)((0x40d04 << 2) + 0xffd00000)
3144 #define EMMC_C_GPING_005 (0x40d05)
3145 #define P_EMMC_C_GPING_005 (volatile uint32_t *)((0x40d05 << 2) + 0xffd00000)
3146 #define EMMC_C_GPING_006 (0x40d06)
3147 #define P_EMMC_C_GPING_006 (volatile uint32_t *)((0x40d06 << 2) + 0xffd00000)
3148 #define EMMC_C_GPING_007 (0x40d07)
3149 #define P_EMMC_C_GPING_007 (volatile uint32_t *)((0x40d07 << 2) + 0xffd00000)
3150 #define EMMC_C_GPING_008 (0x40d08)
3151 #define P_EMMC_C_GPING_008 (volatile uint32_t *)((0x40d08 << 2) + 0xffd00000)
3152 #define EMMC_C_GPING_009 (0x40d09)
3153 #define P_EMMC_C_GPING_009 (volatile uint32_t *)((0x40d09 << 2) + 0xffd00000)
3154 #define EMMC_C_GPING_010 (0x40d0a)
3155 #define P_EMMC_C_GPING_010 (volatile uint32_t *)((0x40d0a << 2) + 0xffd00000)
3156 #define EMMC_C_GPING_011 (0x40d0b)
3157 #define P_EMMC_C_GPING_011 (volatile uint32_t *)((0x40d0b << 2) + 0xffd00000)
3158 #define EMMC_C_GPING_012 (0x40d0c)
3159 #define P_EMMC_C_GPING_012 (volatile uint32_t *)((0x40d0c << 2) + 0xffd00000)
3160 #define EMMC_C_GPING_013 (0x40d0d)
3161 #define P_EMMC_C_GPING_013 (volatile uint32_t *)((0x40d0d << 2) + 0xffd00000)
3162 #define EMMC_C_GPING_014 (0x40d0e)
3163 #define P_EMMC_C_GPING_014 (volatile uint32_t *)((0x40d0e << 2) + 0xffd00000)
3164 #define EMMC_C_GPING_015 (0x40d0f)
3165 #define P_EMMC_C_GPING_015 (volatile uint32_t *)((0x40d0f << 2) + 0xffd00000)
3166 #define EMMC_C_GPING_016 (0x40d10)
3167 #define P_EMMC_C_GPING_016 (volatile uint32_t *)((0x40d10 << 2) + 0xffd00000)
3168 #define EMMC_C_GPING_017 (0x40d11)
3169 #define P_EMMC_C_GPING_017 (volatile uint32_t *)((0x40d11 << 2) + 0xffd00000)
3170 #define EMMC_C_GPING_018 (0x40d12)
3171 #define P_EMMC_C_GPING_018 (volatile uint32_t *)((0x40d12 << 2) + 0xffd00000)
3172 #define EMMC_C_GPING_019 (0x40d13)
3173 #define P_EMMC_C_GPING_019 (volatile uint32_t *)((0x40d13 << 2) + 0xffd00000)
3174 #define EMMC_C_GPING_020 (0x40d14)
3175 #define P_EMMC_C_GPING_020 (volatile uint32_t *)((0x40d14 << 2) + 0xffd00000)
3176 #define EMMC_C_GPING_021 (0x40d15)
3177 #define P_EMMC_C_GPING_021 (volatile uint32_t *)((0x40d15 << 2) + 0xffd00000)
3178 #define EMMC_C_GPING_022 (0x40d16)
3179 #define P_EMMC_C_GPING_022 (volatile uint32_t *)((0x40d16 << 2) + 0xffd00000)
3180 #define EMMC_C_GPING_023 (0x40d17)
3181 #define P_EMMC_C_GPING_023 (volatile uint32_t *)((0x40d17 << 2) + 0xffd00000)
3182 #define EMMC_C_GPING_024 (0x40d18)
3183 #define P_EMMC_C_GPING_024 (volatile uint32_t *)((0x40d18 << 2) + 0xffd00000)
3184 #define EMMC_C_GPING_025 (0x40d19)
3185 #define P_EMMC_C_GPING_025 (volatile uint32_t *)((0x40d19 << 2) + 0xffd00000)
3186 #define EMMC_C_GPING_026 (0x40d1a)
3187 #define P_EMMC_C_GPING_026 (volatile uint32_t *)((0x40d1a << 2) + 0xffd00000)
3188 #define EMMC_C_GPING_027 (0x40d1b)
3189 #define P_EMMC_C_GPING_027 (volatile uint32_t *)((0x40d1b << 2) + 0xffd00000)
3190 #define EMMC_C_GPING_028 (0x40d1c)
3191 #define P_EMMC_C_GPING_028 (volatile uint32_t *)((0x40d1c << 2) + 0xffd00000)
3192 #define EMMC_C_GPING_029 (0x40d1d)
3193 #define P_EMMC_C_GPING_029 (volatile uint32_t *)((0x40d1d << 2) + 0xffd00000)
3194 #define EMMC_C_GPING_030 (0x40d1e)
3195 #define P_EMMC_C_GPING_030 (volatile uint32_t *)((0x40d1e << 2) + 0xffd00000)
3196 #define EMMC_C_GPING_031 (0x40d1f)
3197 #define P_EMMC_C_GPING_031 (volatile uint32_t *)((0x40d1f << 2) + 0xffd00000)
3198 #define EMMC_C_GPING_032 (0x40d20)
3199 #define P_EMMC_C_GPING_032 (volatile uint32_t *)((0x40d20 << 2) + 0xffd00000)
3200 #define EMMC_C_GPING_033 (0x40d21)
3201 #define P_EMMC_C_GPING_033 (volatile uint32_t *)((0x40d21 << 2) + 0xffd00000)
3202 #define EMMC_C_GPING_034 (0x40d22)
3203 #define P_EMMC_C_GPING_034 (volatile uint32_t *)((0x40d22 << 2) + 0xffd00000)
3204 #define EMMC_C_GPING_035 (0x40d23)
3205 #define P_EMMC_C_GPING_035 (volatile uint32_t *)((0x40d23 << 2) + 0xffd00000)
3206 #define EMMC_C_GPING_036 (0x40d24)
3207 #define P_EMMC_C_GPING_036 (volatile uint32_t *)((0x40d24 << 2) + 0xffd00000)
3208 #define EMMC_C_GPING_037 (0x40d25)
3209 #define P_EMMC_C_GPING_037 (volatile uint32_t *)((0x40d25 << 2) + 0xffd00000)
3210 #define EMMC_C_GPING_038 (0x40d26)
3211 #define P_EMMC_C_GPING_038 (volatile uint32_t *)((0x40d26 << 2) + 0xffd00000)
3212 #define EMMC_C_GPING_039 (0x40d27)
3213 #define P_EMMC_C_GPING_039 (volatile uint32_t *)((0x40d27 << 2) + 0xffd00000)
3214 #define EMMC_C_GPING_040 (0x40d28)
3215 #define P_EMMC_C_GPING_040 (volatile uint32_t *)((0x40d28 << 2) + 0xffd00000)
3216 #define EMMC_C_GPING_041 (0x40d29)
3217 #define P_EMMC_C_GPING_041 (volatile uint32_t *)((0x40d29 << 2) + 0xffd00000)
3218 #define EMMC_C_GPING_042 (0x40d2a)
3219 #define P_EMMC_C_GPING_042 (volatile uint32_t *)((0x40d2a << 2) + 0xffd00000)
3220 #define EMMC_C_GPING_043 (0x40d2b)
3221 #define P_EMMC_C_GPING_043 (volatile uint32_t *)((0x40d2b << 2) + 0xffd00000)
3222 #define EMMC_C_GPING_044 (0x40d2c)
3223 #define P_EMMC_C_GPING_044 (volatile uint32_t *)((0x40d2c << 2) + 0xffd00000)
3224 #define EMMC_C_GPING_045 (0x40d2d)
3225 #define P_EMMC_C_GPING_045 (volatile uint32_t *)((0x40d2d << 2) + 0xffd00000)
3226 #define EMMC_C_GPING_046 (0x40d2e)
3227 #define P_EMMC_C_GPING_046 (volatile uint32_t *)((0x40d2e << 2) + 0xffd00000)
3228 #define EMMC_C_GPING_047 (0x40d2f)
3229 #define P_EMMC_C_GPING_047 (volatile uint32_t *)((0x40d2f << 2) + 0xffd00000)
3230 #define EMMC_C_GPING_048 (0x40d30)
3231 #define P_EMMC_C_GPING_048 (volatile uint32_t *)((0x40d30 << 2) + 0xffd00000)
3232 #define EMMC_C_GPING_049 (0x40d31)
3233 #define P_EMMC_C_GPING_049 (volatile uint32_t *)((0x40d31 << 2) + 0xffd00000)
3234 #define EMMC_C_GPING_050 (0x40d32)
3235 #define P_EMMC_C_GPING_050 (volatile uint32_t *)((0x40d32 << 2) + 0xffd00000)
3236 #define EMMC_C_GPING_051 (0x40d33)
3237 #define P_EMMC_C_GPING_051 (volatile uint32_t *)((0x40d33 << 2) + 0xffd00000)
3238 #define EMMC_C_GPING_052 (0x40d34)
3239 #define P_EMMC_C_GPING_052 (volatile uint32_t *)((0x40d34 << 2) + 0xffd00000)
3240 #define EMMC_C_GPING_053 (0x40d35)
3241 #define P_EMMC_C_GPING_053 (volatile uint32_t *)((0x40d35 << 2) + 0xffd00000)
3242 #define EMMC_C_GPING_054 (0x40d36)
3243 #define P_EMMC_C_GPING_054 (volatile uint32_t *)((0x40d36 << 2) + 0xffd00000)
3244 #define EMMC_C_GPING_055 (0x40d37)
3245 #define P_EMMC_C_GPING_055 (volatile uint32_t *)((0x40d37 << 2) + 0xffd00000)
3246 #define EMMC_C_GPING_056 (0x40d38)
3247 #define P_EMMC_C_GPING_056 (volatile uint32_t *)((0x40d38 << 2) + 0xffd00000)
3248 #define EMMC_C_GPING_057 (0x40d39)
3249 #define P_EMMC_C_GPING_057 (volatile uint32_t *)((0x40d39 << 2) + 0xffd00000)
3250 #define EMMC_C_GPING_058 (0x40d3a)
3251 #define P_EMMC_C_GPING_058 (volatile uint32_t *)((0x40d3a << 2) + 0xffd00000)
3252 #define EMMC_C_GPING_059 (0x40d3b)
3253 #define P_EMMC_C_GPING_059 (volatile uint32_t *)((0x40d3b << 2) + 0xffd00000)
3254 #define EMMC_C_GPING_060 (0x40d3c)
3255 #define P_EMMC_C_GPING_060 (volatile uint32_t *)((0x40d3c << 2) + 0xffd00000)
3256 #define EMMC_C_GPING_061 (0x40d3d)
3257 #define P_EMMC_C_GPING_061 (volatile uint32_t *)((0x40d3d << 2) + 0xffd00000)
3258 #define EMMC_C_GPING_062 (0x40d3e)
3259 #define P_EMMC_C_GPING_062 (volatile uint32_t *)((0x40d3e << 2) + 0xffd00000)
3260 #define EMMC_C_GPING_063 (0x40d3f)
3261 #define P_EMMC_C_GPING_063 (volatile uint32_t *)((0x40d3f << 2) + 0xffd00000)
3262 #define EMMC_C_GPING_064 (0x40d40)
3263 #define P_EMMC_C_GPING_064 (volatile uint32_t *)((0x40d40 << 2) + 0xffd00000)
3264 #define EMMC_C_GPING_065 (0x40d41)
3265 #define P_EMMC_C_GPING_065 (volatile uint32_t *)((0x40d41 << 2) + 0xffd00000)
3266 #define EMMC_C_GPING_066 (0x40d42)
3267 #define P_EMMC_C_GPING_066 (volatile uint32_t *)((0x40d42 << 2) + 0xffd00000)
3268 #define EMMC_C_GPING_067 (0x40d43)
3269 #define P_EMMC_C_GPING_067 (volatile uint32_t *)((0x40d43 << 2) + 0xffd00000)
3270 #define EMMC_C_GPING_068 (0x40d44)
3271 #define P_EMMC_C_GPING_068 (volatile uint32_t *)((0x40d44 << 2) + 0xffd00000)
3272 #define EMMC_C_GPING_069 (0x40d45)
3273 #define P_EMMC_C_GPING_069 (volatile uint32_t *)((0x40d45 << 2) + 0xffd00000)
3274 #define EMMC_C_GPING_070 (0x40d46)
3275 #define P_EMMC_C_GPING_070 (volatile uint32_t *)((0x40d46 << 2) + 0xffd00000)
3276 #define EMMC_C_GPING_071 (0x40d47)
3277 #define P_EMMC_C_GPING_071 (volatile uint32_t *)((0x40d47 << 2) + 0xffd00000)
3278 #define EMMC_C_GPING_072 (0x40d48)
3279 #define P_EMMC_C_GPING_072 (volatile uint32_t *)((0x40d48 << 2) + 0xffd00000)
3280 #define EMMC_C_GPING_073 (0x40d49)
3281 #define P_EMMC_C_GPING_073 (volatile uint32_t *)((0x40d49 << 2) + 0xffd00000)
3282 #define EMMC_C_GPING_074 (0x40d4a)
3283 #define P_EMMC_C_GPING_074 (volatile uint32_t *)((0x40d4a << 2) + 0xffd00000)
3284 #define EMMC_C_GPING_075 (0x40d4b)
3285 #define P_EMMC_C_GPING_075 (volatile uint32_t *)((0x40d4b << 2) + 0xffd00000)
3286 #define EMMC_C_GPING_076 (0x40d4c)
3287 #define P_EMMC_C_GPING_076 (volatile uint32_t *)((0x40d4c << 2) + 0xffd00000)
3288 #define EMMC_C_GPING_077 (0x40d4d)
3289 #define P_EMMC_C_GPING_077 (volatile uint32_t *)((0x40d4d << 2) + 0xffd00000)
3290 #define EMMC_C_GPING_078 (0x40d4e)
3291 #define P_EMMC_C_GPING_078 (volatile uint32_t *)((0x40d4e << 2) + 0xffd00000)
3292 #define EMMC_C_GPING_079 (0x40d4f)
3293 #define P_EMMC_C_GPING_079 (volatile uint32_t *)((0x40d4f << 2) + 0xffd00000)
3294 #define EMMC_C_GPING_080 (0x40d50)
3295 #define P_EMMC_C_GPING_080 (volatile uint32_t *)((0x40d50 << 2) + 0xffd00000)
3296 #define EMMC_C_GPING_081 (0x40d51)
3297 #define P_EMMC_C_GPING_081 (volatile uint32_t *)((0x40d51 << 2) + 0xffd00000)
3298 #define EMMC_C_GPING_082 (0x40d52)
3299 #define P_EMMC_C_GPING_082 (volatile uint32_t *)((0x40d52 << 2) + 0xffd00000)
3300 #define EMMC_C_GPING_083 (0x40d53)
3301 #define P_EMMC_C_GPING_083 (volatile uint32_t *)((0x40d53 << 2) + 0xffd00000)
3302 #define EMMC_C_GPING_084 (0x40d54)
3303 #define P_EMMC_C_GPING_084 (volatile uint32_t *)((0x40d54 << 2) + 0xffd00000)
3304 #define EMMC_C_GPING_085 (0x40d55)
3305 #define P_EMMC_C_GPING_085 (volatile uint32_t *)((0x40d55 << 2) + 0xffd00000)
3306 #define EMMC_C_GPING_086 (0x40d56)
3307 #define P_EMMC_C_GPING_086 (volatile uint32_t *)((0x40d56 << 2) + 0xffd00000)
3308 #define EMMC_C_GPING_087 (0x40d57)
3309 #define P_EMMC_C_GPING_087 (volatile uint32_t *)((0x40d57 << 2) + 0xffd00000)
3310 #define EMMC_C_GPING_088 (0x40d58)
3311 #define P_EMMC_C_GPING_088 (volatile uint32_t *)((0x40d58 << 2) + 0xffd00000)
3312 #define EMMC_C_GPING_089 (0x40d59)
3313 #define P_EMMC_C_GPING_089 (volatile uint32_t *)((0x40d59 << 2) + 0xffd00000)
3314 #define EMMC_C_GPING_090 (0x40d5a)
3315 #define P_EMMC_C_GPING_090 (volatile uint32_t *)((0x40d5a << 2) + 0xffd00000)
3316 #define EMMC_C_GPING_091 (0x40d5b)
3317 #define P_EMMC_C_GPING_091 (volatile uint32_t *)((0x40d5b << 2) + 0xffd00000)
3318 #define EMMC_C_GPING_092 (0x40d5c)
3319 #define P_EMMC_C_GPING_092 (volatile uint32_t *)((0x40d5c << 2) + 0xffd00000)
3320 #define EMMC_C_GPING_093 (0x40d5d)
3321 #define P_EMMC_C_GPING_093 (volatile uint32_t *)((0x40d5d << 2) + 0xffd00000)
3322 #define EMMC_C_GPING_094 (0x40d5e)
3323 #define P_EMMC_C_GPING_094 (volatile uint32_t *)((0x40d5e << 2) + 0xffd00000)
3324 #define EMMC_C_GPING_095 (0x40d5f)
3325 #define P_EMMC_C_GPING_095 (volatile uint32_t *)((0x40d5f << 2) + 0xffd00000)
3326 #define EMMC_C_GPING_096 (0x40d60)
3327 #define P_EMMC_C_GPING_096 (volatile uint32_t *)((0x40d60 << 2) + 0xffd00000)
3328 #define EMMC_C_GPING_097 (0x40d61)
3329 #define P_EMMC_C_GPING_097 (volatile uint32_t *)((0x40d61 << 2) + 0xffd00000)
3330 #define EMMC_C_GPING_098 (0x40d62)
3331 #define P_EMMC_C_GPING_098 (volatile uint32_t *)((0x40d62 << 2) + 0xffd00000)
3332 #define EMMC_C_GPING_099 (0x40d63)
3333 #define P_EMMC_C_GPING_099 (volatile uint32_t *)((0x40d63 << 2) + 0xffd00000)
3334 #define EMMC_C_GPING_100 (0x40d64)
3335 #define P_EMMC_C_GPING_100 (volatile uint32_t *)((0x40d64 << 2) + 0xffd00000)
3336 #define EMMC_C_GPING_101 (0x40d65)
3337 #define P_EMMC_C_GPING_101 (volatile uint32_t *)((0x40d65 << 2) + 0xffd00000)
3338 #define EMMC_C_GPING_102 (0x40d66)
3339 #define P_EMMC_C_GPING_102 (volatile uint32_t *)((0x40d66 << 2) + 0xffd00000)
3340 #define EMMC_C_GPING_103 (0x40d67)
3341 #define P_EMMC_C_GPING_103 (volatile uint32_t *)((0x40d67 << 2) + 0xffd00000)
3342 #define EMMC_C_GPING_104 (0x40d68)
3343 #define P_EMMC_C_GPING_104 (volatile uint32_t *)((0x40d68 << 2) + 0xffd00000)
3344 #define EMMC_C_GPING_105 (0x40d69)
3345 #define P_EMMC_C_GPING_105 (volatile uint32_t *)((0x40d69 << 2) + 0xffd00000)
3346 #define EMMC_C_GPING_106 (0x40d6a)
3347 #define P_EMMC_C_GPING_106 (volatile uint32_t *)((0x40d6a << 2) + 0xffd00000)
3348 #define EMMC_C_GPING_107 (0x40d6b)
3349 #define P_EMMC_C_GPING_107 (volatile uint32_t *)((0x40d6b << 2) + 0xffd00000)
3350 #define EMMC_C_GPING_108 (0x40d6c)
3351 #define P_EMMC_C_GPING_108 (volatile uint32_t *)((0x40d6c << 2) + 0xffd00000)
3352 #define EMMC_C_GPING_109 (0x40d6d)
3353 #define P_EMMC_C_GPING_109 (volatile uint32_t *)((0x40d6d << 2) + 0xffd00000)
3354 #define EMMC_C_GPING_110 (0x40d6e)
3355 #define P_EMMC_C_GPING_110 (volatile uint32_t *)((0x40d6e << 2) + 0xffd00000)
3356 #define EMMC_C_GPING_111 (0x40d6f)
3357 #define P_EMMC_C_GPING_111 (volatile uint32_t *)((0x40d6f << 2) + 0xffd00000)
3358 #define EMMC_C_GPING_112 (0x40d70)
3359 #define P_EMMC_C_GPING_112 (volatile uint32_t *)((0x40d70 << 2) + 0xffd00000)
3360 #define EMMC_C_GPING_113 (0x40d71)
3361 #define P_EMMC_C_GPING_113 (volatile uint32_t *)((0x40d71 << 2) + 0xffd00000)
3362 #define EMMC_C_GPING_114 (0x40d72)
3363 #define P_EMMC_C_GPING_114 (volatile uint32_t *)((0x40d72 << 2) + 0xffd00000)
3364 #define EMMC_C_GPING_115 (0x40d73)
3365 #define P_EMMC_C_GPING_115 (volatile uint32_t *)((0x40d73 << 2) + 0xffd00000)
3366 #define EMMC_C_GPING_116 (0x40d74)
3367 #define P_EMMC_C_GPING_116 (volatile uint32_t *)((0x40d74 << 2) + 0xffd00000)
3368 #define EMMC_C_GPING_117 (0x40d75)
3369 #define P_EMMC_C_GPING_117 (volatile uint32_t *)((0x40d75 << 2) + 0xffd00000)
3370 #define EMMC_C_GPING_118 (0x40d76)
3371 #define P_EMMC_C_GPING_118 (volatile uint32_t *)((0x40d76 << 2) + 0xffd00000)
3372 #define EMMC_C_GPING_119 (0x40d77)
3373 #define P_EMMC_C_GPING_119 (volatile uint32_t *)((0x40d77 << 2) + 0xffd00000)
3374 #define EMMC_C_GPING_120 (0x40d78)
3375 #define P_EMMC_C_GPING_120 (volatile uint32_t *)((0x40d78 << 2) + 0xffd00000)
3376 #define EMMC_C_GPING_121 (0x40d79)
3377 #define P_EMMC_C_GPING_121 (volatile uint32_t *)((0x40d79 << 2) + 0xffd00000)
3378 #define EMMC_C_GPING_122 (0x40d7a)
3379 #define P_EMMC_C_GPING_122 (volatile uint32_t *)((0x40d7a << 2) + 0xffd00000)
3380 #define EMMC_C_GPING_123 (0x40d7b)
3381 #define P_EMMC_C_GPING_123 (volatile uint32_t *)((0x40d7b << 2) + 0xffd00000)
3382 #define EMMC_C_GPING_124 (0x40d7c)
3383 #define P_EMMC_C_GPING_124 (volatile uint32_t *)((0x40d7c << 2) + 0xffd00000)
3384 #define EMMC_C_GPING_125 (0x40d7d)
3385 #define P_EMMC_C_GPING_125 (volatile uint32_t *)((0x40d7d << 2) + 0xffd00000)
3386 #define EMMC_C_GPING_126 (0x40d7e)
3387 #define P_EMMC_C_GPING_126 (volatile uint32_t *)((0x40d7e << 2) + 0xffd00000)
3388 #define EMMC_C_GPING_127 (0x40d7f)
3389 #define P_EMMC_C_GPING_127 (volatile uint32_t *)((0x40d7f << 2) + 0xffd00000)
3390 #define EMMC_C_GPONG_000 (0x40d80)
3391 #define P_EMMC_C_GPONG_000 (volatile uint32_t *)((0x40d80 << 2) + 0xffd00000)
3392 #define EMMC_C_GPONG_001 (0x40d81)
3393 #define P_EMMC_C_GPONG_001 (volatile uint32_t *)((0x40d81 << 2) + 0xffd00000)
3394 #define EMMC_C_GPONG_002 (0x40d82)
3395 #define P_EMMC_C_GPONG_002 (volatile uint32_t *)((0x40d82 << 2) + 0xffd00000)
3396 #define EMMC_C_GPONG_003 (0x40d83)
3397 #define P_EMMC_C_GPONG_003 (volatile uint32_t *)((0x40d83 << 2) + 0xffd00000)
3398 #define EMMC_C_GPONG_004 (0x40d84)
3399 #define P_EMMC_C_GPONG_004 (volatile uint32_t *)((0x40d84 << 2) + 0xffd00000)
3400 #define EMMC_C_GPONG_005 (0x40d85)
3401 #define P_EMMC_C_GPONG_005 (volatile uint32_t *)((0x40d85 << 2) + 0xffd00000)
3402 #define EMMC_C_GPONG_006 (0x40d86)
3403 #define P_EMMC_C_GPONG_006 (volatile uint32_t *)((0x40d86 << 2) + 0xffd00000)
3404 #define EMMC_C_GPONG_007 (0x40d87)
3405 #define P_EMMC_C_GPONG_007 (volatile uint32_t *)((0x40d87 << 2) + 0xffd00000)
3406 #define EMMC_C_GPONG_008 (0x40d88)
3407 #define P_EMMC_C_GPONG_008 (volatile uint32_t *)((0x40d88 << 2) + 0xffd00000)
3408 #define EMMC_C_GPONG_009 (0x40d89)
3409 #define P_EMMC_C_GPONG_009 (volatile uint32_t *)((0x40d89 << 2) + 0xffd00000)
3410 #define EMMC_C_GPONG_010 (0x40d8a)
3411 #define P_EMMC_C_GPONG_010 (volatile uint32_t *)((0x40d8a << 2) + 0xffd00000)
3412 #define EMMC_C_GPONG_011 (0x40d8b)
3413 #define P_EMMC_C_GPONG_011 (volatile uint32_t *)((0x40d8b << 2) + 0xffd00000)
3414 #define EMMC_C_GPONG_012 (0x40d8c)
3415 #define P_EMMC_C_GPONG_012 (volatile uint32_t *)((0x40d8c << 2) + 0xffd00000)
3416 #define EMMC_C_GPONG_013 (0x40d8d)
3417 #define P_EMMC_C_GPONG_013 (volatile uint32_t *)((0x40d8d << 2) + 0xffd00000)
3418 #define EMMC_C_GPONG_014 (0x40d8e)
3419 #define P_EMMC_C_GPONG_014 (volatile uint32_t *)((0x40d8e << 2) + 0xffd00000)
3420 #define EMMC_C_GPONG_015 (0x40d8f)
3421 #define P_EMMC_C_GPONG_015 (volatile uint32_t *)((0x40d8f << 2) + 0xffd00000)
3422 #define EMMC_C_GPONG_016 (0x40d90)
3423 #define P_EMMC_C_GPONG_016 (volatile uint32_t *)((0x40d90 << 2) + 0xffd00000)
3424 #define EMMC_C_GPONG_017 (0x40d91)
3425 #define P_EMMC_C_GPONG_017 (volatile uint32_t *)((0x40d91 << 2) + 0xffd00000)
3426 #define EMMC_C_GPONG_018 (0x40d92)
3427 #define P_EMMC_C_GPONG_018 (volatile uint32_t *)((0x40d92 << 2) + 0xffd00000)
3428 #define EMMC_C_GPONG_019 (0x40d93)
3429 #define P_EMMC_C_GPONG_019 (volatile uint32_t *)((0x40d93 << 2) + 0xffd00000)
3430 #define EMMC_C_GPONG_020 (0x40d94)
3431 #define P_EMMC_C_GPONG_020 (volatile uint32_t *)((0x40d94 << 2) + 0xffd00000)
3432 #define EMMC_C_GPONG_021 (0x40d95)
3433 #define P_EMMC_C_GPONG_021 (volatile uint32_t *)((0x40d95 << 2) + 0xffd00000)
3434 #define EMMC_C_GPONG_022 (0x40d96)
3435 #define P_EMMC_C_GPONG_022 (volatile uint32_t *)((0x40d96 << 2) + 0xffd00000)
3436 #define EMMC_C_GPONG_023 (0x40d97)
3437 #define P_EMMC_C_GPONG_023 (volatile uint32_t *)((0x40d97 << 2) + 0xffd00000)
3438 #define EMMC_C_GPONG_024 (0x40d98)
3439 #define P_EMMC_C_GPONG_024 (volatile uint32_t *)((0x40d98 << 2) + 0xffd00000)
3440 #define EMMC_C_GPONG_025 (0x40d99)
3441 #define P_EMMC_C_GPONG_025 (volatile uint32_t *)((0x40d99 << 2) + 0xffd00000)
3442 #define EMMC_C_GPONG_026 (0x40d9a)
3443 #define P_EMMC_C_GPONG_026 (volatile uint32_t *)((0x40d9a << 2) + 0xffd00000)
3444 #define EMMC_C_GPONG_027 (0x40d9b)
3445 #define P_EMMC_C_GPONG_027 (volatile uint32_t *)((0x40d9b << 2) + 0xffd00000)
3446 #define EMMC_C_GPONG_028 (0x40d9c)
3447 #define P_EMMC_C_GPONG_028 (volatile uint32_t *)((0x40d9c << 2) + 0xffd00000)
3448 #define EMMC_C_GPONG_029 (0x40d9d)
3449 #define P_EMMC_C_GPONG_029 (volatile uint32_t *)((0x40d9d << 2) + 0xffd00000)
3450 #define EMMC_C_GPONG_030 (0x40d9e)
3451 #define P_EMMC_C_GPONG_030 (volatile uint32_t *)((0x40d9e << 2) + 0xffd00000)
3452 #define EMMC_C_GPONG_031 (0x40d9f)
3453 #define P_EMMC_C_GPONG_031 (volatile uint32_t *)((0x40d9f << 2) + 0xffd00000)
3454 #define EMMC_C_GPONG_032 (0x40da0)
3455 #define P_EMMC_C_GPONG_032 (volatile uint32_t *)((0x40da0 << 2) + 0xffd00000)
3456 #define EMMC_C_GPONG_033 (0x40da1)
3457 #define P_EMMC_C_GPONG_033 (volatile uint32_t *)((0x40da1 << 2) + 0xffd00000)
3458 #define EMMC_C_GPONG_034 (0x40da2)
3459 #define P_EMMC_C_GPONG_034 (volatile uint32_t *)((0x40da2 << 2) + 0xffd00000)
3460 #define EMMC_C_GPONG_035 (0x40da3)
3461 #define P_EMMC_C_GPONG_035 (volatile uint32_t *)((0x40da3 << 2) + 0xffd00000)
3462 #define EMMC_C_GPONG_036 (0x40da4)
3463 #define P_EMMC_C_GPONG_036 (volatile uint32_t *)((0x40da4 << 2) + 0xffd00000)
3464 #define EMMC_C_GPONG_037 (0x40da5)
3465 #define P_EMMC_C_GPONG_037 (volatile uint32_t *)((0x40da5 << 2) + 0xffd00000)
3466 #define EMMC_C_GPONG_038 (0x40da6)
3467 #define P_EMMC_C_GPONG_038 (volatile uint32_t *)((0x40da6 << 2) + 0xffd00000)
3468 #define EMMC_C_GPONG_039 (0x40da7)
3469 #define P_EMMC_C_GPONG_039 (volatile uint32_t *)((0x40da7 << 2) + 0xffd00000)
3470 #define EMMC_C_GPONG_040 (0x40da8)
3471 #define P_EMMC_C_GPONG_040 (volatile uint32_t *)((0x40da8 << 2) + 0xffd00000)
3472 #define EMMC_C_GPONG_041 (0x40da9)
3473 #define P_EMMC_C_GPONG_041 (volatile uint32_t *)((0x40da9 << 2) + 0xffd00000)
3474 #define EMMC_C_GPONG_042 (0x40daa)
3475 #define P_EMMC_C_GPONG_042 (volatile uint32_t *)((0x40daa << 2) + 0xffd00000)
3476 #define EMMC_C_GPONG_043 (0x40dab)
3477 #define P_EMMC_C_GPONG_043 (volatile uint32_t *)((0x40dab << 2) + 0xffd00000)
3478 #define EMMC_C_GPONG_044 (0x40dac)
3479 #define P_EMMC_C_GPONG_044 (volatile uint32_t *)((0x40dac << 2) + 0xffd00000)
3480 #define EMMC_C_GPONG_045 (0x40dad)
3481 #define P_EMMC_C_GPONG_045 (volatile uint32_t *)((0x40dad << 2) + 0xffd00000)
3482 #define EMMC_C_GPONG_046 (0x40dae)
3483 #define P_EMMC_C_GPONG_046 (volatile uint32_t *)((0x40dae << 2) + 0xffd00000)
3484 #define EMMC_C_GPONG_047 (0x40daf)
3485 #define P_EMMC_C_GPONG_047 (volatile uint32_t *)((0x40daf << 2) + 0xffd00000)
3486 #define EMMC_C_GPONG_048 (0x40db0)
3487 #define P_EMMC_C_GPONG_048 (volatile uint32_t *)((0x40db0 << 2) + 0xffd00000)
3488 #define EMMC_C_GPONG_049 (0x40db1)
3489 #define P_EMMC_C_GPONG_049 (volatile uint32_t *)((0x40db1 << 2) + 0xffd00000)
3490 #define EMMC_C_GPONG_050 (0x40db2)
3491 #define P_EMMC_C_GPONG_050 (volatile uint32_t *)((0x40db2 << 2) + 0xffd00000)
3492 #define EMMC_C_GPONG_051 (0x40db3)
3493 #define P_EMMC_C_GPONG_051 (volatile uint32_t *)((0x40db3 << 2) + 0xffd00000)
3494 #define EMMC_C_GPONG_052 (0x40db4)
3495 #define P_EMMC_C_GPONG_052 (volatile uint32_t *)((0x40db4 << 2) + 0xffd00000)
3496 #define EMMC_C_GPONG_053 (0x40db5)
3497 #define P_EMMC_C_GPONG_053 (volatile uint32_t *)((0x40db5 << 2) + 0xffd00000)
3498 #define EMMC_C_GPONG_054 (0x40db6)
3499 #define P_EMMC_C_GPONG_054 (volatile uint32_t *)((0x40db6 << 2) + 0xffd00000)
3500 #define EMMC_C_GPONG_055 (0x40db7)
3501 #define P_EMMC_C_GPONG_055 (volatile uint32_t *)((0x40db7 << 2) + 0xffd00000)
3502 #define EMMC_C_GPONG_056 (0x40db8)
3503 #define P_EMMC_C_GPONG_056 (volatile uint32_t *)((0x40db8 << 2) + 0xffd00000)
3504 #define EMMC_C_GPONG_057 (0x40db9)
3505 #define P_EMMC_C_GPONG_057 (volatile uint32_t *)((0x40db9 << 2) + 0xffd00000)
3506 #define EMMC_C_GPONG_058 (0x40dba)
3507 #define P_EMMC_C_GPONG_058 (volatile uint32_t *)((0x40dba << 2) + 0xffd00000)
3508 #define EMMC_C_GPONG_059 (0x40dbb)
3509 #define P_EMMC_C_GPONG_059 (volatile uint32_t *)((0x40dbb << 2) + 0xffd00000)
3510 #define EMMC_C_GPONG_060 (0x40dbc)
3511 #define P_EMMC_C_GPONG_060 (volatile uint32_t *)((0x40dbc << 2) + 0xffd00000)
3512 #define EMMC_C_GPONG_061 (0x40dbd)
3513 #define P_EMMC_C_GPONG_061 (volatile uint32_t *)((0x40dbd << 2) + 0xffd00000)
3514 #define EMMC_C_GPONG_062 (0x40dbe)
3515 #define P_EMMC_C_GPONG_062 (volatile uint32_t *)((0x40dbe << 2) + 0xffd00000)
3516 #define EMMC_C_GPONG_063 (0x40dbf)
3517 #define P_EMMC_C_GPONG_063 (volatile uint32_t *)((0x40dbf << 2) + 0xffd00000)
3518 #define EMMC_C_GPONG_064 (0x40dc0)
3519 #define P_EMMC_C_GPONG_064 (volatile uint32_t *)((0x40dc0 << 2) + 0xffd00000)
3520 #define EMMC_C_GPONG_065 (0x40dc1)
3521 #define P_EMMC_C_GPONG_065 (volatile uint32_t *)((0x40dc1 << 2) + 0xffd00000)
3522 #define EMMC_C_GPONG_066 (0x40dc2)
3523 #define P_EMMC_C_GPONG_066 (volatile uint32_t *)((0x40dc2 << 2) + 0xffd00000)
3524 #define EMMC_C_GPONG_067 (0x40dc3)
3525 #define P_EMMC_C_GPONG_067 (volatile uint32_t *)((0x40dc3 << 2) + 0xffd00000)
3526 #define EMMC_C_GPONG_068 (0x40dc4)
3527 #define P_EMMC_C_GPONG_068 (volatile uint32_t *)((0x40dc4 << 2) + 0xffd00000)
3528 #define EMMC_C_GPONG_069 (0x40dc5)
3529 #define P_EMMC_C_GPONG_069 (volatile uint32_t *)((0x40dc5 << 2) + 0xffd00000)
3530 #define EMMC_C_GPONG_070 (0x40dc6)
3531 #define P_EMMC_C_GPONG_070 (volatile uint32_t *)((0x40dc6 << 2) + 0xffd00000)
3532 #define EMMC_C_GPONG_071 (0x40dc7)
3533 #define P_EMMC_C_GPONG_071 (volatile uint32_t *)((0x40dc7 << 2) + 0xffd00000)
3534 #define EMMC_C_GPONG_072 (0x40dc8)
3535 #define P_EMMC_C_GPONG_072 (volatile uint32_t *)((0x40dc8 << 2) + 0xffd00000)
3536 #define EMMC_C_GPONG_073 (0x40dc9)
3537 #define P_EMMC_C_GPONG_073 (volatile uint32_t *)((0x40dc9 << 2) + 0xffd00000)
3538 #define EMMC_C_GPONG_074 (0x40dca)
3539 #define P_EMMC_C_GPONG_074 (volatile uint32_t *)((0x40dca << 2) + 0xffd00000)
3540 #define EMMC_C_GPONG_075 (0x40dcb)
3541 #define P_EMMC_C_GPONG_075 (volatile uint32_t *)((0x40dcb << 2) + 0xffd00000)
3542 #define EMMC_C_GPONG_076 (0x40dcc)
3543 #define P_EMMC_C_GPONG_076 (volatile uint32_t *)((0x40dcc << 2) + 0xffd00000)
3544 #define EMMC_C_GPONG_077 (0x40dcd)
3545 #define P_EMMC_C_GPONG_077 (volatile uint32_t *)((0x40dcd << 2) + 0xffd00000)
3546 #define EMMC_C_GPONG_078 (0x40dce)
3547 #define P_EMMC_C_GPONG_078 (volatile uint32_t *)((0x40dce << 2) + 0xffd00000)
3548 #define EMMC_C_GPONG_079 (0x40dcf)
3549 #define P_EMMC_C_GPONG_079 (volatile uint32_t *)((0x40dcf << 2) + 0xffd00000)
3550 #define EMMC_C_GPONG_080 (0x40dd0)
3551 #define P_EMMC_C_GPONG_080 (volatile uint32_t *)((0x40dd0 << 2) + 0xffd00000)
3552 #define EMMC_C_GPONG_081 (0x40dd1)
3553 #define P_EMMC_C_GPONG_081 (volatile uint32_t *)((0x40dd1 << 2) + 0xffd00000)
3554 #define EMMC_C_GPONG_082 (0x40dd2)
3555 #define P_EMMC_C_GPONG_082 (volatile uint32_t *)((0x40dd2 << 2) + 0xffd00000)
3556 #define EMMC_C_GPONG_083 (0x40dd3)
3557 #define P_EMMC_C_GPONG_083 (volatile uint32_t *)((0x40dd3 << 2) + 0xffd00000)
3558 #define EMMC_C_GPONG_084 (0x40dd4)
3559 #define P_EMMC_C_GPONG_084 (volatile uint32_t *)((0x40dd4 << 2) + 0xffd00000)
3560 #define EMMC_C_GPONG_085 (0x40dd5)
3561 #define P_EMMC_C_GPONG_085 (volatile uint32_t *)((0x40dd5 << 2) + 0xffd00000)
3562 #define EMMC_C_GPONG_086 (0x40dd6)
3563 #define P_EMMC_C_GPONG_086 (volatile uint32_t *)((0x40dd6 << 2) + 0xffd00000)
3564 #define EMMC_C_GPONG_087 (0x40dd7)
3565 #define P_EMMC_C_GPONG_087 (volatile uint32_t *)((0x40dd7 << 2) + 0xffd00000)
3566 #define EMMC_C_GPONG_088 (0x40dd8)
3567 #define P_EMMC_C_GPONG_088 (volatile uint32_t *)((0x40dd8 << 2) + 0xffd00000)
3568 #define EMMC_C_GPONG_089 (0x40dd9)
3569 #define P_EMMC_C_GPONG_089 (volatile uint32_t *)((0x40dd9 << 2) + 0xffd00000)
3570 #define EMMC_C_GPONG_090 (0x40dda)
3571 #define P_EMMC_C_GPONG_090 (volatile uint32_t *)((0x40dda << 2) + 0xffd00000)
3572 #define EMMC_C_GPONG_091 (0x40ddb)
3573 #define P_EMMC_C_GPONG_091 (volatile uint32_t *)((0x40ddb << 2) + 0xffd00000)
3574 #define EMMC_C_GPONG_092 (0x40ddc)
3575 #define P_EMMC_C_GPONG_092 (volatile uint32_t *)((0x40ddc << 2) + 0xffd00000)
3576 #define EMMC_C_GPONG_093 (0x40ddd)
3577 #define P_EMMC_C_GPONG_093 (volatile uint32_t *)((0x40ddd << 2) + 0xffd00000)
3578 #define EMMC_C_GPONG_094 (0x40dde)
3579 #define P_EMMC_C_GPONG_094 (volatile uint32_t *)((0x40dde << 2) + 0xffd00000)
3580 #define EMMC_C_GPONG_095 (0x40ddf)
3581 #define P_EMMC_C_GPONG_095 (volatile uint32_t *)((0x40ddf << 2) + 0xffd00000)
3582 #define EMMC_C_GPONG_096 (0x40de0)
3583 #define P_EMMC_C_GPONG_096 (volatile uint32_t *)((0x40de0 << 2) + 0xffd00000)
3584 #define EMMC_C_GPONG_097 (0x40de1)
3585 #define P_EMMC_C_GPONG_097 (volatile uint32_t *)((0x40de1 << 2) + 0xffd00000)
3586 #define EMMC_C_GPONG_098 (0x40de2)
3587 #define P_EMMC_C_GPONG_098 (volatile uint32_t *)((0x40de2 << 2) + 0xffd00000)
3588 #define EMMC_C_GPONG_099 (0x40de3)
3589 #define P_EMMC_C_GPONG_099 (volatile uint32_t *)((0x40de3 << 2) + 0xffd00000)
3590 #define EMMC_C_GPONG_100 (0x40de4)
3591 #define P_EMMC_C_GPONG_100 (volatile uint32_t *)((0x40de4 << 2) + 0xffd00000)
3592 #define EMMC_C_GPONG_101 (0x40de5)
3593 #define P_EMMC_C_GPONG_101 (volatile uint32_t *)((0x40de5 << 2) + 0xffd00000)
3594 #define EMMC_C_GPONG_102 (0x40de6)
3595 #define P_EMMC_C_GPONG_102 (volatile uint32_t *)((0x40de6 << 2) + 0xffd00000)
3596 #define EMMC_C_GPONG_103 (0x40de7)
3597 #define P_EMMC_C_GPONG_103 (volatile uint32_t *)((0x40de7 << 2) + 0xffd00000)
3598 #define EMMC_C_GPONG_104 (0x40de8)
3599 #define P_EMMC_C_GPONG_104 (volatile uint32_t *)((0x40de8 << 2) + 0xffd00000)
3600 #define EMMC_C_GPONG_105 (0x40de9)
3601 #define P_EMMC_C_GPONG_105 (volatile uint32_t *)((0x40de9 << 2) + 0xffd00000)
3602 #define EMMC_C_GPONG_106 (0x40dea)
3603 #define P_EMMC_C_GPONG_106 (volatile uint32_t *)((0x40dea << 2) + 0xffd00000)
3604 #define EMMC_C_GPONG_107 (0x40deb)
3605 #define P_EMMC_C_GPONG_107 (volatile uint32_t *)((0x40deb << 2) + 0xffd00000)
3606 #define EMMC_C_GPONG_108 (0x40dec)
3607 #define P_EMMC_C_GPONG_108 (volatile uint32_t *)((0x40dec << 2) + 0xffd00000)
3608 #define EMMC_C_GPONG_109 (0x40ded)
3609 #define P_EMMC_C_GPONG_109 (volatile uint32_t *)((0x40ded << 2) + 0xffd00000)
3610 #define EMMC_C_GPONG_110 (0x40dee)
3611 #define P_EMMC_C_GPONG_110 (volatile uint32_t *)((0x40dee << 2) + 0xffd00000)
3612 #define EMMC_C_GPONG_111 (0x40def)
3613 #define P_EMMC_C_GPONG_111 (volatile uint32_t *)((0x40def << 2) + 0xffd00000)
3614 #define EMMC_C_GPONG_112 (0x40df0)
3615 #define P_EMMC_C_GPONG_112 (volatile uint32_t *)((0x40df0 << 2) + 0xffd00000)
3616 #define EMMC_C_GPONG_113 (0x40df1)
3617 #define P_EMMC_C_GPONG_113 (volatile uint32_t *)((0x40df1 << 2) + 0xffd00000)
3618 #define EMMC_C_GPONG_114 (0x40df2)
3619 #define P_EMMC_C_GPONG_114 (volatile uint32_t *)((0x40df2 << 2) + 0xffd00000)
3620 #define EMMC_C_GPONG_115 (0x40df3)
3621 #define P_EMMC_C_GPONG_115 (volatile uint32_t *)((0x40df3 << 2) + 0xffd00000)
3622 #define EMMC_C_GPONG_116 (0x40df4)
3623 #define P_EMMC_C_GPONG_116 (volatile uint32_t *)((0x40df4 << 2) + 0xffd00000)
3624 #define EMMC_C_GPONG_117 (0x40df5)
3625 #define P_EMMC_C_GPONG_117 (volatile uint32_t *)((0x40df5 << 2) + 0xffd00000)
3626 #define EMMC_C_GPONG_118 (0x40df6)
3627 #define P_EMMC_C_GPONG_118 (volatile uint32_t *)((0x40df6 << 2) + 0xffd00000)
3628 #define EMMC_C_GPONG_119 (0x40df7)
3629 #define P_EMMC_C_GPONG_119 (volatile uint32_t *)((0x40df7 << 2) + 0xffd00000)
3630 #define EMMC_C_GPONG_120 (0x40df8)
3631 #define P_EMMC_C_GPONG_120 (volatile uint32_t *)((0x40df8 << 2) + 0xffd00000)
3632 #define EMMC_C_GPONG_121 (0x40df9)
3633 #define P_EMMC_C_GPONG_121 (volatile uint32_t *)((0x40df9 << 2) + 0xffd00000)
3634 #define EMMC_C_GPONG_122 (0x40dfa)
3635 #define P_EMMC_C_GPONG_122 (volatile uint32_t *)((0x40dfa << 2) + 0xffd00000)
3636 #define EMMC_C_GPONG_123 (0x40dfb)
3637 #define P_EMMC_C_GPONG_123 (volatile uint32_t *)((0x40dfb << 2) + 0xffd00000)
3638 #define EMMC_C_GPONG_124 (0x40dfc)
3639 #define P_EMMC_C_GPONG_124 (volatile uint32_t *)((0x40dfc << 2) + 0xffd00000)
3640 #define EMMC_C_GPONG_125 (0x40dfd)
3641 #define P_EMMC_C_GPONG_125 (volatile uint32_t *)((0x40dfd << 2) + 0xffd00000)
3642 #define EMMC_C_GPONG_126 (0x40dfe)
3643 #define P_EMMC_C_GPONG_126 (volatile uint32_t *)((0x40dfe << 2) + 0xffd00000)
3644 #define EMMC_C_GPONG_127 (0x40dff)
3645 #define P_EMMC_C_GPONG_127 (volatile uint32_t *)((0x40dff << 2) + 0xffd00000)
3646 //
3647 // Closing file: emmc_reg.h
3648 //
3649 //
3650 // Reading file: usb_reg.h
3651 //
3652 // $periphs/rtl/periphs_core register defines for the
3653 // APB bus
3654 // ------------------------------------------------------------------------------------
3655 // -----------------------------------------------
3656 // CBUS_BASE: USB_CBUS_BASE = 0x424
3657 // -----------------------------------------------
3658 #define USB21_REG0 (0x42408)
3659 #define P_USB21_REG0 (volatile uint32_t *)((0x42408 << 2) + 0xffd00000)
3660 #define USB21_REG1 (0x42409)
3661 #define P_USB21_REG1 (volatile uint32_t *)((0x42409 << 2) + 0xffd00000)
3662 #define USB21_REG2 (0x4240a)
3663 #define P_USB21_REG2 (volatile uint32_t *)((0x4240a << 2) + 0xffd00000)
3664 //
3665 // Closing file: usb_reg.h
3666 //
3667 //`include "bt656_reg.h"
3668 //`include "pdm_reg.h"
3669 //========================================================================
3670 // Global Control Registers (12'h000 - 12'h0ff)
3671 //
3672 //========================================================================
3673 // -----------------------------------------------
3674 // CBUS_BASE: RESET_CBUS_BASE = 0x04
3675 // -----------------------------------------------
3676 #define VERSION_CTRL (0x0400)
3677 #define P_VERSION_CTRL (volatile uint32_t *)((0x0400 << 2) + 0xffd00000)
3678 #define RESET0_REGISTER (0x0401)
3679 #define P_RESET0_REGISTER (volatile uint32_t *)((0x0401 << 2) + 0xffd00000)
3680 #define RESET1_REGISTER (0x0402)
3681 #define P_RESET1_REGISTER (volatile uint32_t *)((0x0402 << 2) + 0xffd00000)
3682 #define RESET2_REGISTER (0x0403)
3683 #define P_RESET2_REGISTER (volatile uint32_t *)((0x0403 << 2) + 0xffd00000)
3684 #define RESET3_REGISTER (0x0404)
3685 #define P_RESET3_REGISTER (volatile uint32_t *)((0x0404 << 2) + 0xffd00000)
3686 #define RESET4_REGISTER (0x0405)
3687 #define P_RESET4_REGISTER (volatile uint32_t *)((0x0405 << 2) + 0xffd00000)
3688 #define RESET5_REGISTER (0x0406)
3689 #define P_RESET5_REGISTER (volatile uint32_t *)((0x0406 << 2) + 0xffd00000)
3690 #define RESET6_REGISTER (0x0407)
3691 #define P_RESET6_REGISTER (volatile uint32_t *)((0x0407 << 2) + 0xffd00000)
3692 #define RESET7_REGISTER (0x0408)
3693 #define P_RESET7_REGISTER (volatile uint32_t *)((0x0408 << 2) + 0xffd00000)
3694 #define RESET0_MASK (0x0410)
3695 #define P_RESET0_MASK (volatile uint32_t *)((0x0410 << 2) + 0xffd00000)
3696 #define RESET1_MASK (0x0411)
3697 #define P_RESET1_MASK (volatile uint32_t *)((0x0411 << 2) + 0xffd00000)
3698 #define RESET2_MASK (0x0412)
3699 #define P_RESET2_MASK (volatile uint32_t *)((0x0412 << 2) + 0xffd00000)
3700 #define RESET3_MASK (0x0413)
3701 #define P_RESET3_MASK (volatile uint32_t *)((0x0413 << 2) + 0xffd00000)
3702 #define RESET4_MASK (0x0414)
3703 #define P_RESET4_MASK (volatile uint32_t *)((0x0414 << 2) + 0xffd00000)
3704 #define RESET5_MASK (0x0415)
3705 #define P_RESET5_MASK (volatile uint32_t *)((0x0415 << 2) + 0xffd00000)
3706 #define RESET6_MASK (0x0416)
3707 #define P_RESET6_MASK (volatile uint32_t *)((0x0416 << 2) + 0xffd00000)
3708 #define CRT_MASK (0x0417)
3709 #define P_CRT_MASK (volatile uint32_t *)((0x0417 << 2) + 0xffd00000)
3710 #define RESET7_MASK (0x0418)
3711 #define P_RESET7_MASK (volatile uint32_t *)((0x0418 << 2) + 0xffd00000)
3712 #define RESET0_LEVEL (0x0420)
3713 #define P_RESET0_LEVEL (volatile uint32_t *)((0x0420 << 2) + 0xffd00000)
3714 #define RESET1_LEVEL (0x0421)
3715 #define P_RESET1_LEVEL (volatile uint32_t *)((0x0421 << 2) + 0xffd00000)
3716 #define RESET2_LEVEL (0x0422)
3717 #define P_RESET2_LEVEL (volatile uint32_t *)((0x0422 << 2) + 0xffd00000)
3718 #define RESET3_LEVEL (0x0423)
3719 #define P_RESET3_LEVEL (volatile uint32_t *)((0x0423 << 2) + 0xffd00000)
3720 #define RESET4_LEVEL (0x0424)
3721 #define P_RESET4_LEVEL (volatile uint32_t *)((0x0424 << 2) + 0xffd00000)
3722 #define RESET5_LEVEL (0x0425)
3723 #define P_RESET5_LEVEL (volatile uint32_t *)((0x0425 << 2) + 0xffd00000)
3724 #define RESET6_LEVEL (0x0426)
3725 #define P_RESET6_LEVEL (volatile uint32_t *)((0x0426 << 2) + 0xffd00000)
3726 #define RESET7_LEVEL (0x0427)
3727 #define P_RESET7_LEVEL (volatile uint32_t *)((0x0427 << 2) + 0xffd00000)
3728 //======================================
3729 // Reset Register Bits
3730 //
3731 //======================================
3732 #define HIU_RESET 0x0001
3733 #define VLD_RESET 0x0002
3734 #define IQIDCT_RESET 0x0004
3735 #define MC_RESET 0x0008
3736 #define DCU_RESET 0x0010
3737 #define VIU_RESET 0x0020
3738 #define AIU_RESET 0x0040
3739 #define CPU_RESET 0x0080
3740 #define AC3_RESET 0x0100
3741 #define MPEG_RESET 0x0200
3742 //=======================================================================
3743 // XIF module
3744 // `include "xregs.h"
3745 #define X_INT_ADR 0x400
3746 #define GPIO_ADR 0x401
3747 #define GPIO_ADR_H8 0x402
3748 #define WFIFO_DEPTH 8
3749 #define WFIFO_PointerWidth 3
3750 #define WFIFO_WORDSIZE 32
3751 //========================================================================
3752 // registers for mipi_dsi (12'h8a0 - 12'h8ff)
3753 //========================================================================
3754 //
3755 // Reading file: dsi_regs.h
3756 //
3757 // synopsys translate_off
3758 // synopsys translate_on
3759 //===========================================================================
3760 // MIPI DSI HOST CONTROLLER Registers 0x1800 - 0x18ff
3761 //===========================================================================
3762 // -----------------------------------------------
3763 // CBUS_BASE: DSI_CBUS_BASE = 0x18
3764 // -----------------------------------------------
3765 #define MIPI_DSI_REGISTER
3766 //------------------------------------------------------------------------------
3767 // DWC IP registers: Synopsys IP, please refer to MIPI DSI HOST Databook
3768 //------------------------------------------------------------------------------
3769 #define MIPI_DSI_DWC_VERSION_OS (0x1800)
3770 #define P_MIPI_DSI_DWC_VERSION_OS (volatile uint32_t *)((0x1800 << 2) + 0xffd00000)
3771 #define MIPI_DSI_DWC_PWR_UP_OS (0x1801)
3772 #define P_MIPI_DSI_DWC_PWR_UP_OS (volatile uint32_t *)((0x1801 << 2) + 0xffd00000)
3773 #define MIPI_DSI_DWC_CLKMGR_CFG_OS (0x1802)
3774 #define P_MIPI_DSI_DWC_CLKMGR_CFG_OS (volatile uint32_t *)((0x1802 << 2) + 0xffd00000)
3775 #define MIPI_DSI_DWC_DPI_VCID_OS (0x1803)
3776 #define P_MIPI_DSI_DWC_DPI_VCID_OS (volatile uint32_t *)((0x1803 << 2) + 0xffd00000)
3777 #define MIPI_DSI_DWC_DPI_COLOR_CODING_OS (0x1804)
3778 #define P_MIPI_DSI_DWC_DPI_COLOR_CODING_OS (volatile uint32_t *)((0x1804 << 2) + 0xffd00000)
3779 #define MIPI_DSI_DWC_DPI_CFG_POL_OS (0x1805)
3780 #define P_MIPI_DSI_DWC_DPI_CFG_POL_OS (volatile uint32_t *)((0x1805 << 2) + 0xffd00000)
3781 #define MIPI_DSI_DWC_DPI_LP_CMD_TIM_OS (0x1806)
3782 #define P_MIPI_DSI_DWC_DPI_LP_CMD_TIM_OS (volatile uint32_t *)((0x1806 << 2) + 0xffd00000)
3783 #define MIPI_DSI_DWC_PCKHDL_CFG_OS (0x180b)
3784 #define P_MIPI_DSI_DWC_PCKHDL_CFG_OS (volatile uint32_t *)((0x180b << 2) + 0xffd00000)
3785 #define MIPI_DSI_DWC_GEN_VCID_OS (0x180c)
3786 #define P_MIPI_DSI_DWC_GEN_VCID_OS (volatile uint32_t *)((0x180c << 2) + 0xffd00000)
3787 #define MIPI_DSI_DWC_MODE_CFG_OS (0x180d)
3788 #define P_MIPI_DSI_DWC_MODE_CFG_OS (volatile uint32_t *)((0x180d << 2) + 0xffd00000)
3789 #define MIPI_DSI_DWC_VID_MODE_CFG_OS (0x180e)
3790 #define P_MIPI_DSI_DWC_VID_MODE_CFG_OS (volatile uint32_t *)((0x180e << 2) + 0xffd00000)
3791 #define MIPI_DSI_DWC_VID_PKT_SIZE_OS (0x180f)
3792 #define P_MIPI_DSI_DWC_VID_PKT_SIZE_OS (volatile uint32_t *)((0x180f << 2) + 0xffd00000)
3793 #define MIPI_DSI_DWC_VID_NUM_CHUNKS_OS (0x1810)
3794 #define P_MIPI_DSI_DWC_VID_NUM_CHUNKS_OS (volatile uint32_t *)((0x1810 << 2) + 0xffd00000)
3795 #define MIPI_DSI_DWC_VID_NULL_SIZE_OS (0x1811)
3796 #define P_MIPI_DSI_DWC_VID_NULL_SIZE_OS (volatile uint32_t *)((0x1811 << 2) + 0xffd00000)
3797 #define MIPI_DSI_DWC_VID_HSA_TIME_OS (0x1812)
3798 #define P_MIPI_DSI_DWC_VID_HSA_TIME_OS (volatile uint32_t *)((0x1812 << 2) + 0xffd00000)
3799 #define MIPI_DSI_DWC_VID_HBP_TIME_OS (0x1813)
3800 #define P_MIPI_DSI_DWC_VID_HBP_TIME_OS (volatile uint32_t *)((0x1813 << 2) + 0xffd00000)
3801 #define MIPI_DSI_DWC_VID_HLINE_TIME_OS (0x1814)
3802 #define P_MIPI_DSI_DWC_VID_HLINE_TIME_OS (volatile uint32_t *)((0x1814 << 2) + 0xffd00000)
3803 #define MIPI_DSI_DWC_VID_VSA_LINES_OS (0x1815)
3804 #define P_MIPI_DSI_DWC_VID_VSA_LINES_OS (volatile uint32_t *)((0x1815 << 2) + 0xffd00000)
3805 #define MIPI_DSI_DWC_VID_VBP_LINES_OS (0x1816)
3806 #define P_MIPI_DSI_DWC_VID_VBP_LINES_OS (volatile uint32_t *)((0x1816 << 2) + 0xffd00000)
3807 #define MIPI_DSI_DWC_VID_VFP_LINES_OS (0x1817)
3808 #define P_MIPI_DSI_DWC_VID_VFP_LINES_OS (volatile uint32_t *)((0x1817 << 2) + 0xffd00000)
3809 #define MIPI_DSI_DWC_VID_VACTIVE_LINES_OS (0x1818)
3810 #define P_MIPI_DSI_DWC_VID_VACTIVE_LINES_OS (volatile uint32_t *)((0x1818 << 2) + 0xffd00000)
3811 #define MIPI_DSI_DWC_EDPI_CMD_SIZE_OS (0x1819)
3812 #define P_MIPI_DSI_DWC_EDPI_CMD_SIZE_OS (volatile uint32_t *)((0x1819 << 2) + 0xffd00000)
3813 #define MIPI_DSI_DWC_CMD_MODE_CFG_OS (0x181a)
3814 #define P_MIPI_DSI_DWC_CMD_MODE_CFG_OS (volatile uint32_t *)((0x181a << 2) + 0xffd00000)
3815 #define MIPI_DSI_DWC_GEN_HDR_OS (0x181b)
3816 #define P_MIPI_DSI_DWC_GEN_HDR_OS (volatile uint32_t *)((0x181b << 2) + 0xffd00000)
3817 #define MIPI_DSI_DWC_GEN_PLD_DATA_OS (0x181c)
3818 #define P_MIPI_DSI_DWC_GEN_PLD_DATA_OS (volatile uint32_t *)((0x181c << 2) + 0xffd00000)
3819 #define MIPI_DSI_DWC_CMD_PKT_STATUS_OS (0x181d)
3820 #define P_MIPI_DSI_DWC_CMD_PKT_STATUS_OS (volatile uint32_t *)((0x181d << 2) + 0xffd00000)
3821 #define MIPI_DSI_DWC_TO_CNT_CFG_OS (0x181e)
3822 #define P_MIPI_DSI_DWC_TO_CNT_CFG_OS (volatile uint32_t *)((0x181e << 2) + 0xffd00000)
3823 #define MIPI_DSI_DWC_HS_RD_TO_CNT_OS (0x181f)
3824 #define P_MIPI_DSI_DWC_HS_RD_TO_CNT_OS (volatile uint32_t *)((0x181f << 2) + 0xffd00000)
3825 #define MIPI_DSI_DWC_LP_RD_TO_CNT_OS (0x1820)
3826 #define P_MIPI_DSI_DWC_LP_RD_TO_CNT_OS (volatile uint32_t *)((0x1820 << 2) + 0xffd00000)
3827 #define MIPI_DSI_DWC_HS_WR_TO_CNT_OS (0x1821)
3828 #define P_MIPI_DSI_DWC_HS_WR_TO_CNT_OS (volatile uint32_t *)((0x1821 << 2) + 0xffd00000)
3829 #define MIPI_DSI_DWC_LP_WR_TO_CNT_OS (0x1822)
3830 #define P_MIPI_DSI_DWC_LP_WR_TO_CNT_OS (volatile uint32_t *)((0x1822 << 2) + 0xffd00000)
3831 #define MIPI_DSI_DWC_BTA_TO_CNT_OS (0x1823)
3832 #define P_MIPI_DSI_DWC_BTA_TO_CNT_OS (volatile uint32_t *)((0x1823 << 2) + 0xffd00000)
3833 #define MIPI_DSI_DWC_SDF_3D_OS (0x1824)
3834 #define P_MIPI_DSI_DWC_SDF_3D_OS (volatile uint32_t *)((0x1824 << 2) + 0xffd00000)
3835 #define MIPI_DSI_DWC_LPCLK_CTRL_OS (0x1825)
3836 #define P_MIPI_DSI_DWC_LPCLK_CTRL_OS (volatile uint32_t *)((0x1825 << 2) + 0xffd00000)
3837 #define MIPI_DSI_DWC_PHY_TMR_LPCLK_CFG_OS (0x1826)
3838 #define P_MIPI_DSI_DWC_PHY_TMR_LPCLK_CFG_OS (volatile uint32_t *)((0x1826 << 2) + 0xffd00000)
3839 #define MIPI_DSI_DWC_PHY_TMR_CFG_OS (0x1827)
3840 #define P_MIPI_DSI_DWC_PHY_TMR_CFG_OS (volatile uint32_t *)((0x1827 << 2) + 0xffd00000)
3841 #define MIPI_DSI_DWC_PHY_RSTZ_OS (0x1828)
3842 #define P_MIPI_DSI_DWC_PHY_RSTZ_OS (volatile uint32_t *)((0x1828 << 2) + 0xffd00000)
3843 #define MIPI_DSI_DWC_PHY_IF_CFG_OS (0x1829)
3844 #define P_MIPI_DSI_DWC_PHY_IF_CFG_OS (volatile uint32_t *)((0x1829 << 2) + 0xffd00000)
3845 #define MIPI_DSI_DWC_PHY_ULPS_CTRL_OS (0x182a)
3846 #define P_MIPI_DSI_DWC_PHY_ULPS_CTRL_OS (volatile uint32_t *)((0x182a << 2) + 0xffd00000)
3847 #define MIPI_DSI_DWC_PHY_TX_TRIGGERS_OS (0x182b)
3848 #define P_MIPI_DSI_DWC_PHY_TX_TRIGGERS_OS (volatile uint32_t *)((0x182b << 2) + 0xffd00000)
3849 #define MIPI_DSI_DWC_PHY_STATUS_OS (0x182c)
3850 #define P_MIPI_DSI_DWC_PHY_STATUS_OS (volatile uint32_t *)((0x182c << 2) + 0xffd00000)
3851 #define MIPI_DSI_DWC_PHY_TST_CTRL0_OS (0x182d)
3852 #define P_MIPI_DSI_DWC_PHY_TST_CTRL0_OS (volatile uint32_t *)((0x182d << 2) + 0xffd00000)
3853 #define MIPI_DSI_DWC_PHY_TST_CTRL1_OS (0x182e)
3854 #define P_MIPI_DSI_DWC_PHY_TST_CTRL1_OS (volatile uint32_t *)((0x182e << 2) + 0xffd00000)
3855 #define MIPI_DSI_DWC_INT_ST0_OS (0x182f)
3856 #define P_MIPI_DSI_DWC_INT_ST0_OS (volatile uint32_t *)((0x182f << 2) + 0xffd00000)
3857 #define MIPI_DSI_DWC_INT_ST1_OS (0x1830)
3858 #define P_MIPI_DSI_DWC_INT_ST1_OS (volatile uint32_t *)((0x1830 << 2) + 0xffd00000)
3859 #define MIPI_DSI_DWC_INT_MSK0_OS (0x1831)
3860 #define P_MIPI_DSI_DWC_INT_MSK0_OS (volatile uint32_t *)((0x1831 << 2) + 0xffd00000)
3861 #define MIPI_DSI_DWC_INT_MSK1_OS (0x1832)
3862 #define P_MIPI_DSI_DWC_INT_MSK1_OS (volatile uint32_t *)((0x1832 << 2) + 0xffd00000)
3863 //------------------------------------------------------------------------------
3864 // Top-level registers: AmLogic proprietary
3865 //------------------------------------------------------------------------------
3866 // 31: 4 Reserved. Default 0.
3867 // 3 RW ~tim_rst_n: 1=Assert SW reset on mipi_dsi_host_timing block. 0=Release reset. Default 1.
3868 // 2 RW ~dpi_rst_n: 1=Assert SW reset on mipi_dsi_host_dpi block. 0=Release reset. Default 1.
3869 // 1 RW ~intr_rst_n: 1=Assert SW reset on mipi_dsi_host_intr block. 0=Release reset. Default 1.
3870 // 0 RW ~dwc_rst_n: 1=Assert SW reset on IP core. 0=Release reset. Default 1.
3871 #define MIPI_DSI_TOP_SW_RESET (0x18f0)
3872 #define P_MIPI_DSI_TOP_SW_RESET (volatile uint32_t *)((0x18f0 << 2) + 0xffd00000)
3873 // 31: 3 Reserved. Default 0.
3874 // 2 RW clock_freerun: Apply to auto-clock gate only. Default 0.
3875 // 0=Default, use auto-clock gating to save power;
3876 // 1=use free-run clock, disable auto-clock gating, for debug mode.
3877 // 1 RW enable_pixclk: A manual clock gate option, due to DWC IP does not have auto-clock gating. 1=Enable pixclk. Default 0.
3878 // 0 RW enable_sysclk: A manual clock gate option, due to DWC IP does not have auto-clock gating. 1=Enable sysclk. Default 0.
3879 #define MIPI_DSI_TOP_CLK_CNTL (0x18f1)
3880 #define P_MIPI_DSI_TOP_CLK_CNTL (volatile uint32_t *)((0x18f1 << 2) + 0xffd00000)
3881 // 31:27 Reserved. Default 0.
3882 // 26 RW de_dpi_pol: 1= Invert DE polarity from mipi_dsi_host_dpi. Default 0.
3883 // 25 RW hsync_dpi_pol: 1= Invert HS polarity from mipi_dsi_host_dpi. Default 0.
3884 // 24 RW vsync_dpi_pol: 1= Invert VS polarity from mipi_dsi_host_dpi. Default 0.
3885 // 23:20 RW dpi_color_mode: Define DPI pixel format. Default 0.
3886 // 0=16-bit RGB565 config 1;
3887 // 1=16-bit RGB565 config 2;
3888 // 2=16-bit RGB565 config 3;
3889 // 3=18-bit RGB666 config 1;
3890 // 4=18-bit RGB666 config 2;
3891 // 5=24-bit RGB888;
3892 // 6=20-bit YCbCr 4:2:2;
3893 // 7=24-bit YCbCr 4:2:2;
3894 // 8=16-bit YCbCr 4:2:2;
3895 // 9=30-bit RGB;
3896 // 10=36-bit RGB;
3897 // 11=12-bit YCbCr 4:2:0.
3898 // 19 Reserved. Default 0.
3899 // 18:16 RW in_color_mode: Define VENC data width. Default 0.
3900 // 0=30-bit pixel;
3901 // 1=24-bit pixel;
3902 // 2=18-bit pixel, RGB666;
3903 // 3=16-bit pixel, RGB565.
3904 // 15:14 RW chroma_subsample: Define method of chroma subsampling. Default 0.
3905 // Applicable to YUV422 or YUV420 only.
3906 // 0=Use even pixel's chroma;
3907 // 1=Use odd pixel's chroma;
3908 // 2=Use averaged value between even and odd pair.
3909 // 13:12 RW comp2_sel: Select which component to be Cr or B: 0=comp0; 1=comp1; 2=comp2. Default 2.
3910 // 11:10 RW comp1_sel: Select which component to be Cb or G: 0=comp0; 1=comp1; 2=comp2. Default 1.
3911 // 9: 8 RW comp0_sel: Select which component to be Y or R: 0=comp0; 1=comp1; 2=comp2. Default 0.
3912 // 7 Reserved. Default 0.
3913 // 6 RW de_venc_pol: 1= Invert DE polarity from VENC. Default 0.
3914 // 5 RW hsync_venc_pol: 1= Invert HS polarity from VENC. Default 0.
3915 // 4 RW vsync_venc_pol: 1= Invert VS polarity from VENC. Default 0.
3916 // 3 RW dpicolorm: Signal to IP. Default 0.
3917 // 2 RW dpishutdn: Signal to IP. Default 0.
3918 // 1 Reserved. Default 0.
3919 // 0 Reserved. Default 0.
3920 #define MIPI_DSI_TOP_CNTL (0x18f2)
3921 #define P_MIPI_DSI_TOP_CNTL (volatile uint32_t *)((0x18f2 << 2) + 0xffd00000)
3922 // 31:16 Reserved. Default 0.
3923 // 15: 8 RW suspend_frame_rate: Define rate of timed-suspend. Default 0.
3924 // 0=Execute suspend every frame; 1=Every other frame; ...; 255=Every 256 frame.
3925 // 7: 3 Reserved. Default 0.
3926 // 2 RW timed_suspend_en: 1=Enable timed suspend VencL. 0=Disable timed suspend. Default 0.
3927 // 1 RW manual_suspend_en: 1=Enable manual suspend VencL. 1=Cancel manual suspend VencL. Default 0.
3928 // 0 RW suspend_on_edpihalt:1=Enable IP's edpihalt signal to suspend VencL; 0=IP's edpihalt signal does not affect VencL. Default 1.
3929 #define MIPI_DSI_TOP_SUSPEND_CNTL (0x18f3)
3930 #define P_MIPI_DSI_TOP_SUSPEND_CNTL (volatile uint32_t *)((0x18f3 << 2) + 0xffd00000)
3931 // 31:29 Reserved. Default 0.
3932 // 28:16 RW suspend_line_end: Define timed-suspend region. Suspend from [pix_start,line_start] to [pix_end,line_end]. Default 0.
3933 // 15:13 Reserved. Default 0.
3934 // 12: 0 RW suspend_line_start: Define timed-suspend region. Suspend from [pix_start,line_start] to [pix_end,line_end]. Default 0.
3935 #define MIPI_DSI_TOP_SUSPEND_LINE (0x18f4)
3936 #define P_MIPI_DSI_TOP_SUSPEND_LINE (volatile uint32_t *)((0x18f4 << 2) + 0xffd00000)
3937 // 31:29 Reserved. Default 0.
3938 // 28:16 RW suspend_pix_end: Define timed-suspend region. Suspend from [pix_start,line_start] to [pix_end,line_end]. Default 0.
3939 // 15:13 Reserved. Default 0.
3940 // 12: 0 RW suspend_pix_start: Define timed-suspend region. Suspend from [pix_start,line_start] to [pix_end,line_end]. Default 0.
3941 #define MIPI_DSI_TOP_SUSPEND_PIX (0x18f5)
3942 #define P_MIPI_DSI_TOP_SUSPEND_PIX (volatile uint32_t *)((0x18f5 << 2) + 0xffd00000)
3943 // 31:20 Reserved. Default 0.
3944 // 19:10 RW meas_vsync: Control on measuring Host Controller's vsync. Default 0.
3945 // [ 19] meas_en: 1=Enable measurement
3946 // [ 18] accum_meas_en: 0=meas_count is cleared at the end of each measure;
3947 // 1=meas_count is accumulated at the end of each measure.
3948 // [17:10] vsync_span: Define the duration of a measure is to last for how many Vsyncs.
3949 // 9: 0 RW meas_edpite: Control on measuring Display Slave's edpite. Default 0.
3950 // [ 9] meas_en: 1=Enable measurement
3951 // [ 8] accum_meas_en: 0=meas_count is cleared at the end of each measure;
3952 // 1=meas_count is accumulated at the end of each measure.
3953 // [ 7: 0] edpite_span: Define the duration of a measure is to last for how many edpite.
3954 #define MIPI_DSI_TOP_MEAS_CNTL (0x18f6)
3955 #define P_MIPI_DSI_TOP_MEAS_CNTL (volatile uint32_t *)((0x18f6 << 2) + 0xffd00000)
3956 // 31 R stat_edpihalt: status of edpihalt signal from IP. Default 0.
3957 // 30:29 Reserved. Default 0.
3958 // 28:16 R stat_te_line: Snapshot of Host's line position at edpite. Default 0.
3959 // 15:13 Reserved. Default 0.
3960 // 12: 0 R stat_te_pix: Snapshot of Host's pixel position at edpite. Default 0.
3961 #define MIPI_DSI_TOP_STAT (0x18f7)
3962 #define P_MIPI_DSI_TOP_STAT (volatile uint32_t *)((0x18f7 << 2) + 0xffd00000)
3963 // To measure display slave's frame rate, we can use a reference clock to measure the duration of one of more edpite pulse(s).
3964 // Measurement control is by register MIPI_DSI_TOP_MEAS_CNTL bit[9:0].
3965 // Reference clock comes from clk_rst_tst.cts_dsi_meas_clk, and is defined by HIU register HHI_VDIN_MEAS_CLK_CNTL bit[23:12].
3966 // Mesurement result is in MIPI_DSI_TOP_MEAS_STAT_TE0 and MIPI_DSI_TOP_MEAS_STAT_TE1, as below:
3967 // edpite_meas_count[47:0]: Number of reference clock cycles counted during one measure period (non-incremental measure), or
3968 // during all measure periods so far (incremental measure).
3969 // edpite_meas_count_n[3:0]:Number of measure periods has been done. Number can wrap over.
3970 //
3971 // 31: 0 R edpite_meas_count[31:0]. Default 0.
3972 #define MIPI_DSI_TOP_MEAS_STAT_TE0 (0x18f8)
3973 #define P_MIPI_DSI_TOP_MEAS_STAT_TE0 (volatile uint32_t *)((0x18f8 << 2) + 0xffd00000)
3974 // 19:16 R edpite_meas_count_n. Default 0.
3975 // 15: 0 R edpite_meas_count[47:32]. Default 0.
3976 #define MIPI_DSI_TOP_MEAS_STAT_TE1 (0x18f9)
3977 #define P_MIPI_DSI_TOP_MEAS_STAT_TE1 (volatile uint32_t *)((0x18f9 << 2) + 0xffd00000)
3978 // To measure Host's frame rate, we can use a reference clock to measure the duration of one of more Vsync pulse(s).
3979 // Measurement control is by register MIPI_DSI_TOP_MEAS_CNTL bit[19:10].
3980 // Reference clock comes from clk_rst_tst.cts_dsi_meas_clk, and is defined by HIU register HHI_VDIN_MEAS_CLK_CNTL bit[23:12].
3981 // Mesurement result is in MIPI_DSI_TOP_MEAS_STAT_VS0 and MIPI_DSI_TOP_MEAS_STAT_VS1, as below:
3982 // vsync_meas_count[47:0]: Number of reference clock cycles counted during one measure period (non-incremental measure), or
3983 // during all measure periods so far (incremental measure).
3984 // vsync_meas_count_n[3:0]: Number of measure periods has been done. Number can wrap over.
3985 //
3986 // 31: 0 R vsync_meas_count[31:0]. Default 0.
3987 #define MIPI_DSI_TOP_MEAS_STAT_VS0 (0x18fa)
3988 #define P_MIPI_DSI_TOP_MEAS_STAT_VS0 (volatile uint32_t *)((0x18fa << 2) + 0xffd00000)
3989 // 19:16 R vsync_meas_count_n. Default 0.
3990 // 15: 0 R vsync_meas_count[47:32]. Default 0.
3991 #define MIPI_DSI_TOP_MEAS_STAT_VS1 (0x18fb)
3992 #define P_MIPI_DSI_TOP_MEAS_STAT_VS1 (volatile uint32_t *)((0x18fb << 2) + 0xffd00000)
3993 // 31:16 RW intr_stat/clr. For each bit, read as this interrupt level status, write 1 to clear. Default 0.
3994 // Note: To clear the interrupt level, simply write 1 to the specific bit, no need to write 0 afterwards.
3995 // [31:22] Reserved
3996 // [ 21] stat/clr of EOF interrupt
3997 // [ 20] stat/clr of de_fall interrupt
3998 // [ 19] stat/clr of de_rise interrupt
3999 // [ 18] stat/clr of vs_fall interrupt
4000 // [ 17] stat/clr of vs_rise interrupt
4001 // [ 16] stat/clr of dwc_edpite interrupt
4002 // 15: 0 RW intr_enable. For each bit, 1=enable this interrupt, 0=disable. Default 0.
4003 // [15: 6] Reserved
4004 // [ 5] EOF (End_Of_Field) interrupt
4005 // [ 4] de_fall interrupt
4006 // [ 3] de_rise interrupt
4007 // [ 2] vs_fall interrupt
4008 // [ 1] vs_rise interrupt
4009 // [ 0] dwc_edpite interrupt
4010 #define MIPI_DSI_TOP_INTR_CNTL_STAT (0x18fc)
4011 #define P_MIPI_DSI_TOP_INTR_CNTL_STAT (volatile uint32_t *)((0x18fc << 2) + 0xffd00000)
4012 // 31: 2 Reserved. Default 0.
4013 // 1: 0 RW mem_pd. Default 3.
4014 #define MIPI_DSI_TOP_MEM_PD (0x18fd)
4015 #define P_MIPI_DSI_TOP_MEM_PD (volatile uint32_t *)((0x18fd << 2) + 0xffd00000)
4016 // synopsys translate_off
4017 // synopsys translate_on
4018 //
4019 // Closing file: dsi_regs.h
4020 //
4021 //======================================
4022 // CPU Assist module
4023 //
4024 //======================================
4025 // -----------------------------------------------
4026 // CBUS_BASE: ASSIST_CBUS_BASE = 0x20
4027 // -----------------------------------------------
4028 //`define ASSIST_AMR_MBOX1_INT 8'h4d
4029 //`define ASSIST_AMR_MBOX2_INT 8'h4e
4030 #define ASSIST_AMR_SCRATCH0 (0x204f)
4031 #define P_ASSIST_AMR_SCRATCH0 (volatile uint32_t *)((0x204f << 2) + 0xffd00000)
4032 #define ASSIST_AMR_SCRATCH1 (0x2050)
4033 #define P_ASSIST_AMR_SCRATCH1 (volatile uint32_t *)((0x2050 << 2) + 0xffd00000)
4034 #define ASSIST_AMR_SCRATCH2 (0x2051)
4035 #define P_ASSIST_AMR_SCRATCH2 (volatile uint32_t *)((0x2051 << 2) + 0xffd00000)
4036 #define ASSIST_AMR_SCRATCH3 (0x2052)
4037 #define P_ASSIST_AMR_SCRATCH3 (volatile uint32_t *)((0x2052 << 2) + 0xffd00000)
4038 #define ASSIST_HW_REV (0x2053)
4039 #define P_ASSIST_HW_REV (volatile uint32_t *)((0x2053 << 2) + 0xffd00000)
4040 //`define ASSIST_CBUS_ARB 8'h54
4041 #define ASSIST_POR_CONFIG (0x2055)
4042 #define P_ASSIST_POR_CONFIG (volatile uint32_t *)((0x2055 << 2) + 0xffd00000)
4043 #define ASSIST_SPARE16_REG1 (0x2056)
4044 #define P_ASSIST_SPARE16_REG1 (volatile uint32_t *)((0x2056 << 2) + 0xffd00000)
4045 #define ASSIST_SPARE16_REG2 (0x2057)
4046 #define P_ASSIST_SPARE16_REG2 (volatile uint32_t *)((0x2057 << 2) + 0xffd00000)
4047 #define ASSIST_SPARE8_REG1 (0x2058)
4048 #define P_ASSIST_SPARE8_REG1 (volatile uint32_t *)((0x2058 << 2) + 0xffd00000)
4049 #define ASSIST_SPARE8_REG2 (0x2059)
4050 #define P_ASSIST_SPARE8_REG2 (volatile uint32_t *)((0x2059 << 2) + 0xffd00000)
4051 // Duplicate Address...when used please move to a new address
4052 // `define TO_AMRISC_REG 8'h59 // for amrisc
4053 #define ASSIST_SPARE8_REG3 (0x205a)
4054 #define P_ASSIST_SPARE8_REG3 (volatile uint32_t *)((0x205a << 2) + 0xffd00000)
4055 // Duplicate Address...when used please move to a new address
4056 // `define FROM_AMRISC_REG 8'h5a // for amrisc
4057 // Duplicate Address...when used please move to a new address
4058 // `define MPEG2_DECODER_CONTROL 8'h5b // for amrisc
4059 #define AC3_CTRL_REG1 (0x205b)
4060 #define P_AC3_CTRL_REG1 (volatile uint32_t *)((0x205b << 2) + 0xffd00000)
4061 #define AC3_CTRL_REG2 (0x205c)
4062 #define P_AC3_CTRL_REG2 (volatile uint32_t *)((0x205c << 2) + 0xffd00000)
4063 #define AC3_CTRL_REG3 (0x205d)
4064 #define P_AC3_CTRL_REG3 (volatile uint32_t *)((0x205d << 2) + 0xffd00000)
4065 #define AC3_CTRL_REG4 (0x205e)
4066 #define P_AC3_CTRL_REG4 (volatile uint32_t *)((0x205e << 2) + 0xffd00000)
4067 //`define ASSIST_PMEM_SPLIT 8'h5f
4068 #define ASSIST_GEN_CNTL (0x2068)
4069 #define P_ASSIST_GEN_CNTL (volatile uint32_t *)((0x2068 << 2) + 0xffd00000)
4070 #define EE_ASSIST_MBOX0_IRQ_REG (0x2070)
4071 #define P_EE_ASSIST_MBOX0_IRQ_REG (volatile uint32_t *)((0x2070 << 2) + 0xffd00000)
4072 #define EE_ASSIST_MBOX0_CLR_REG (0x2071)
4073 #define P_EE_ASSIST_MBOX0_CLR_REG (volatile uint32_t *)((0x2071 << 2) + 0xffd00000)
4074 #define EE_ASSIST_MBOX0_MASK (0x2072)
4075 #define P_EE_ASSIST_MBOX0_MASK (volatile uint32_t *)((0x2072 << 2) + 0xffd00000)
4076 #define EE_ASSIST_MBOX0_FIQ_SEL (0x2073)
4077 #define P_EE_ASSIST_MBOX0_FIQ_SEL (volatile uint32_t *)((0x2073 << 2) + 0xffd00000)
4078 #define EE_ASSIST_MBOX1_IRQ_REG (0x2074)
4079 #define P_EE_ASSIST_MBOX1_IRQ_REG (volatile uint32_t *)((0x2074 << 2) + 0xffd00000)
4080 #define EE_ASSIST_MBOX1_CLR_REG (0x2075)
4081 #define P_EE_ASSIST_MBOX1_CLR_REG (volatile uint32_t *)((0x2075 << 2) + 0xffd00000)
4082 #define EE_ASSIST_MBOX1_MASK (0x2076)
4083 #define P_EE_ASSIST_MBOX1_MASK (volatile uint32_t *)((0x2076 << 2) + 0xffd00000)
4084 #define EE_ASSIST_MBOX1_FIQ_SEL (0x2077)
4085 #define P_EE_ASSIST_MBOX1_FIQ_SEL (volatile uint32_t *)((0x2077 << 2) + 0xffd00000)
4086 #define EE_ASSIST_MBOX2_IRQ_REG (0x2078)
4087 #define P_EE_ASSIST_MBOX2_IRQ_REG (volatile uint32_t *)((0x2078 << 2) + 0xffd00000)
4088 #define EE_ASSIST_MBOX2_CLR_REG (0x2079)
4089 #define P_EE_ASSIST_MBOX2_CLR_REG (volatile uint32_t *)((0x2079 << 2) + 0xffd00000)
4090 #define EE_ASSIST_MBOX2_MASK (0x207a)
4091 #define P_EE_ASSIST_MBOX2_MASK (volatile uint32_t *)((0x207a << 2) + 0xffd00000)
4092 #define EE_ASSIST_MBOX2_FIQ_SEL (0x207b)
4093 #define P_EE_ASSIST_MBOX2_FIQ_SEL (volatile uint32_t *)((0x207b << 2) + 0xffd00000)
4094 #define EE_ASSIST_MBOX3_IRQ_REG (0x207c)
4095 #define P_EE_ASSIST_MBOX3_IRQ_REG (volatile uint32_t *)((0x207c << 2) + 0xffd00000)
4096 #define EE_ASSIST_MBOX3_CLR_REG (0x207d)
4097 #define P_EE_ASSIST_MBOX3_CLR_REG (volatile uint32_t *)((0x207d << 2) + 0xffd00000)
4098 #define EE_ASSIST_MBOX3_MASK (0x207e)
4099 #define P_EE_ASSIST_MBOX3_MASK (volatile uint32_t *)((0x207e << 2) + 0xffd00000)
4100 #define EE_ASSIST_MBOX3_FIQ_SEL (0x207f)
4101 #define P_EE_ASSIST_MBOX3_FIQ_SEL (volatile uint32_t *)((0x207f << 2) + 0xffd00000)
4102 // synopsys translate_off
4103 // synopsys translate_on
4104 //
4105 // Closing file: ./register_map.h
4106 //
4107 //
4108 // Reading file: ./vcbus_regs.h
4109 //
4110 // synopsys translate_off
4111 // synopsys translate_on
4112 //===========================================================================
4113 //`define RDMA_VCBUS_BASE 8'h11
4114 //===========================================================================
4115 //
4116 // Reading file: rdma_regs.h
4117 //
4118 //===========================================================================
4119 // RDMA registers 0x00 - 0xff
4120 //===========================================================================
4121 // -----------------------------------------------
4122 // CBUS_BASE: RDMA_VCBUS_BASE = 0x11
4123 // -----------------------------------------------
4124 // Bit 31: 0 RW AHB start address for manual start DMA
4125 #define RDMA_AHB_START_ADDR_MAN (0x1100)
4126 #define P_RDMA_AHB_START_ADDR_MAN (volatile uint32_t *)((0x1100 << 2) + 0xff900000)
4127 // Bit 31: 0 RW AHB end address for manual start DMA
4128 #define RDMA_AHB_END_ADDR_MAN (0x1101)
4129 #define P_RDMA_AHB_END_ADDR_MAN (volatile uint32_t *)((0x1101 << 2) + 0xff900000)
4130 // Bit 31: 0 RW AHB start address for auto start source 1
4131 #define RDMA_AHB_START_ADDR_1 (0x1102)
4132 #define P_RDMA_AHB_START_ADDR_1 (volatile uint32_t *)((0x1102 << 2) + 0xff900000)
4133 // Bit 31: 0 RW AHB end address for auto start source 1
4134 #define RDMA_AHB_END_ADDR_1 (0x1103)
4135 #define P_RDMA_AHB_END_ADDR_1 (volatile uint32_t *)((0x1103 << 2) + 0xff900000)
4136 // Bit 31: 0 RW AHB start address for auto start source 2
4137 #define RDMA_AHB_START_ADDR_2 (0x1104)
4138 #define P_RDMA_AHB_START_ADDR_2 (volatile uint32_t *)((0x1104 << 2) + 0xff900000)
4139 // Bit 31: 0 RW AHB end address for auto start source 2
4140 #define RDMA_AHB_END_ADDR_2 (0x1105)
4141 #define P_RDMA_AHB_END_ADDR_2 (volatile uint32_t *)((0x1105 << 2) + 0xff900000)
4142 // Bit 31: 0 RW AHB start address for auto start source 3
4143 #define RDMA_AHB_START_ADDR_3 (0x1106)
4144 #define P_RDMA_AHB_START_ADDR_3 (volatile uint32_t *)((0x1106 << 2) + 0xff900000)
4145 // Bit 31: 0 RW AHB end address for auto start source 3
4146 #define RDMA_AHB_END_ADDR_3 (0x1107)
4147 #define P_RDMA_AHB_END_ADDR_3 (volatile uint32_t *)((0x1107 << 2) + 0xff900000)
4148 // Bit 31: 0 RW AHB start address for auto start source 4
4149 #define RDMA_AHB_START_ADDR_4 (0x1108)
4150 #define P_RDMA_AHB_START_ADDR_4 (volatile uint32_t *)((0x1108 << 2) + 0xff900000)
4151 // Bit 31: 0 RW AHB end address for auto start source 4
4152 #define RDMA_AHB_END_ADDR_4 (0x1109)
4153 #define P_RDMA_AHB_END_ADDR_4 (volatile uint32_t *)((0x1109 << 2) + 0xff900000)
4154 // Bit 31: 0 RW AHB start address for auto start source 5
4155 #define RDMA_AHB_START_ADDR_5 (0x110a)
4156 #define P_RDMA_AHB_START_ADDR_5 (volatile uint32_t *)((0x110a << 2) + 0xff900000)
4157 // Bit 31: 0 RW AHB end address for auto start source 5
4158 #define RDMA_AHB_END_ADDR_5 (0x110b)
4159 #define P_RDMA_AHB_END_ADDR_5 (volatile uint32_t *)((0x110b << 2) + 0xff900000)
4160 // Bit 31: 0 RW AHB start address for auto start source 6
4161 #define RDMA_AHB_START_ADDR_6 (0x110c)
4162 #define P_RDMA_AHB_START_ADDR_6 (volatile uint32_t *)((0x110c << 2) + 0xff900000)
4163 // Bit 31: 0 RW AHB end address for auto start source 6
4164 #define RDMA_AHB_END_ADDR_6 (0x110d)
4165 #define P_RDMA_AHB_END_ADDR_6 (volatile uint32_t *)((0x110d << 2) + 0xff900000)
4166 // Bit 31: 0 RW AHB start address for auto start source 7
4167 #define RDMA_AHB_START_ADDR_7 (0x110e)
4168 #define P_RDMA_AHB_START_ADDR_7 (volatile uint32_t *)((0x110e << 2) + 0xff900000)
4169 // Bit 31: 0 RW AHB end address for auto start source 7
4170 #define RDMA_AHB_END_ADDR_7 (0x110f)
4171 #define P_RDMA_AHB_END_ADDR_7 (volatile uint32_t *)((0x110f << 2) + 0xff900000)
4172 // Auto start DMA control:
4173 // Bit 31:24 RW ctrl_enable_int_3. Interrupt inputs enable mask for source 3.
4174 // Bit 23:16 RW ctrl_enable_int_2. Interrupt inputs enable mask for source 2.
4175 // Bit 15: 8 RW ctrl_enable_int_1. Interrupt inputs enable mask for source 1.
4176 // Bit 7 RW ctrl_cbus_write_3. Register read/write mode for auto-start 3. 1=Register write; 0=Register read.
4177 // Bit 6 RW ctrl_cbus_write_3. Register read/write mode for auto-start 2. 1=Register write; 0=Register read.
4178 // Bit 5 RW ctrl_cbus_write_3. Register read/write mode for auto-start 1. 1=Register write; 0=Register read.
4179 // Bit 4 R Rsrv.
4180 // Bit 3 RW ctrl_cbus_addr_incr_3. 1=Incremental register access for auto-start 3; 0=Non-incremental (individual) register access.
4181 // Bit 2 RW ctrl_cbus_addr_incr_2. 1=Incremental register access for auto-start 2; 0=Non-incremental (individual) register access.
4182 // Bit 1 RW ctrl_cbus_addr_incr_1. 1=Incremental register access for auto-start 1; 0=Non-incremental (individual) register access.
4183 // Bit 0 R Rsrv.
4184 #define RDMA_ACCESS_AUTO (0x1110)
4185 #define P_RDMA_ACCESS_AUTO (volatile uint32_t *)((0x1110 << 2) + 0xff900000)
4186 #define RDMA_ACCESS_AUTO2 (0x1111)
4187 #define P_RDMA_ACCESS_AUTO2 (volatile uint32_t *)((0x1111 << 2) + 0xff900000)
4188 #define RDMA_ACCESS_AUTO3 (0x1112)
4189 #define P_RDMA_ACCESS_AUTO3 (volatile uint32_t *)((0x1112 << 2) + 0xff900000)
4190 // Manual start DMA control:
4191 // Bit 31: 3 R Rsrv.
4192 // Bit 2 RW ctrl_cbus_write_man. Register read/write mode for manual-start. 1=Register write; 0=Register read.
4193 // Bit 1 RW ctrl_cbus_addr_incr_man. 1=Incremental register access for manual-start; 0=Non-incremental (individual) register access.
4194 // Bit 0 W ctrl_start_man. Write 1 to this bit to manual-start DMA. This bit always read back 0.
4195 #define RDMA_ACCESS_MAN (0x1113)
4196 #define P_RDMA_ACCESS_MAN (volatile uint32_t *)((0x1113 << 2) + 0xff900000)
4197 // RDMA general control:
4198 // Bit 31:25 R Rsrv.
4199 // Bit 24 W ctrl_clr_rdma_done_int. Write 1 to reset rdma_int level to 0. No need to clear this bit.
4200 // Bit 23:19 R Rsrv.
4201 // Bit 18:13 R Rsrv.
4202 // Bit 12: 7 R Rsrv.
4203 // Bit 6 RW ctrl_ddr_urgent.
4204 // Bit 5: 4 RW ctrl_ahb_wr_burst_size. 0=ABH write request burst size 16;
4205 // 1=ABH write request burst size 24;
4206 // 2=ABH write request burst size 32;
4207 // 3=ABH write request burst size 48.
4208 // Bit 3: 2 RW ctrl_ahb_rd_burst_size. 0=ABH read request burst size 16;
4209 // 1=ABH read request burst size 24;
4210 // 2=ABH read request burst size 32;
4211 // 3=ABH read request burst size 48.
4212 // Bit 1 RW ctrl_sw_reset. 1=Reset RDMA logics except register.
4213 // Bit 0 RW ctrl_free_clk_enable. 0=Default, Enable clock gating. 1=No clock gating, enable free clock.
4214 #define RDMA_CTRL (0x1114)
4215 #define P_RDMA_CTRL (volatile uint32_t *)((0x1114 << 2) + 0xff900000)
4216 // Read only.
4217 // Bit 31:29 R Rsrv.
4218 // Bit 28 R rdma_done_int.
4219 // Bit 27:25 R Rsrv.
4220 // Bit 24:18 R ahb_wrfifo_cnt. FIFO for buffering CBus read data to be sent to AHB
4221 // Bit 17:11 R ahb_rdfifo_cnt. FIFO for buffering data read from AHB.
4222 // Bit 10: 8 R ddr_req_st. =0 -- Idle; !=0 -- AHB interfacing ongoing.
4223 // Bit 7: 4 R curr_req. Latest requests that is being/been serviced. E.g. 0000=Idle; 0010=Latest serviced request is Req 1.
4224 // Bit 3: 0 R req_latch. Requests that are yet to be serviced. E.g. 0000=No request; 0001=Req 0 waiting; 1100=Req 2 and 3 waiting.
4225 #define RDMA_STATUS (0x1115)
4226 #define P_RDMA_STATUS (volatile uint32_t *)((0x1115 << 2) + 0xff900000)
4227 #define RDMA_STATUS2 (0x1116)
4228 #define P_RDMA_STATUS2 (volatile uint32_t *)((0x1116 << 2) + 0xff900000)
4229 #define RDMA_STATUS3 (0x1117)
4230 #define P_RDMA_STATUS3 (volatile uint32_t *)((0x1117 << 2) + 0xff900000)
4231 #define RDMA_ACCESS_AUTO4 (0x1118)
4232 #define P_RDMA_ACCESS_AUTO4 (volatile uint32_t *)((0x1118 << 2) + 0xff900000)
4233 #define RDMA_SRAM_CNTL (0x1120)
4234 #define P_RDMA_SRAM_CNTL (volatile uint32_t *)((0x1120 << 2) + 0xff900000)
4235 #define RDMA_SRAM_REGADDR (0x1121)
4236 #define P_RDMA_SRAM_REGADDR (volatile uint32_t *)((0x1121 << 2) + 0xff900000)
4237 #define RDMA_SRAM_REGDATA (0x1122)
4238 #define P_RDMA_SRAM_REGDATA (volatile uint32_t *)((0x1122 << 2) + 0xff900000)
4239 //
4240 // Closing file: rdma_regs.h
4241 //
4242 //===========================================================================
4243 // VDIN
4244 //===========================================================================
4245 // -----------------------------------------------
4246 // CBUS_BASE: VDIN_VCBUS_BASE = 0x12
4247 // -----------------------------------------------
4248 //VDIN0 8'h00 - 8'h7f
4249 //VDIN1 8'h80 - 8'hef
4250 #define VDIN0_OFFSET 0x00
4251 #define VDIN1_OFFSET 0x80
4252
4253 #define VDIN_SCALE_COEF_IDX (0x1200)
4254 #define P_VDIN_SCALE_COEF_IDX (volatile uint32_t *)((0x1200 << 2) + 0xff900000)
4255 #define VDIN_SCALE_COEF (0x1201)
4256 #define P_VDIN_SCALE_COEF (volatile uint32_t *)((0x1201 << 2) + 0xff900000)
4257 //bit 31, mpeg_to_vdin_sel, 0: mpeg source to NR directly, 1: mpeg source pass through here
4258 //bit 30, mpeg_field info which can be written by software
4259 //Bit 29, force go_field, pulse signal
4260 //Bit 28, force go_line, pulse signal
4261 //Bit 27, enable mpeg_go_field input signal
4262 //Bit 26:20, hold lines
4263 //Bit 19, delay go_field function enable
4264 //Bit 18:12, delay go_field line number
4265 //Bit 11:10, component2 output switch, 00: select component0 in, 01: select component1 in, 10: select component2 in
4266 //Bit 9:8, component1 output switch, 00: select component0 in, 01: select component1 in, 10: select component2 in
4267 //Bit 7:6, component0 output switch, 00: select component0 in, 01: select component1 in, 10: select component2 in
4268 //Bit 5, input window selection function enable
4269 //Bit 4, enable VDIN common data input, otherwise there will be no video data input
4270 //Bit 3:0 vdin selection, 1: mpeg_in from dram, 2: bt656 input, 3: component input, 4: tvdecoder input, 5: hdmi rx input, 6: digtial video input, 7: loopback from Viu1, 8: MIPI.
4271 #define VDIN_COM_CTRL0 (0x1202)
4272 #define P_VDIN_COM_CTRL0 (volatile uint32_t *)((0x1202 << 2) + 0xff900000)
4273 //Bit 28:16 active_max_pix_cnt, readonly
4274 //Bit 12:0 active_max_pix_cnt_shadow, readonly
4275 #define VDIN_ACTIVE_MAX_PIX_CNT_STATUS (0x1203)
4276 #define P_VDIN_ACTIVE_MAX_PIX_CNT_STATUS (volatile uint32_t *)((0x1203 << 2) + 0xff900000)
4277 //Bit 28:16 go_line_cnt, readonly
4278 //Bit 12:0 active_line_cnt, readonly
4279 #define VDIN_LCNT_STATUS (0x1204)
4280 #define P_VDIN_LCNT_STATUS (volatile uint32_t *)((0x1204 << 2) + 0xff900000)
4281 //Readonly
4282 //Bit [14:3] lfifo_buf_cnt
4283 //Bit 2, vdin_direct_done status
4284 //Bit 1, vdin_nr_done status
4285 //Bit 0, field
4286 #define VDIN_COM_STATUS0 (0x1205)
4287 #define P_VDIN_COM_STATUS0 (volatile uint32_t *)((0x1205 << 2) + 0xff900000)
4288 //Readonly
4289 //Bit 31, vdi4 fifo overflow
4290 //Bit 29:24, vdi3_asfifo_cnt
4291 //Bit 23, vdi3 fifo overflow
4292 //Bit 21:16, vdi3_asfifo_cnt
4293 //Bit 15, vdi2 fifo overflow
4294 //Bit 13:8, vdi2_asfifo_cnt
4295 //Bit 7, vdi1 fifo overflow
4296 //Bit 5:0, vdi1_asfifo_cnt
4297 #define VDIN_COM_STATUS1 (0x1206)
4298 #define P_VDIN_COM_STATUS1 (volatile uint32_t *)((0x1206 << 2) + 0xff900000)
4299 //Bit 28:16 go_line_cnt_shadow, readonly
4300 //Bit 12:0 active_line_cnt_shadow, readonly
4301 #define VDIN_LCNT_SHADOW_STATUS (0x1207)
4302 #define P_VDIN_LCNT_SHADOW_STATUS (volatile uint32_t *)((0x1207 << 2) + 0xff900000)
4303 //each 8bit asfifo_ctrl is following:
4304 //Bit 7, DE enable
4305 //Bit 6, go field enable
4306 //Bit 5, go line enable
4307 //Bit 4, if true, negative active input vsync
4308 //Bit 3, if true, negative active input hsync
4309 //Bit 2, vsync soft reset fifo enable
4310 //Bit 1, overflow status clear
4311 //Bit 0 asfifo soft reset, level signal
4312 //Bit 7:0 vdi1 asfifo_ctrl
4313 //Bit 23:16 vdi2 asfifo_ctrl
4314 #define VDIN_ASFIFO_CTRL0 (0x1208)
4315 #define P_VDIN_ASFIFO_CTRL0 (volatile uint32_t *)((0x1208 << 2) + 0xff900000)
4316 //Bit 7:0 vdi3 asfifo_ctrl
4317 //Bit 23:16 vdi4 asfifo_ctrl
4318 #define VDIN_ASFIFO_CTRL1 (0x1209)
4319 #define P_VDIN_ASFIFO_CTRL1 (volatile uint32_t *)((0x1209 << 2) + 0xff900000)
4320 //Bit 28:16 input width minus 1, after the window function
4321 //Bit 12:0 output width minus 1
4322 #define VDIN_WIDTHM1I_WIDTHM1O (0x120a)
4323 #define P_VDIN_WIDTHM1I_WIDTHM1O (volatile uint32_t *)((0x120a << 2) + 0xff900000)
4324 //Bit 20:17 prehsc_mode, bit 3:2, prehsc odd line interp mode, bit 1:0, prehsc even line interp mode,
4325 // each 2bit, 00: pix0+pix1/2, average, 01: pix1, 10: pix0
4326 //Bit 16:15 sp422_mode, special mode for the component1 and component2, 00: normal case, 01: 32 64 32, 10: 0 64 64 0, 11: 16 96 16
4327 //Bit 14:8, hsc_ini_pixi_ptr, signed data, only useful when short_lineo_en is true
4328 //Bit 7, prehsc_en
4329 //Bit 6, hsc_en,
4330 //Bit 5, hsc_short_lineo_en, short line output enable
4331 //Bit 4, hsc_nearest_en
4332 //Bit 3, hsc_phase0_always_en
4333 //Bit 2:0, hsc_bank_length
4334 #define VDIN_SC_MISC_CTRL (0x120b)
4335 #define P_VDIN_SC_MISC_CTRL (volatile uint32_t *)((0x120b << 2) + 0xff900000)
4336 //Bit 28:24, integer portion
4337 //Bit 23:0, fraction portion
4338 #define VDIN_HSC_PHASE_STEP (0x120c)
4339 #define P_VDIN_HSC_PHASE_STEP (volatile uint32_t *)((0x120c << 2) + 0xff900000)
4340 //Bit 30:29 hscale rpt_p0_num
4341 //Bit 28:24 hscale ini_rcv_num
4342 //Bit 23:0 hscale ini_phase
4343 #define VDIN_HSC_INI_CTRL (0x120d)
4344 #define P_VDIN_HSC_INI_CTRL (volatile uint32_t *)((0x120d << 2) + 0xff900000)
4345 //Read only
4346 //Bit 23, vdi7 fifo overflow
4347 //Bit 21:16, vdi7_asfifo_cnt
4348 //Bit 15, vdi6 fifo overflow
4349 //Bit 13:8, vdi6_asfifo_cnt
4350 //Bit 7, vdi5 fifo overflow
4351 //Bit 5:0, vdi5_asfifo_cnt
4352 #define VDIN_COM_STATUS2 (0x120e)
4353 #define P_VDIN_COM_STATUS2 (volatile uint32_t *)((0x120e << 2) + 0xff900000)
4354 //Bit 25:16 asfifo decimate control
4355 //Bit 25, if true, decimation counter sync with first valid DE in the field,
4356 //otherwise the decimation counter is not sync with external signal
4357 //Bit 24, decimation de enable
4358 //Bit 23:20, decimation phase, which counter value use to decimate,
4359 //Bit 19:16, decimation number, 0: not decimation, 1: decimation 2, 2: decimation 3 ....
4360 //Bit 7:0 vdi5 asfifo_ctrl
4361 #define VDIN_ASFIFO_CTRL2 (0x120f)
4362 #define P_VDIN_ASFIFO_CTRL2 (volatile uint32_t *)((0x120f << 2) + 0xff900000)
4363 //Bit 7, highlight_en
4364 //Bit 6 probe_post, if true, probe pixel data after matrix, otherwise probe pixel data before matrix
4365 //Bit 5:4 probe_sel, 00: select matrix 0, 01: select matrix 1, otherwise select nothing
4366 //Bit 3:2, matrix coef idx selection, 00: select mat0, 01: select mat1, otherwise slect nothing
4367 //Bit 1 mat1 conversion matrix enable
4368 //Bit 0 mat0 conversion matrix enable
4369 #define VDIN_MATRIX_CTRL (0x1210)
4370 #define P_VDIN_MATRIX_CTRL (volatile uint32_t *)((0x1210 << 2) + 0xff900000)
4371 //Bit 28:16 coef00
4372 //Bit 12:0 coef01
4373 #define VDIN_MATRIX_COEF00_01 (0x1211)
4374 #define P_VDIN_MATRIX_COEF00_01 (volatile uint32_t *)((0x1211 << 2) + 0xff900000)
4375 //Bit 28:16 coef02
4376 //Bit 12:0 coef10
4377 #define VDIN_MATRIX_COEF02_10 (0x1212)
4378 #define P_VDIN_MATRIX_COEF02_10 (volatile uint32_t *)((0x1212 << 2) + 0xff900000)
4379 //Bit 28:16 coef11
4380 //Bit 12:0 coef12
4381 #define VDIN_MATRIX_COEF11_12 (0x1213)
4382 #define P_VDIN_MATRIX_COEF11_12 (volatile uint32_t *)((0x1213 << 2) + 0xff900000)
4383 //Bit 28:16 coef20
4384 //Bit 12:0 coef21
4385 #define VDIN_MATRIX_COEF20_21 (0x1214)
4386 #define P_VDIN_MATRIX_COEF20_21 (volatile uint32_t *)((0x1214 << 2) + 0xff900000)
4387 //BIt 18:16 conv_rs
4388 //Bit 12:0 coef22
4389 #define VDIN_MATRIX_COEF22 (0x1215)
4390 #define P_VDIN_MATRIX_COEF22 (volatile uint32_t *)((0x1215 << 2) + 0xff900000)
4391 //Bit 26:16 offset0
4392 //Bit 10:0 offset1
4393 #define VDIN_MATRIX_OFFSET0_1 (0x1216)
4394 #define P_VDIN_MATRIX_OFFSET0_1 (volatile uint32_t *)((0x1216 << 2) + 0xff900000)
4395 //Bit 10:0 offset2
4396 #define VDIN_MATRIX_OFFSET2 (0x1217)
4397 #define P_VDIN_MATRIX_OFFSET2 (volatile uint32_t *)((0x1217 << 2) + 0xff900000)
4398 //Bit 26:16 pre_offset0
4399 //Bit 10:0 pre_offset1
4400 #define VDIN_MATRIX_PRE_OFFSET0_1 (0x1218)
4401 #define P_VDIN_MATRIX_PRE_OFFSET0_1 (volatile uint32_t *)((0x1218 << 2) + 0xff900000)
4402 //Bit 10:0 pre_offset2
4403 #define VDIN_MATRIX_PRE_OFFSET2 (0x1219)
4404 #define P_VDIN_MATRIX_PRE_OFFSET2 (volatile uint32_t *)((0x1219 << 2) + 0xff900000)
4405 //12:0 lfifo_buf_size
4406 #define VDIN_LFIFO_CTRL (0x121a)
4407 #define P_VDIN_LFIFO_CTRL (volatile uint32_t *)((0x121a << 2) + 0xff900000)
4408 #define VDIN_COM_GCLK_CTRL (0x121b)
4409 #define P_VDIN_COM_GCLK_CTRL (volatile uint32_t *)((0x121b << 2) + 0xff900000)
4410 //12:0 VDIN input interface width minus 1, before the window function, after the de decimation
4411 #define VDIN_INTF_WIDTHM1 (0x121c)
4412 #define P_VDIN_INTF_WIDTHM1 (volatile uint32_t *)((0x121c << 2) + 0xff900000)
4413 //Bit 15 //default== 0, urgent_ctrl_en
4414 //Bit 14 //default== 0, urgent_wr, if true for write buffer
4415 //Bit 13 //default== 0, out_inv_en
4416 //Bit 12 //default == 0, urgent_ini_value
4417 //Bit 11:6 //default == 0, up_th up threshold
4418 //Bit 5:0 //default == 0, dn_th dn threshold
4419 #define VDIN_LFIFO_URG_CTRL (0x121e)
4420 #define P_VDIN_LFIFO_URG_CTRL (volatile uint32_t *)((0x121e << 2) + 0xff900000)
4421 //Bit 8, 1: discard data before line fifo, 0: normal mode
4422 //Bit 7:0 Write chroma canvas address
4423 #define VDIN_WR_CTRL2 (0x121f)
4424 #define P_VDIN_WR_CTRL2 (volatile uint32_t *)((0x121f << 2) + 0xff900000)
4425 //Bit 31:30 hconv_mode, Applicable only to bit[13:12]=0 or 2. 0: Output every even pixels' CbCr;
4426 // 1: Output every odd pixels' CbCr;
4427 // 2: Output an average value per even&odd pair of pixels;
4428 // 3: Output all CbCr. (This does NOT apply to bit[13:12]=0 -- 4:2:2 mode.)
4429 //Bit 29 no_clk_gate: disable vid_wr_mif clock gating function.
4430 //Bit 28 clear write response counter in the vdin write memory interface
4431 //Bit 27 eol_sel, 1: use eol as the line end indication, 0: use width as line end indication in the vdin write memory interface
4432 //Bit 26 vcp_nr_en. Only used in VDIN0. NOT used in VDIN1.
4433 //Bit 25 vcp_wr_en. Only used in VDIN0. NOT used in VDIN1.
4434 //Bit 24 vcp_in_en. Only used in VDIN0. NOT used in VDIN1.
4435 //Bit 23 vdin frame reset enble, if true, it will provide frame reset during go_field(vsync) to the modules after that
4436 //Bit 22 vdin line fifo soft reset enable, meaning, if true line fifo will reset during go_field (vsync)
4437 //Bit 21 vdin direct write done status clear bit
4438 //Bit 20 vdin NR write done status clear bit
4439 //Bit 18 swap_cbcr. Applicable only to bit[13:12]=2. 0: Output CbCr (NV12); 1: Output CrCb (NV21).
4440 //Bit 17:16 vconv_mode, Applicable only to bit[13:12]=2. 0: Output every even lines' CbCr;
4441 // 1: Output every odd lines' CbCr;
4442 // 2: Reserved;
4443 // 3: Output all CbCr.
4444 //Bit 13:12 vdin write format, 0: 4:2:2 to luma canvas, 1: 4:4:4 to luma canvas,
4445 // 2: Y to luma canvas, CbCr to chroma canvas. For NV12/21, also define Bit 31:30, 17:16, and bit 18.
4446 //Bit 11 vdin write canvas double buffer enable, means the canvas address will be latched by vsync before using
4447 //Bit 10 1: disable ctrl_reg write pulse which will reset internal counter. when bit 11 is 1, this bit should be 1.
4448 //Bit 9 vdin write request urgent
4449 //Bit 8 vdin write request enable
4450 //Bit 7:0 Write luma canvas address
4451 #define VDIN_WR_CTRL (0x1220)
4452 #define P_VDIN_WR_CTRL (volatile uint32_t *)((0x1220 << 2) + 0xff900000)
4453 //Bit 29, if true, horizontal reverse
4454 //Bit 28:16 start
4455 //Bit 12:0 end
4456 #define VDIN_WR_H_START_END (0x1221)
4457 #define P_VDIN_WR_H_START_END (volatile uint32_t *)((0x1221 << 2) + 0xff900000)
4458 //Bit 29, if true, vertical reverse
4459 //Bit 28:16 start
4460 //Bit 12:0 end
4461 #define VDIN_WR_V_START_END (0x1222)
4462 #define P_VDIN_WR_V_START_END (volatile uint32_t *)((0x1222 << 2) + 0xff900000)
4463 //Bit 24:20, integer portion
4464 //Bit 19:0, fraction portion
4465 #define VDIN_VSC_PHASE_STEP (0x1223)
4466 #define P_VDIN_VSC_PHASE_STEP (volatile uint32_t *)((0x1223 << 2) + 0xff900000)
4467 //Bit 23, vsc_en, vertical scaler enable
4468 //Bit 21 vsc_phase0_always_en, when scale up, you have to set it to 1
4469 //Bit 20:16 ini skip_line_num
4470 //Bit 15:0 vscaler ini_phase
4471 #define VDIN_VSC_INI_CTRL (0x1224)
4472 #define P_VDIN_VSC_INI_CTRL (volatile uint32_t *)((0x1224 << 2) + 0xff900000)
4473 //Bit 28:16, vshrink input height minus 1
4474 //Bit 12:0, scaler input height minus 1
4475 #define VDIN_SCIN_HEIGHTM1 (0x1225)
4476 #define P_VDIN_SCIN_HEIGHTM1 (volatile uint32_t *)((0x1225 << 2) + 0xff900000)
4477 //Bit 23:16, dummy component 0
4478 //Bit 15:8, dummy component 1
4479 //Bit 7:0, dummy component 2
4480 #define VDIN_DUMMY_DATA (0x1226)
4481 #define P_VDIN_DUMMY_DATA (volatile uint32_t *)((0x1226 << 2) + 0xff900000)
4482 //Read only
4483 //Bit 29:20 component 0
4484 //Bit 19:10 component 1
4485 //Bit 9:0 component 2
4486 #define VDIN_MATRIX_PROBE_COLOR (0x1228)
4487 #define P_VDIN_MATRIX_PROBE_COLOR (volatile uint32_t *)((0x1228 << 2) + 0xff900000)
4488 //Bit 23:16 component 0
4489 //Bit 15:8 component 1
4490 //Bit 7:0 component 2
4491 #define VDIN_MATRIX_HL_COLOR (0x1229)
4492 #define P_VDIN_MATRIX_HL_COLOR (volatile uint32_t *)((0x1229 << 2) + 0xff900000)
4493 //28:16 probe x, postion
4494 //12:0 probe y, position
4495 #define VDIN_MATRIX_PROBE_POS (0x122a)
4496 #define P_VDIN_MATRIX_PROBE_POS (volatile uint32_t *)((0x122a << 2) + 0xff900000)
4497 #define VDIN_CHROMA_ADDR_PORT (0x122b)
4498 #define P_VDIN_CHROMA_ADDR_PORT (volatile uint32_t *)((0x122b << 2) + 0xff900000)
4499 #define VDIN_CHROMA_DATA_PORT (0x122c)
4500 #define P_VDIN_CHROMA_DATA_PORT (volatile uint32_t *)((0x122c << 2) + 0xff900000)
4501 //
4502 #define VDIN_CM_BRI_CON_CTRL (0x122d)
4503 #define P_VDIN_CM_BRI_CON_CTRL (volatile uint32_t *)((0x122d << 2) + 0xff900000)
4504 //Bit 17 clk_cyc_cnt_clr, if true, clear this register
4505 //Bit 16 if true, use vpu clock to count one line, otherwise use actually hsync to count line_cnt
4506 //Bit 15:0 line width using vpu clk
4507 #define VDIN_GO_LINE_CTRL (0x122f)
4508 #define P_VDIN_GO_LINE_CTRL (volatile uint32_t *)((0x122f << 2) + 0xff900000)
4509 //Bit 31:24 hist_pix_white_th, larger than this th is counted as white pixel
4510 //Bit 23:16 hist_pix_black_th, less than this th is counted as black pixel
4511 //Bit 11 hist_34bin_only, 34 bin only mode, including white/black
4512 //Bit 10:9 ldim_stts_din_sel, 00: from matrix0 dout, 01: from vsc_dout, 10: from matrix1 dout, 11: form matrix1 din
4513 //Bit 8 ldim_stts_en
4514 //Bit 6:5 hist_dnlp_low the real pixels in each bins got by VDIN_DNLP_HISTXX should multiple with 2^(dnlp_low+3)
4515 //Bit 3:2 hist_din_sel the source used for hist statistics. 00: from matrix0 dout, 01: from vsc_dout, 10: from matrix1 dout, 11: form matrix1 din
4516 //Bit 1 hist_win_en 1'b0: hist used for full picture; 1'b1: hist used for pixels within hist window
4517 //Bit 0 hist_spl_en 1'b0: disable hist readback; 1'b1: enable hist readback
4518 #define VDIN_HIST_CTRL (0x1230)
4519 #define P_VDIN_HIST_CTRL (volatile uint32_t *)((0x1230 << 2) + 0xff900000)
4520 //Bit 28:16 hist_hstart horizontal start value to define hist window
4521 //Bit 12:0 hist_hend horizontal end value to define hist window
4522 #define VDIN_HIST_H_START_END (0x1231)
4523 #define P_VDIN_HIST_H_START_END (volatile uint32_t *)((0x1231 << 2) + 0xff900000)
4524 //Bit 28:16 hist_vstart vertical start value to define hist window
4525 //Bit 12:0 hist_vend vertical end value to define hist window
4526 #define VDIN_HIST_V_START_END (0x1232)
4527 #define P_VDIN_HIST_V_START_END (volatile uint32_t *)((0x1232 << 2) + 0xff900000)
4528 //Bit 15:8 hist_max maximum value
4529 //Bit 7:0 hist_min minimum value
4530 //read only
4531 #define VDIN_HIST_MAX_MIN (0x1233)
4532 #define P_VDIN_HIST_MAX_MIN (volatile uint32_t *)((0x1233 << 2) + 0xff900000)
4533 //Bit 31:0 hist_spl_rd
4534 //counts for the total luma value
4535 //read only
4536 #define VDIN_HIST_SPL_VAL (0x1234)
4537 #define P_VDIN_HIST_SPL_VAL (volatile uint32_t *)((0x1234 << 2) + 0xff900000)
4538 //Bit 21:0 hist_spl_pixel_count
4539 //counts for the total calculated pixels
4540 //read only
4541 #define VDIN_HIST_SPL_PIX_CNT (0x1235)
4542 #define P_VDIN_HIST_SPL_PIX_CNT (volatile uint32_t *)((0x1235 << 2) + 0xff900000)
4543 //Bit 31:0 hist_chroma_sum
4544 //counts for the total chroma value
4545 //read only
4546 #define VDIN_HIST_CHROMA_SUM (0x1236)
4547 #define P_VDIN_HIST_CHROMA_SUM (volatile uint32_t *)((0x1236 << 2) + 0xff900000)
4548 //Bit 31:16 higher hist bin
4549 //Bit 15:0 lower hist bin
4550 //0-255 are splited to 64 bins evenly, and VDIN_DNLP_HISTXX
4551 //are the statistic number of pixels that within each bin.
4552 //VDIN_DNLP_HIST00[15:0] counts for the first bin
4553 //VDIN_DNLP_HIST00[31:16] counts for the second bin
4554 //VDIN_DNLP_HIST01[15:0] counts for the third bin
4555 //VDIN_DNLP_HIST01[31:16] counts for the fourth bin
4556 //etc...
4557 //read only
4558 #define VDIN_DNLP_HIST00 (0x1237)
4559 #define P_VDIN_DNLP_HIST00 (volatile uint32_t *)((0x1237 << 2) + 0xff900000)
4560 #define VDIN_DNLP_HIST01 (0x1238)
4561 #define P_VDIN_DNLP_HIST01 (volatile uint32_t *)((0x1238 << 2) + 0xff900000)
4562 #define VDIN_DNLP_HIST02 (0x1239)
4563 #define P_VDIN_DNLP_HIST02 (volatile uint32_t *)((0x1239 << 2) + 0xff900000)
4564 #define VDIN_DNLP_HIST03 (0x123a)
4565 #define P_VDIN_DNLP_HIST03 (volatile uint32_t *)((0x123a << 2) + 0xff900000)
4566 #define VDIN_DNLP_HIST04 (0x123b)
4567 #define P_VDIN_DNLP_HIST04 (volatile uint32_t *)((0x123b << 2) + 0xff900000)
4568 #define VDIN_DNLP_HIST05 (0x123c)
4569 #define P_VDIN_DNLP_HIST05 (volatile uint32_t *)((0x123c << 2) + 0xff900000)
4570 #define VDIN_DNLP_HIST06 (0x123d)
4571 #define P_VDIN_DNLP_HIST06 (volatile uint32_t *)((0x123d << 2) + 0xff900000)
4572 #define VDIN_DNLP_HIST07 (0x123e)
4573 #define P_VDIN_DNLP_HIST07 (volatile uint32_t *)((0x123e << 2) + 0xff900000)
4574 #define VDIN_DNLP_HIST08 (0x123f)
4575 #define P_VDIN_DNLP_HIST08 (volatile uint32_t *)((0x123f << 2) + 0xff900000)
4576 #define VDIN_DNLP_HIST09 (0x1240)
4577 #define P_VDIN_DNLP_HIST09 (volatile uint32_t *)((0x1240 << 2) + 0xff900000)
4578 #define VDIN_DNLP_HIST10 (0x1241)
4579 #define P_VDIN_DNLP_HIST10 (volatile uint32_t *)((0x1241 << 2) + 0xff900000)
4580 #define VDIN_DNLP_HIST11 (0x1242)
4581 #define P_VDIN_DNLP_HIST11 (volatile uint32_t *)((0x1242 << 2) + 0xff900000)
4582 #define VDIN_DNLP_HIST12 (0x1243)
4583 #define P_VDIN_DNLP_HIST12 (volatile uint32_t *)((0x1243 << 2) + 0xff900000)
4584 #define VDIN_DNLP_HIST13 (0x1244)
4585 #define P_VDIN_DNLP_HIST13 (volatile uint32_t *)((0x1244 << 2) + 0xff900000)
4586 #define VDIN_DNLP_HIST14 (0x1245)
4587 #define P_VDIN_DNLP_HIST14 (volatile uint32_t *)((0x1245 << 2) + 0xff900000)
4588 #define VDIN_DNLP_HIST15 (0x1246)
4589 #define P_VDIN_DNLP_HIST15 (volatile uint32_t *)((0x1246 << 2) + 0xff900000)
4590 #define VDIN_DNLP_HIST16 (0x1247)
4591 #define P_VDIN_DNLP_HIST16 (volatile uint32_t *)((0x1247 << 2) + 0xff900000)
4592 #define VDIN_DNLP_HIST17 (0x1248)
4593 #define P_VDIN_DNLP_HIST17 (volatile uint32_t *)((0x1248 << 2) + 0xff900000)
4594 #define VDIN_DNLP_HIST18 (0x1249)
4595 #define P_VDIN_DNLP_HIST18 (volatile uint32_t *)((0x1249 << 2) + 0xff900000)
4596 #define VDIN_DNLP_HIST19 (0x124a)
4597 #define P_VDIN_DNLP_HIST19 (volatile uint32_t *)((0x124a << 2) + 0xff900000)
4598 #define VDIN_DNLP_HIST20 (0x124b)
4599 #define P_VDIN_DNLP_HIST20 (volatile uint32_t *)((0x124b << 2) + 0xff900000)
4600 #define VDIN_DNLP_HIST21 (0x124c)
4601 #define P_VDIN_DNLP_HIST21 (volatile uint32_t *)((0x124c << 2) + 0xff900000)
4602 #define VDIN_DNLP_HIST22 (0x124d)
4603 #define P_VDIN_DNLP_HIST22 (volatile uint32_t *)((0x124d << 2) + 0xff900000)
4604 #define VDIN_DNLP_HIST23 (0x124e)
4605 #define P_VDIN_DNLP_HIST23 (volatile uint32_t *)((0x124e << 2) + 0xff900000)
4606 #define VDIN_DNLP_HIST24 (0x124f)
4607 #define P_VDIN_DNLP_HIST24 (volatile uint32_t *)((0x124f << 2) + 0xff900000)
4608 #define VDIN_DNLP_HIST25 (0x1250)
4609 #define P_VDIN_DNLP_HIST25 (volatile uint32_t *)((0x1250 << 2) + 0xff900000)
4610 #define VDIN_DNLP_HIST26 (0x1251)
4611 #define P_VDIN_DNLP_HIST26 (volatile uint32_t *)((0x1251 << 2) + 0xff900000)
4612 #define VDIN_DNLP_HIST27 (0x1252)
4613 #define P_VDIN_DNLP_HIST27 (volatile uint32_t *)((0x1252 << 2) + 0xff900000)
4614 #define VDIN_DNLP_HIST28 (0x1253)
4615 #define P_VDIN_DNLP_HIST28 (volatile uint32_t *)((0x1253 << 2) + 0xff900000)
4616 #define VDIN_DNLP_HIST29 (0x1254)
4617 #define P_VDIN_DNLP_HIST29 (volatile uint32_t *)((0x1254 << 2) + 0xff900000)
4618 #define VDIN_DNLP_HIST30 (0x1255)
4619 #define P_VDIN_DNLP_HIST30 (volatile uint32_t *)((0x1255 << 2) + 0xff900000)
4620 #define VDIN_DNLP_HIST31 (0x1256)
4621 #define P_VDIN_DNLP_HIST31 (volatile uint32_t *)((0x1256 << 2) + 0xff900000)
4622 //Bit 31, local dimming statistic enable
4623 //Bit 28, eol enable
4624 //Bit 27:25, vertical line overlap number for max finding
4625 //Bit 24:22, horizontal pixel overlap number, 0: 17 pix, 1: 9 pix, 2: 5 pix, 3: 3 pix, 4: 0 pix
4626 //Bit 20, 1,2,1 low pass filter enable before max/hist statistic
4627 //Bit 19:16, region H/V position index, refer to VDIN_LDIM_STTS_HIST_SET_REGION
4628 //Bit 15, 1: region read index auto increase per read to VDIN_LDIM_STTS_HIST_READ_REGION
4629 //Bit 6:0, region read index
4630 #define VDIN_LDIM_STTS_HIST_REGION_IDX (0x1257)
4631 #define P_VDIN_LDIM_STTS_HIST_REGION_IDX (volatile uint32_t *)((0x1257 << 2) + 0xff900000)
4632 //Bit 28:0, if VDIN_LDIM_STTS_HIST_REGION_IDX[19:16] == 5'h0: read/write hvstart0
4633 // if VDIN_LDIM_STTS_HIST_REGION_IDX[19:16] == 5'h1: read/write hend01
4634 // if VDIN_LDIM_STTS_HIST_REGION_IDX[19:16] == 5'h2: read/write vend01
4635 // if VDIN_LDIM_STTS_HIST_REGION_IDX[19:16] == 5'h3: read/write hend23
4636 // if VDIN_LDIM_STTS_HIST_REGION_IDX[19:16] == 5'h4: read/write vend23
4637 // if VDIN_LDIM_STTS_HIST_REGION_IDX[19:16] == 5'h5: read/write hend45
4638 // if VDIN_LDIM_STTS_HIST_REGION_IDX[19:16] == 5'h6: read/write vend45
4639 // if VDIN_LDIM_STTS_HIST_REGION_IDX[19:16] == 5'd7: read/write hend67
4640 // if VDIN_LDIM_STTS_HIST_REGION_IDX[19:16] == 5'h8: read/write vend67
4641 // if VDIN_LDIM_STTS_HIST_REGION_IDX[19:16] == 5'h9: read/write hend89
4642 // if VDIN_LDIM_STTS_HIST_REGION_IDX[19:16] == 5'ha: read/write vend89
4643 //hvstart0, Bit 28:16 row0 vstart, Bit 12:0 col0 hstart
4644 //hend01, Bit 28:16 col1 hend, Bit 12:0 col0 hend
4645 //vend01, Bit 28:16 row1 vend, Bit 12:0 row0 vend
4646 //hend23, Bit 28:16 col3 hend, Bit 12:0 col2 hend
4647 //vend23, Bit 28:16 row3 vend, Bit 12:0 row2 vend
4648 //hend45, Bit 28:16 col5 hend, Bit 12:0 col4 hend
4649 //vend45, Bit 28:16 row5 vend, Bit 12:0 row4 vend
4650 //hend67, Bit 28:16 col7 hend, Bit 12:0 col6 hend
4651 //vend67, Bit 28:16 row7 vend, Bit 12:0 row6 vend
4652 //hend89, Bit 28:16 col9 hend, Bit 12:0 col8 hend
4653 //vend89, Bit 28:16 row9 vend, Bit 12:0 row8 vend
4654 #define VDIN_LDIM_STTS_HIST_SET_REGION (0x1258)
4655 #define P_VDIN_LDIM_STTS_HIST_SET_REGION (volatile uint32_t *)((0x1258 << 2) + 0xff900000)
4656 //REGION STATISTIC DATA READ OUT PORT, bit 29:20 max_comp2, bit 19:10 max_comp1, bit 9:0 max_comp0
4657 #define VDIN_LDIM_STTS_HIST_READ_REGION (0x1259)
4658 #define P_VDIN_LDIM_STTS_HIST_READ_REGION (volatile uint32_t *)((0x1259 << 2) + 0xff900000)
4659 //Bit 18, reset bit, high active
4660 //Bit 17, if true, widen hs/vs pulse
4661 //Bit 16 vsync total counter always accumulating enable
4662 //Bit 14:12, select hs/vs of video input channel to measure, 0: no selection, 1: vdi1, 2: vid2, 3: vid3, 4:vid4, 5:vdi5, 6:vid6, 7:vdi7, 8: vdi8
4663 //Bit 11:4, vsync_span, define how many vsync span need to measure
4664 //Bit 2:0 meas_hs_index, index to select which HS counter/range
4665 #define VDIN_MEAS_CTRL0 (0x125a)
4666 #define P_VDIN_MEAS_CTRL0 (volatile uint32_t *)((0x125a << 2) + 0xff900000)
4667 //Read only
4668 //19:16 meas_ind_total_count_n, every number of sync_span vsyncs, this count add 1
4669 //15:0 high bit portion of vsync total counter
4670 #define VDIN_MEAS_VS_COUNT_HI (0x125b)
4671 #define P_VDIN_MEAS_VS_COUNT_HI (volatile uint32_t *)((0x125b << 2) + 0xff900000)
4672 //Read only
4673 //31:0, low bit portion of vsync total counter
4674 #define VDIN_MEAS_VS_COUNT_LO (0x125c)
4675 #define P_VDIN_MEAS_VS_COUNT_LO (volatile uint32_t *)((0x125c << 2) + 0xff900000)
4676 //according to the meas_hs_index in register VDIN_MEAS_CTRL0
4677 //meas_hs_index == 0, first hs range
4678 //meas_hs_index == 1, second hs range
4679 //meas_hs_index == 2, third hs range
4680 //meas_hs_index == 3, fourth hs range
4681 //bit 28:16 count_start
4682 //bit 12:0 count_end
4683 #define VDIN_MEAS_HS_RANGE (0x125d)
4684 #define P_VDIN_MEAS_HS_RANGE (volatile uint32_t *)((0x125d << 2) + 0xff900000)
4685 //Read only
4686 //according to the meas_hs_index in register VDIN_MEAS_CTRL0,
4687 //meas_hs_index == 0, first range hs counter,
4688 //meas_hs_index == 1, second range hs coutner
4689 //meas_hs_index == 2, third range hs coutner
4690 //meas_hs_index == 3, fourth range hs coutner
4691 //23:0
4692 #define VDIN_MEAS_HS_COUNT (0x125e)
4693 #define P_VDIN_MEAS_HS_COUNT (volatile uint32_t *)((0x125e << 2) + 0xff900000)
4694 //Bit 8 white_enable
4695 //Bit 7:0 blkbar_white_level
4696 #define VDIN_BLKBAR_CTRL1 (0x125f)
4697 #define P_VDIN_BLKBAR_CTRL1 (volatile uint32_t *)((0x125f << 2) + 0xff900000)
4698 // Bit 31:24 blkbar_black_level threshold to judge a black point
4699 // Bit 23:21 Reserved
4700 // Bit 20:8 blkbar_hwidth left and right region width
4701 // Bit 7:5 blkbar_comp_sel select yin or uin or vin to be the valid input
4702 // Bit 4 blkbar_sw_statistic_en enable software statistic of each block black points number
4703 // Bit 3 blkbar_det_en
4704 // Bit 2:1 blkbar_din_sel
4705 // bit blkbar_det_top_en
4706 #define VDIN_BLKBAR_CTRL0 (0x1260)
4707 #define P_VDIN_BLKBAR_CTRL0 (volatile uint32_t *)((0x1260 << 2) + 0xff900000)
4708 // Bit 31:29 Reserved
4709 // Bit 28:16 blkbar_hstart. Left region start
4710 // Bit 15:13 Reserved
4711 // Bit 12:0 blkbar_hend. Right region end
4712 #define VDIN_BLKBAR_H_START_END (0x1261)
4713 #define P_VDIN_BLKBAR_H_START_END (volatile uint32_t *)((0x1261 << 2) + 0xff900000)
4714 // Bit 31:29 Reserved
4715 // Bit 28:16 blkbar_vstart
4716 // Bit 15:13 Reserved
4717 // Bit 12:0 blkbar_vend
4718 #define VDIN_BLKBAR_V_START_END (0x1262)
4719 #define P_VDIN_BLKBAR_V_START_END (volatile uint32_t *)((0x1262 << 2) + 0xff900000)
4720 // Bit 31:20 Reserved
4721 // Bit 19:0 blkbar_cnt_threshold. threshold to judge whether a block is totally black
4722 #define VDIN_BLKBAR_CNT_THRESHOLD (0x1263)
4723 #define P_VDIN_BLKBAR_CNT_THRESHOLD (volatile uint32_t *)((0x1263 << 2) + 0xff900000)
4724 // Bit 31:29 Reserved
4725 // Bit 28:16 blkbar_row_th1. //threshold of the top blackbar
4726 // Bit 15:13 Reserved
4727 // bit 12:0 blkbar_row_th2 //threshold of the bottom blackbar
4728 #define VDIN_BLKBAR_ROW_TH1_TH2 (0x1264)
4729 #define P_VDIN_BLKBAR_ROW_TH1_TH2 (volatile uint32_t *)((0x1264 << 2) + 0xff900000)
4730 //Readonly
4731 // Bit 31:29 Reserved
4732 // Bit 28:16 blkbar_ind_left_start. horizontal start of the left region in the current searching
4733 // Bit 15:13 Reserved
4734 // Bit 12:0 blkbar_ind_left_end. horizontal end of the left region in the current searching
4735 #define VDIN_BLKBAR_IND_LEFT_START_END (0x1265)
4736 #define P_VDIN_BLKBAR_IND_LEFT_START_END (volatile uint32_t *)((0x1265 << 2) + 0xff900000)
4737 //Readonly
4738 // Bit 31:29 Reserved
4739 // Bit 28:16 blkbar_ind_right_start.horizontal start of the right region in the current searching
4740 // Bit 15:13 Reserved
4741 // Bit 12:0 blkbar_ind_right_end. horizontal end of the right region in the current searching
4742 #define VDIN_BLKBAR_IND_RIGHT_START_END (0x1266)
4743 #define P_VDIN_BLKBAR_IND_RIGHT_START_END (volatile uint32_t *)((0x1266 << 2) + 0xff900000)
4744 //Readonly
4745 // Bit 31:20 Reserved
4746 // Bit 19:0 blkbar_ind_left1_cnt. Black pixel counter. left part of the left region
4747 #define VDIN_BLKBAR_IND_LEFT1_CNT (0x1267)
4748 #define P_VDIN_BLKBAR_IND_LEFT1_CNT (volatile uint32_t *)((0x1267 << 2) + 0xff900000)
4749 //Readonly
4750 // Bit 31:20 Reserved
4751 // Bit 19:0 blkbar_ind_left2_cnt. Black pixel counter. right part of the left region
4752 #define VDIN_BLKBAR_IND_LEFT2_CNT (0x1268)
4753 #define P_VDIN_BLKBAR_IND_LEFT2_CNT (volatile uint32_t *)((0x1268 << 2) + 0xff900000)
4754 //Readonly
4755 // Bit 31:20 Reserved
4756 // Bit 19:0 blkbar_ind_right1_cnt. Black pixel counter. left part of the right region
4757 #define VDIN_BLKBAR_IND_RIGHT1_CNT (0x1269)
4758 #define P_VDIN_BLKBAR_IND_RIGHT1_CNT (volatile uint32_t *)((0x1269 << 2) + 0xff900000)
4759 //Readonly
4760 // Bit 31:20 Reserved
4761 // Bit 19:0 blkbar_ind_right2_cnt. Black pixel counter. right part of the right region
4762 #define VDIN_BLKBAR_IND_RIGHT2_CNT (0x126a)
4763 #define P_VDIN_BLKBAR_IND_RIGHT2_CNT (volatile uint32_t *)((0x126a << 2) + 0xff900000)
4764 //Readonly
4765 // Bit 31:30 Resersed
4766 // Bit 29 blkbar_ind_black_det_done. LEFT/RIGHT Black detection done
4767 // Bit 28:16 blkbar_top_pos. Top black bar position
4768 // Bit 15:13 Reserved.
4769 // Bit 12:0 blkbar_bot_pos. Bottom black bar position
4770 #define VDIN_BLKBAR_STATUS0 (0x126b)
4771 #define P_VDIN_BLKBAR_STATUS0 (volatile uint32_t *)((0x126b << 2) + 0xff900000)
4772 //Readonly
4773 // Bit 31:29 Reserved
4774 // Bit 28:16 blkbar_left_pos. Left black bar posiont
4775 // Bit 15:13 Reserved
4776 // Bit 12:0 blkbar_right_pos. Right black bar position
4777 #define VDIN_BLKBAR_STATUS1 (0x126c)
4778 #define P_VDIN_BLKBAR_STATUS1 (volatile uint32_t *)((0x126c << 2) + 0xff900000)
4779 //Bit 28:16 input window H start
4780 //Bit 12:0 input window H end
4781 #define VDIN_WIN_H_START_END (0x126d)
4782 #define P_VDIN_WIN_H_START_END (volatile uint32_t *)((0x126d << 2) + 0xff900000)
4783 //Bit 28:16 input window H start
4784 //Bit 12:0 input window V start
4785 #define VDIN_WIN_V_START_END (0x126e)
4786 #define P_VDIN_WIN_V_START_END (volatile uint32_t *)((0x126e << 2) + 0xff900000)
4787 //Bit 23:16 vdi8 asfifo_ctrl
4788 //Bit 15:8 vdi7 asfifo_ctrl
4789 //Bit 7:0 vdi6 asfifo_ctrl
4790 #define VDIN_ASFIFO_CTRL3 (0x126f)
4791 #define P_VDIN_ASFIFO_CTRL3 (volatile uint32_t *)((0x126f << 2) + 0xff900000)
4792 //Bit 3:2 vshrk_clk2_ctrl
4793 //Bit 1:0 vshrk_clk1_ctrl
4794 #define VDIN_COM_GCLK_CTRL2 (0x1270)
4795 #define P_VDIN_COM_GCLK_CTRL2 (volatile uint32_t *)((0x1270 << 2) + 0xff900000)
4796 //Bit 27 vshrk_en
4797 //Bit 26:25 vshrk_mode
4798 //Bit 24 vshrk_lpf_mode
4799 //Bit 23:0 vshrk_dummy
4800 #define VDIN_VSHRK_CTRL (0x1271)
4801 #define P_VDIN_VSHRK_CTRL (volatile uint32_t *)((0x1271 << 2) + 0xff900000)
4802 #define VDIN_DNLP_HIST32 (0x1272)
4803 #define P_VDIN_DNLP_HIST32 (volatile uint32_t *)((0x1272 << 2) + 0xff900000)
4804 //Read only
4805 //Bit 7, vdi9 fifo overflow
4806 //Bit 5:0, vdi9_asfifo_cnt
4807 #define VDIN_COM_STATUS3 (0x1273)
4808 #define P_VDIN_COM_STATUS3 (volatile uint32_t *)((0x1273 << 2) + 0xff900000)
4809 #define VDIN_SYNC_MASK (0x1274)
4810 #define P_VDIN_SYNC_MASK (volatile uint32_t *)((0x1274 << 2) + 0xff900000)
4811 //Bit 7:0, hsync_mask_num
4812 //Bit 15:8, vsync_mask_num
4813 //Bit 16, hsync_mask_enable
4814 //Bit 17, vsync_mask_num
4815 //dolby vdin
4816 #define VDIN_DOLBY_DSC_CTRL0 (0x1275)
4817 #define P_VDIN_DOLBY_DSC_CTRL0 (volatile uint32_t *)((0x1275 << 2) + 0xff900000)
4818 #define VDIN_DOLBY_DSC_CTRL1 (0x1276)
4819 #define P_VDIN_DOLBY_DSC_CTRL1 (volatile uint32_t *)((0x1276 << 2) + 0xff900000)
4820 #define VDIN_DOLBY_DSC_CTRL2 (0x1277)
4821 #define P_VDIN_DOLBY_DSC_CTRL2 (volatile uint32_t *)((0x1277 << 2) + 0xff900000)
4822 #define VDIN_DOLBY_DSC_CTRL3 (0x1278)
4823 #define P_VDIN_DOLBY_DSC_CTRL3 (volatile uint32_t *)((0x1278 << 2) + 0xff900000)
4824 #define VDIN_DOLBY_AXI_CTRL0 (0x1279)
4825 #define P_VDIN_DOLBY_AXI_CTRL0 (volatile uint32_t *)((0x1279 << 2) + 0xff900000)
4826 #define VDIN_DOLBY_AXI_CTRL1 (0x127a)
4827 #define P_VDIN_DOLBY_AXI_CTRL1 (volatile uint32_t *)((0x127a << 2) + 0xff900000)
4828 #define VDIN_DOLBY_AXI_CTRL2 (0x127b)
4829 #define P_VDIN_DOLBY_AXI_CTRL2 (volatile uint32_t *)((0x127b << 2) + 0xff900000)
4830 #define VDIN_DOLBY_AXI_CTRL3 (0x127c)
4831 #define P_VDIN_DOLBY_AXI_CTRL3 (volatile uint32_t *)((0x127c << 2) + 0xff900000)
4832 #define VDIN_DOLBY_DSC_STATUS0 (0x127d)
4833 #define P_VDIN_DOLBY_DSC_STATUS0 (volatile uint32_t *)((0x127d << 2) + 0xff900000)
4834 #define VDIN_DOLBY_DSC_STATUS1 (0x127e)
4835 #define P_VDIN_DOLBY_DSC_STATUS1 (volatile uint32_t *)((0x127e << 2) + 0xff900000)
4836 #define VDIN_DOLBY_DSC_STATUS2 (0x127f)
4837 #define P_VDIN_DOLBY_DSC_STATUS2 (volatile uint32_t *)((0x127f << 2) + 0xff900000)
4838 #define VDIN_DOLBY_DSC_STATUS3 (0x121d)
4839 #define P_VDIN_DOLBY_DSC_STATUS3 (volatile uint32_t *)((0x121d << 2) + 0xff900000)
4840
4841 //8'h72 occupied by histogram 32
4842 //VDIN0 8'h00 - 8'h7f
4843 #define P_VDIN0_SCALE_COEF_IDX ((VDIN0_OFFSET << 2) + P_VDIN_SCALE_COEF_IDX )
4844 #define P_VDIN0_SCALE_COEF ((VDIN0_OFFSET << 2) + P_VDIN_SCALE_COEF )
4845 #define P_VDIN0_COM_CTRL0 ((VDIN0_OFFSET << 2) + P_VDIN_COM_CTRL0 )
4846 #define P_VDIN0_ACTIVE_MAX_PIX_CNT_STATUS ((VDIN0_OFFSET << 2) + P_VDIN_ACTIVE_MAX_PIX_CNT_STATUS )
4847 #define P_VDIN0_LCNT_STATUS ((VDIN0_OFFSET << 2) + P_VDIN_LCNT_STATUS )
4848 #define P_VDIN0_COM_STATUS0 ((VDIN0_OFFSET << 2) + P_VDIN_COM_STATUS0 )
4849 #define P_VDIN0_COM_STATUS1 ((VDIN0_OFFSET << 2) + P_VDIN_COM_STATUS1 )
4850 #define P_VDIN0_LCNT_SHADOW_STATUS ((VDIN0_OFFSET << 2) + P_VDIN_LCNT_SHADOW_STATUS )
4851 #define P_VDIN0_ASFIFO_CTRL0 ((VDIN0_OFFSET << 2) + P_VDIN_ASFIFO_CTRL0 )
4852 #define P_VDIN0_ASFIFO_CTRL1 ((VDIN0_OFFSET << 2) + P_VDIN_ASFIFO_CTRL1 )
4853 #define P_VDIN0_WIDTHM1I_WIDTHM1O ((VDIN0_OFFSET << 2) + P_VDIN_WIDTHM1I_WIDTHM1O )
4854 #define P_VDIN0_SC_MISC_CTRL ((VDIN0_OFFSET << 2) + P_VDIN_SC_MISC_CTRL )
4855 #define P_VDIN0_HSC_PHASE_STEP ((VDIN0_OFFSET << 2) + P_VDIN_HSC_PHASE_STEP )
4856 #define P_VDIN0_HSC_INI_CTRL ((VDIN0_OFFSET << 2) + P_VDIN_HSC_INI_CTRL )
4857 #define P_VDIN0_COM_STATUS2 ((VDIN0_OFFSET << 2) + P_VDIN_COM_STATUS2 )
4858 #define P_VDIN0_COM_STATUS3 ((VDIN0_OFFSET << 2) + P_VDIN_COM_STATUS3 )
4859 #define P_VDIN0_ASFIFO_CTRL2 ((VDIN0_OFFSET << 2) + P_VDIN_ASFIFO_CTRL2 )
4860 #define P_VDIN0_MATRIX_CTRL ((VDIN0_OFFSET << 2) + P_VDIN_MATRIX_CTRL )
4861 #define P_VDIN0_MATRIX_COEF00_01 ((VDIN0_OFFSET << 2) + P_VDIN_MATRIX_COEF00_01 )
4862 #define P_VDIN0_MATRIX_COEF02_10 ((VDIN0_OFFSET << 2) + P_VDIN_MATRIX_COEF02_10 )
4863 #define P_VDIN0_MATRIX_COEF11_12 ((VDIN0_OFFSET << 2) + P_VDIN_MATRIX_COEF11_12 )
4864 #define P_VDIN0_MATRIX_COEF20_21 ((VDIN0_OFFSET << 2) + P_VDIN_MATRIX_COEF20_21 )
4865 #define P_VDIN0_MATRIX_COEF22 ((VDIN0_OFFSET << 2) + P_VDIN_MATRIX_COEF22 )
4866 #define P_VDIN0_MATRIX_OFFSET0_1 ((VDIN0_OFFSET << 2) + P_VDIN_MATRIX_OFFSET0_1 )
4867 #define P_VDIN0_MATRIX_OFFSET2 ((VDIN0_OFFSET << 2) + P_VDIN_MATRIX_OFFSET2 )
4868 #define P_VDIN0_MATRIX_PRE_OFFSET0_1 ((VDIN0_OFFSET << 2) + P_VDIN_MATRIX_PRE_OFFSET0_1 )
4869 #define P_VDIN0_MATRIX_PRE_OFFSET2 ((VDIN0_OFFSET << 2) + P_VDIN_MATRIX_PRE_OFFSET2 )
4870 #define P_VDIN0_LFIFO_CTRL ((VDIN0_OFFSET << 2) + P_VDIN_LFIFO_CTRL )
4871 #define P_VDIN0_COM_GCLK_CTRL ((VDIN0_OFFSET << 2) + P_VDIN_COM_GCLK_CTRL )
4872 #define P_VDIN0_INTF_WIDTHM1 ((VDIN0_OFFSET << 2) + P_VDIN_INTF_WIDTHM1 )
4873 #define P_VDIN0_WR_CTRL2 ((VDIN0_OFFSET << 2) + P_VDIN_WR_CTRL2 )
4874 #define P_VDIN0_WR_CTRL ((VDIN0_OFFSET << 2) + P_VDIN_WR_CTRL )
4875 #define P_VDIN0_WR_H_START_END ((VDIN0_OFFSET << 2) + P_VDIN_WR_H_START_END )
4876 #define P_VDIN0_WR_V_START_END ((VDIN0_OFFSET << 2) + P_VDIN_WR_V_START_END )
4877 #define P_VDIN0_VSC_PHASE_STEP ((VDIN0_OFFSET << 2) + P_VDIN_VSC_PHASE_STEP )
4878 #define P_VDIN0_VSC_INI_CTRL ((VDIN0_OFFSET << 2) + P_VDIN_VSC_INI_CTRL )
4879 #define P_VDIN0_SCIN_HEIGHTM1 ((VDIN0_OFFSET << 2) + P_VDIN_SCIN_HEIGHTM1 )
4880 #define P_VDIN0_DUMMY_DATA ((VDIN0_OFFSET << 2) + P_VDIN_DUMMY_DATA )
4881 #define P_VDIN0_MATRIX_PROBE_COLOR ((VDIN0_OFFSET << 2) + P_VDIN_MATRIX_PROBE_COLOR )
4882 #define P_VDIN0_MATRIX_HL_COLOR ((VDIN0_OFFSET << 2) + P_VDIN_MATRIX_HL_COLOR )
4883 #define P_VDIN0_MATRIX_PROBE_POS ((VDIN0_OFFSET << 2) + P_VDIN_MATRIX_PROBE_POS )
4884 #define P_VDIN0_CHROMA_ADDR_PORT ((VDIN0_OFFSET << 2) + P_VDIN_CHROMA_ADDR_PORT )
4885 #define P_VDIN0_CHROMA_DATA_PORT ((VDIN0_OFFSET << 2) + P_VDIN_CHROMA_DATA_PORT )
4886 #define P_VDIN0_CM_BRI_CON_CTRL ((VDIN0_OFFSET << 2) + P_VDIN_CM_BRI_CON_CTRL )
4887 #define P_VDIN0_HIST_CTRL ((VDIN0_OFFSET << 2) + P_VDIN_HIST_CTRL )
4888 #define P_VDIN0_HIST_H_START_END ((VDIN0_OFFSET << 2) + P_VDIN_HIST_H_START_END )
4889 #define P_VDIN0_HIST_V_START_END ((VDIN0_OFFSET << 2) + P_VDIN_HIST_V_START_END )
4890 #define P_VDIN0_HIST_MAX_MIN ((VDIN0_OFFSET << 2) + P_VDIN_HIST_MAX_MIN )
4891 #define P_VDIN0_HIST_SPL_VAL ((VDIN0_OFFSET << 2) + P_VDIN_HIST_SPL_VAL )
4892 #define P_VDIN0_HIST_SPL_PIX_CNT ((VDIN0_OFFSET << 2) + P_VDIN_HIST_SPL_PIX_CNT )
4893 #define P_VDIN0_HIST_CHROMA_SUM ((VDIN0_OFFSET << 2) + P_VDIN_HIST_CHROMA_SUM )
4894 #define P_VDIN0_DNLP_HIST00 ((VDIN0_OFFSET << 2) + P_VDIN_DNLP_HIST00 )
4895 #define P_VDIN0_DNLP_HIST01 ((VDIN0_OFFSET << 2) + P_VDIN_DNLP_HIST01 )
4896 #define P_VDIN0_DNLP_HIST02 ((VDIN0_OFFSET << 2) + P_VDIN_DNLP_HIST02 )
4897 #define P_VDIN0_DNLP_HIST03 ((VDIN0_OFFSET << 2) + P_VDIN_DNLP_HIST03 )
4898 #define P_VDIN0_DNLP_HIST04 ((VDIN0_OFFSET << 2) + P_VDIN_DNLP_HIST04 )
4899 #define P_VDIN0_DNLP_HIST05 ((VDIN0_OFFSET << 2) + P_VDIN_DNLP_HIST05 )
4900 #define P_VDIN0_DNLP_HIST06 ((VDIN0_OFFSET << 2) + P_VDIN_DNLP_HIST06 )
4901 #define P_VDIN0_DNLP_HIST07 ((VDIN0_OFFSET << 2) + P_VDIN_DNLP_HIST07 )
4902 #define P_VDIN0_DNLP_HIST08 ((VDIN0_OFFSET << 2) + P_VDIN_DNLP_HIST08 )
4903 #define P_VDIN0_DNLP_HIST09 ((VDIN0_OFFSET << 2) + P_VDIN_DNLP_HIST09 )
4904 #define P_VDIN0_DNLP_HIST10 ((VDIN0_OFFSET << 2) + P_VDIN_DNLP_HIST10 )
4905 #define P_VDIN0_DNLP_HIST11 ((VDIN0_OFFSET << 2) + P_VDIN_DNLP_HIST11 )
4906 #define P_VDIN0_DNLP_HIST12 ((VDIN0_OFFSET << 2) + P_VDIN_DNLP_HIST12 )
4907 #define P_VDIN0_DNLP_HIST13 ((VDIN0_OFFSET << 2) + P_VDIN_DNLP_HIST13 )
4908 #define P_VDIN0_DNLP_HIST14 ((VDIN0_OFFSET << 2) + P_VDIN_DNLP_HIST14 )
4909 #define P_VDIN0_DNLP_HIST15 ((VDIN0_OFFSET << 2) + P_VDIN_DNLP_HIST15 )
4910 #define P_VDIN0_DNLP_HIST16 ((VDIN0_OFFSET << 2) + P_VDIN_DNLP_HIST16 )
4911 #define P_VDIN0_DNLP_HIST17 ((VDIN0_OFFSET << 2) + P_VDIN_DNLP_HIST17 )
4912 #define P_VDIN0_DNLP_HIST18 ((VDIN0_OFFSET << 2) + P_VDIN_DNLP_HIST18 )
4913 #define P_VDIN0_DNLP_HIST19 ((VDIN0_OFFSET << 2) + P_VDIN_DNLP_HIST19 )
4914 #define P_VDIN0_DNLP_HIST20 ((VDIN0_OFFSET << 2) + P_VDIN_DNLP_HIST20 )
4915 #define P_VDIN0_DNLP_HIST21 ((VDIN0_OFFSET << 2) + P_VDIN_DNLP_HIST21 )
4916 #define P_VDIN0_DNLP_HIST22 ((VDIN0_OFFSET << 2) + P_VDIN_DNLP_HIST22 )
4917 #define P_VDIN0_DNLP_HIST23 ((VDIN0_OFFSET << 2) + P_VDIN_DNLP_HIST23 )
4918 #define P_VDIN0_DNLP_HIST24 ((VDIN0_OFFSET << 2) + P_VDIN_DNLP_HIST24 )
4919 #define P_VDIN0_DNLP_HIST25 ((VDIN0_OFFSET << 2) + P_VDIN_DNLP_HIST25 )
4920 #define P_VDIN0_DNLP_HIST26 ((VDIN0_OFFSET << 2) + P_VDIN_DNLP_HIST26 )
4921 #define P_VDIN0_DNLP_HIST27 ((VDIN0_OFFSET << 2) + P_VDIN_DNLP_HIST27 )
4922 #define P_VDIN0_DNLP_HIST28 ((VDIN0_OFFSET << 2) + P_VDIN_DNLP_HIST28 )
4923 #define P_VDIN0_DNLP_HIST29 ((VDIN0_OFFSET << 2) + P_VDIN_DNLP_HIST29 )
4924 #define P_VDIN0_DNLP_HIST30 ((VDIN0_OFFSET << 2) + P_VDIN_DNLP_HIST30 )
4925 #define P_VDIN0_DNLP_HIST31 ((VDIN0_OFFSET << 2) + P_VDIN_DNLP_HIST31 )
4926 #define P_VDIN0_DNLP_HIST32 ((VDIN0_OFFSET << 2) + P_VDIN_DNLP_HIST32 )
4927 #define P_VDIN0_LDIM_STTS_HIST_REGION_IDX ((VDIN0_OFFSET << 2) + P_VDIN_LDIM_STTS_HIST_REGION_IDX )
4928 #define P_VDIN0_LDIM_STTS_HIST_SET_REGION ((VDIN0_OFFSET << 2) + P_VDIN_LDIM_STTS_HIST_SET_REGION )
4929 #define P_VDIN0_LDIM_STTS_HIST_READ_REGION ((VDIN0_OFFSET << 2) + P_VDIN_LDIM_STTS_HIST_READ_REGION )
4930 #define P_VDIN0_MEAS_CTRL0 ((VDIN0_OFFSET << 2) + P_VDIN_MEAS_CTRL0 )
4931 #define P_VDIN0_MEAS_VS_COUNT_HI ((VDIN0_OFFSET << 2) + P_VDIN_MEAS_VS_COUNT_HI )
4932 #define P_VDIN0_MEAS_VS_COUNT_LO ((VDIN0_OFFSET << 2) + P_VDIN_MEAS_VS_COUNT_LO )
4933 #define P_VDIN0_MEAS_HS_RANGE ((VDIN0_OFFSET << 2) + P_VDIN_MEAS_HS_RANGE )
4934 #define P_VDIN0_MEAS_HS_COUNT ((VDIN0_OFFSET << 2) + P_VDIN_MEAS_HS_COUNT )
4935 #define P_VDIN0_BLKBAR_CTRL1 ((VDIN0_OFFSET << 2) + P_VDIN_BLKBAR_CTRL1 )
4936 #define P_VDIN0_BLKBAR_CTRL0 ((VDIN0_OFFSET << 2) + P_VDIN_BLKBAR_CTRL0 )
4937 #define P_VDIN0_BLKBAR_H_START_END ((VDIN0_OFFSET << 2) + P_VDIN_BLKBAR_H_START_END )
4938 #define P_VDIN0_BLKBAR_V_START_END ((VDIN0_OFFSET << 2) + P_VDIN_BLKBAR_V_START_END )
4939 #define P_VDIN0_BLKBAR_CNT_THRESHOLD ((VDIN0_OFFSET << 2) + P_VDIN_BLKBAR_CNT_THRESHOLD )
4940 #define P_VDIN0_BLKBAR_ROW_TH1_TH2 ((VDIN0_OFFSET << 2) + P_VDIN_BLKBAR_ROW_TH1_TH2 )
4941 #define P_VDIN0_BLKBAR_IND_LEFT_START_END ((VDIN0_OFFSET << 2) + P_VDIN_BLKBAR_IND_LEFT_START_END )
4942 #define P_VDIN0_BLKBAR_IND_RIGHT_START_END ((VDIN0_OFFSET << 2) + P_VDIN_BLKBAR_IND_RIGHT_START_END )
4943 #define P_VDIN0_BLKBAR_IND_LEFT1_CNT ((VDIN0_OFFSET << 2) + P_VDIN_BLKBAR_IND_LEFT1_CNT )
4944 #define P_VDIN0_BLKBAR_IND_LEFT2_CNT ((VDIN0_OFFSET << 2) + P_VDIN_BLKBAR_IND_LEFT2_CNT )
4945 #define P_VDIN0_BLKBAR_IND_RIGHT1_CNT ((VDIN0_OFFSET << 2) + P_VDIN_BLKBAR_IND_RIGHT1_CNT )
4946 #define P_VDIN0_BLKBAR_IND_RIGHT2_CNT ((VDIN0_OFFSET << 2) + P_VDIN_BLKBAR_IND_RIGHT2_CNT )
4947 #define P_VDIN0_BLKBAR_STATUS0 ((VDIN0_OFFSET << 2) + P_VDIN_BLKBAR_STATUS0 )
4948 #define P_VDIN0_BLKBAR_STATUS1 ((VDIN0_OFFSET << 2) + P_VDIN_BLKBAR_STATUS1 )
4949 #define P_VDIN0_WIN_H_START_END ((VDIN0_OFFSET << 2) + P_VDIN_WIN_H_START_END )
4950 #define P_VDIN0_WIN_V_START_END ((VDIN0_OFFSET << 2) + P_VDIN_WIN_V_START_END )
4951 #define P_VDIN0_ASFIFO_CTRL3 ((VDIN0_OFFSET << 2) + P_VDIN_ASFIFO_CTRL3 )
4952 #define P_VDIN0_COM_GCLK_CTRL2 ((VDIN0_OFFSET << 2) + P_VDIN_COM_GCLK_CTRL2 )
4953 #define P_VDIN0_VSHRK_CTRL ((VDIN0_OFFSET << 2) + P_VDIN_VSHRK_CTRL )
4954 #define P_VDIN0_SYNC_MASK ((VDIN0_OFFSET << 2) + P_VDIN_SYNC_MASK )
4955 #define P_VDIN0_DOLBY_DSC_CTRL0 ((VDIN0_OFFSET << 2) + P_VDIN_DOLBY_DSC_CTRL0 )
4956 #define P_VDIN0_DOLBY_DSC_CTRL1 ((VDIN0_OFFSET << 2) + P_VDIN_DOLBY_DSC_CTRL1 )
4957 #define P_VDIN0_DOLBY_DSC_CTRL2 ((VDIN0_OFFSET << 2) + P_VDIN_DOLBY_DSC_CTRL2 )
4958 #define P_VDIN0_DOLBY_DSC_CTRL3 ((VDIN0_OFFSET << 2) + P_VDIN_DOLBY_DSC_CTRL3 )
4959 #define P_VDIN0_DOLBY_AXI_CTRL0 ((VDIN0_OFFSET << 2) + P_VDIN_DOLBY_AXI_CTRL0 )
4960 #define P_VDIN0_DOLBY_AXI_CTRL1 ((VDIN0_OFFSET << 2) + P_VDIN_DOLBY_AXI_CTRL1 )
4961 #define P_VDIN0_DOLBY_AXI_CTRL2 ((VDIN0_OFFSET << 2) + P_VDIN_DOLBY_AXI_CTRL2 )
4962 #define P_VDIN0_DOLBY_AXI_CTRL3 ((VDIN0_OFFSET << 2) + P_VDIN_DOLBY_AXI_CTRL3 )
4963 #define P_VDIN0_DOLBY_DSC_STATUS0 ((VDIN0_OFFSET << 2) + P_VDIN_DOLBY_DSC_STATUS0)
4964 #define P_VDIN0_DOLBY_DSC_STATUS1 ((VDIN0_OFFSET << 2) + P_VDIN_DOLBY_DSC_STATUS1)
4965 #define P_VDIN0_DOLBY_DSC_STATUS2 ((VDIN0_OFFSET << 2) + P_VDIN_DOLBY_DSC_STATUS2)
4966 #define P_VDIN0_DOLBY_DSC_STATUS3 ((VDIN0_OFFSET << 2) + P_VDIN_DOLBY_DSC_STATUS3)
4967
4968
4969 //VDIN1 8'h80 - 8'hef
4970 #define P_VDIN1_SCALE_COEF_IDX ((VDIN1_OFFSET << 2) + P_VDIN_SCALE_COEF_IDX )
4971 #define P_VDIN1_SCALE_COEF ((VDIN1_OFFSET << 2) + P_VDIN_SCALE_COEF )
4972 #define P_VDIN1_COM_CTRL0 ((VDIN1_OFFSET << 2) + P_VDIN_COM_CTRL0 )
4973 #define P_VDIN1_ACTIVE_MAX_PIX_CNT_STATUS ((VDIN1_OFFSET << 2) + P_VDIN_ACTIVE_MAX_PIX_CNT_STATUS )
4974 #define P_VDIN1_LCNT_STATUS ((VDIN1_OFFSET << 2) + P_VDIN_LCNT_STATUS )
4975 #define P_VDIN1_COM_STATUS0 ((VDIN1_OFFSET << 2) + P_VDIN_COM_STATUS0 )
4976 #define P_VDIN1_COM_STATUS1 ((VDIN1_OFFSET << 2) + P_VDIN_COM_STATUS1 )
4977 #define P_VDIN1_LCNT_SHADOW_STATUS ((VDIN1_OFFSET << 2) + P_VDIN_LCNT_SHADOW_STATUS )
4978 #define P_VDIN1_ASFIFO_CTRL0 ((VDIN1_OFFSET << 2) + P_VDIN_ASFIFO_CTRL0 )
4979 #define P_VDIN1_ASFIFO_CTRL1 ((VDIN1_OFFSET << 2) + P_VDIN_ASFIFO_CTRL1 )
4980 #define P_VDIN1_WIDTHM1I_WIDTHM1O ((VDIN1_OFFSET << 2) + P_VDIN_WIDTHM1I_WIDTHM1O )
4981 #define P_VDIN1_SC_MISC_CTRL ((VDIN1_OFFSET << 2) + P_VDIN_SC_MISC_CTRL )
4982 #define P_VDIN1_HSC_PHASE_STEP ((VDIN1_OFFSET << 2) + P_VDIN_HSC_PHASE_STEP )
4983 #define P_VDIN1_HSC_INI_CTRL ((VDIN1_OFFSET << 2) + P_VDIN_HSC_INI_CTRL )
4984 #define P_VDIN1_COM_STATUS2 ((VDIN1_OFFSET << 2) + P_VDIN_COM_STATUS2 )
4985 #define P_VDIN1_COM_STATUS3 ((VDIN1_OFFSET << 2) + P_VDIN_COM_STATUS3 )
4986 #define P_VDIN1_ASFIFO_CTRL2 ((VDIN1_OFFSET << 2) + P_VDIN_ASFIFO_CTRL2 )
4987 #define P_VDIN1_MATRIX_CTRL ((VDIN1_OFFSET << 2) + P_VDIN_MATRIX_CTRL )
4988 #define P_VDIN1_MATRIX_COEF00_01 ((VDIN1_OFFSET << 2) + P_VDIN_MATRIX_COEF00_01 )
4989 #define P_VDIN1_MATRIX_COEF02_10 ((VDIN1_OFFSET << 2) + P_VDIN_MATRIX_COEF02_10 )
4990 #define P_VDIN1_MATRIX_COEF11_12 ((VDIN1_OFFSET << 2) + P_VDIN_MATRIX_COEF11_12 )
4991 #define P_VDIN1_MATRIX_COEF20_21 ((VDIN1_OFFSET << 2) + P_VDIN_MATRIX_COEF20_21 )
4992 #define P_VDIN1_MATRIX_COEF22 ((VDIN1_OFFSET << 2) + P_VDIN_MATRIX_COEF22 )
4993 #define P_VDIN1_MATRIX_OFFSET0_1 ((VDIN1_OFFSET << 2) + P_VDIN_MATRIX_OFFSET0_1 )
4994 #define P_VDIN1_MATRIX_OFFSET2 ((VDIN1_OFFSET << 2) + P_VDIN_MATRIX_OFFSET2 )
4995 #define P_VDIN1_MATRIX_PRE_OFFSET0_1 ((VDIN1_OFFSET << 2) + P_VDIN_MATRIX_PRE_OFFSET0_1 )
4996 #define P_VDIN1_MATRIX_PRE_OFFSET2 ((VDIN1_OFFSET << 2) + P_VDIN_MATRIX_PRE_OFFSET2 )
4997 #define P_VDIN1_LFIFO_CTRL ((VDIN1_OFFSET << 2) + P_VDIN_LFIFO_CTRL )
4998 #define P_VDIN1_COM_GCLK_CTRL ((VDIN1_OFFSET << 2) + P_VDIN_COM_GCLK_CTRL )
4999 #define P_VDIN1_INTF_WIDTHM1 ((VDIN1_OFFSET << 2) + P_VDIN_INTF_WIDTHM1 )
5000 #define P_VDIN1_WR_CTRL2 ((VDIN1_OFFSET << 2) + P_VDIN_WR_CTRL2 )
5001 #define P_VDIN1_WR_CTRL ((VDIN1_OFFSET << 2) + P_VDIN_WR_CTRL )
5002 #define P_VDIN1_WR_H_START_END ((VDIN1_OFFSET << 2) + P_VDIN_WR_H_START_END )
5003 #define P_VDIN1_WR_V_START_END ((VDIN1_OFFSET << 2) + P_VDIN_WR_V_START_END )
5004 #define P_VDIN1_VSC_PHASE_STEP ((VDIN1_OFFSET << 2) + P_VDIN_VSC_PHASE_STEP )
5005 #define P_VDIN1_VSC_INI_CTRL ((VDIN1_OFFSET << 2) + P_VDIN_VSC_INI_CTRL )
5006 #define P_VDIN1_SCIN_HEIGHTM1 ((VDIN1_OFFSET << 2) + P_VDIN_SCIN_HEIGHTM1 )
5007 #define P_VDIN1_DUMMY_DATA ((VDIN1_OFFSET << 2) + P_VDIN_DUMMY_DATA )
5008 #define P_VDIN1_MATRIX_PROBE_COLOR ((VDIN1_OFFSET << 2) + P_VDIN_MATRIX_PROBE_COLOR )
5009 #define P_VDIN1_MATRIX_HL_COLOR ((VDIN1_OFFSET << 2) + P_VDIN_MATRIX_HL_COLOR )
5010 #define P_VDIN1_MATRIX_PROBE_POS ((VDIN1_OFFSET << 2) + P_VDIN_MATRIX_PROBE_POS )
5011 #define P_VDIN1_CHROMA_ADDR_PORT ((VDIN1_OFFSET << 2) + P_VDIN_CHROMA_ADDR_PORT )
5012 #define P_VDIN1_CHROMA_DATA_PORT ((VDIN1_OFFSET << 2) + P_VDIN_CHROMA_DATA_PORT )
5013 #define P_VDIN1_CM_BRI_CON_CTRL ((VDIN1_OFFSET << 2) + P_VDIN_CM_BRI_CON_CTRL )
5014 #define P_VDIN1_HIST_CTRL ((VDIN1_OFFSET << 2) + P_VDIN_HIST_CTRL )
5015 #define P_VDIN1_HIST_H_START_END ((VDIN1_OFFSET << 2) + P_VDIN_HIST_H_START_END )
5016 #define P_VDIN1_HIST_V_START_END ((VDIN1_OFFSET << 2) + P_VDIN_HIST_V_START_END )
5017 #define P_VDIN1_HIST_MAX_MIN ((VDIN1_OFFSET << 2) + P_VDIN_HIST_MAX_MIN )
5018 #define P_VDIN1_HIST_SPL_VAL ((VDIN1_OFFSET << 2) + P_VDIN_HIST_SPL_VAL )
5019 #define P_VDIN1_HIST_SPL_PIX_CNT ((VDIN1_OFFSET << 2) + P_VDIN_HIST_SPL_PIX_CNT )
5020 #define P_VDIN1_HIST_CHROMA_SUM ((VDIN1_OFFSET << 2) + P_VDIN_HIST_CHROMA_SUM )
5021 #define P_VDIN1_DNLP_HIST00 ((VDIN1_OFFSET << 2) + P_VDIN_DNLP_HIST00 )
5022 #define P_VDIN1_DNLP_HIST01 ((VDIN1_OFFSET << 2) + P_VDIN_DNLP_HIST01 )
5023 #define P_VDIN1_DNLP_HIST02 ((VDIN1_OFFSET << 2) + P_VDIN_DNLP_HIST02 )
5024 #define P_VDIN1_DNLP_HIST03 ((VDIN1_OFFSET << 2) + P_VDIN_DNLP_HIST03 )
5025 #define P_VDIN1_DNLP_HIST04 ((VDIN1_OFFSET << 2) + P_VDIN_DNLP_HIST04 )
5026 #define P_VDIN1_DNLP_HIST05 ((VDIN1_OFFSET << 2) + P_VDIN_DNLP_HIST05 )
5027 #define P_VDIN1_DNLP_HIST06 ((VDIN1_OFFSET << 2) + P_VDIN_DNLP_HIST06 )
5028 #define P_VDIN1_DNLP_HIST07 ((VDIN1_OFFSET << 2) + P_VDIN_DNLP_HIST07 )
5029 #define P_VDIN1_DNLP_HIST08 ((VDIN1_OFFSET << 2) + P_VDIN_DNLP_HIST08 )
5030 #define P_VDIN1_DNLP_HIST09 ((VDIN1_OFFSET << 2) + P_VDIN_DNLP_HIST09 )
5031 #define P_VDIN1_DNLP_HIST10 ((VDIN1_OFFSET << 2) + P_VDIN_DNLP_HIST10 )
5032 #define P_VDIN1_DNLP_HIST11 ((VDIN1_OFFSET << 2) + P_VDIN_DNLP_HIST11 )
5033 #define P_VDIN1_DNLP_HIST12 ((VDIN1_OFFSET << 2) + P_VDIN_DNLP_HIST12 )
5034 #define P_VDIN1_DNLP_HIST13 ((VDIN1_OFFSET << 2) + P_VDIN_DNLP_HIST13 )
5035 #define P_VDIN1_DNLP_HIST14 ((VDIN1_OFFSET << 2) + P_VDIN_DNLP_HIST14 )
5036 #define P_VDIN1_DNLP_HIST15 ((VDIN1_OFFSET << 2) + P_VDIN_DNLP_HIST15 )
5037 #define P_VDIN1_DNLP_HIST16 ((VDIN1_OFFSET << 2) + P_VDIN_DNLP_HIST16 )
5038 #define P_VDIN1_DNLP_HIST17 ((VDIN1_OFFSET << 2) + P_VDIN_DNLP_HIST17 )
5039 #define P_VDIN1_DNLP_HIST18 ((VDIN1_OFFSET << 2) + P_VDIN_DNLP_HIST18 )
5040 #define P_VDIN1_DNLP_HIST19 ((VDIN1_OFFSET << 2) + P_VDIN_DNLP_HIST19 )
5041 #define P_VDIN1_DNLP_HIST20 ((VDIN1_OFFSET << 2) + P_VDIN_DNLP_HIST20 )
5042 #define P_VDIN1_DNLP_HIST21 ((VDIN1_OFFSET << 2) + P_VDIN_DNLP_HIST21 )
5043 #define P_VDIN1_DNLP_HIST22 ((VDIN1_OFFSET << 2) + P_VDIN_DNLP_HIST22 )
5044 #define P_VDIN1_DNLP_HIST23 ((VDIN1_OFFSET << 2) + P_VDIN_DNLP_HIST23 )
5045 #define P_VDIN1_DNLP_HIST24 ((VDIN1_OFFSET << 2) + P_VDIN_DNLP_HIST24 )
5046 #define P_VDIN1_DNLP_HIST25 ((VDIN1_OFFSET << 2) + P_VDIN_DNLP_HIST25 )
5047 #define P_VDIN1_DNLP_HIST26 ((VDIN1_OFFSET << 2) + P_VDIN_DNLP_HIST26 )
5048 #define P_VDIN1_DNLP_HIST27 ((VDIN1_OFFSET << 2) + P_VDIN_DNLP_HIST27 )
5049 #define P_VDIN1_DNLP_HIST28 ((VDIN1_OFFSET << 2) + P_VDIN_DNLP_HIST28 )
5050 #define P_VDIN1_DNLP_HIST29 ((VDIN1_OFFSET << 2) + P_VDIN_DNLP_HIST29 )
5051 #define P_VDIN1_DNLP_HIST30 ((VDIN1_OFFSET << 2) + P_VDIN_DNLP_HIST30 )
5052 #define P_VDIN1_DNLP_HIST31 ((VDIN1_OFFSET << 2) + P_VDIN_DNLP_HIST31 )
5053 #define P_VDIN1_DNLP_HIST32 ((VDIN1_OFFSET << 2) + P_VDIN_DNLP_HIST32 )
5054 #define P_VDIN1_LDIM_STTS_HIST_REGION_IDX ((VDIN1_OFFSET << 2) + P_VDIN_LDIM_STTS_HIST_REGION_IDX )
5055 #define P_VDIN1_LDIM_STTS_HIST_SET_REGION ((VDIN1_OFFSET << 2) + P_VDIN_LDIM_STTS_HIST_SET_REGION )
5056 #define P_VDIN1_LDIM_STTS_HIST_READ_REGION ((VDIN1_OFFSET << 2) + P_VDIN_LDIM_STTS_HIST_READ_REGION )
5057 #define P_VDIN1_MEAS_CTRL0 ((VDIN1_OFFSET << 2) + P_VDIN_MEAS_CTRL0 )
5058 #define P_VDIN1_MEAS_VS_COUNT_HI ((VDIN1_OFFSET << 2) + P_VDIN_MEAS_VS_COUNT_HI )
5059 #define P_VDIN1_MEAS_VS_COUNT_LO ((VDIN1_OFFSET << 2) + P_VDIN_MEAS_VS_COUNT_LO )
5060 #define P_VDIN1_MEAS_HS_RANGE ((VDIN1_OFFSET << 2) + P_VDIN_MEAS_HS_RANGE )
5061 #define P_VDIN1_MEAS_HS_COUNT ((VDIN1_OFFSET << 2) + P_VDIN_MEAS_HS_COUNT )
5062 #define P_VDIN1_BLKBAR_CTRL1 ((VDIN1_OFFSET << 2) + P_VDIN_BLKBAR_CTRL1 )
5063 #define P_VDIN1_BLKBAR_CTRL0 ((VDIN1_OFFSET << 2) + P_VDIN_BLKBAR_CTRL0 )
5064 #define P_VDIN1_BLKBAR_H_START_END ((VDIN1_OFFSET << 2) + P_VDIN_BLKBAR_H_START_END )
5065 #define P_VDIN1_BLKBAR_V_START_END ((VDIN1_OFFSET << 2) + P_VDIN_BLKBAR_V_START_END )
5066 #define P_VDIN1_BLKBAR_CNT_THRESHOLD ((VDIN1_OFFSET << 2) + P_VDIN_BLKBAR_CNT_THRESHOLD )
5067 #define P_VDIN1_BLKBAR_ROW_TH1_TH2 ((VDIN1_OFFSET << 2) + P_VDIN_BLKBAR_ROW_TH1_TH2 )
5068 #define P_VDIN1_BLKBAR_IND_LEFT_START_END ((VDIN1_OFFSET << 2) + P_VDIN_BLKBAR_IND_LEFT_START_END )
5069 #define P_VDIN1_BLKBAR_IND_RIGHT_START_END ((VDIN1_OFFSET << 2) + P_VDIN_BLKBAR_IND_RIGHT_START_END )
5070 #define P_VDIN1_BLKBAR_IND_LEFT1_CNT ((VDIN1_OFFSET << 2) + P_VDIN_BLKBAR_IND_LEFT1_CNT )
5071 #define P_VDIN1_BLKBAR_IND_LEFT2_CNT ((VDIN1_OFFSET << 2) + P_VDIN_BLKBAR_IND_LEFT2_CNT )
5072 #define P_VDIN1_BLKBAR_IND_RIGHT1_CNT ((VDIN1_OFFSET << 2) + P_VDIN_BLKBAR_IND_RIGHT1_CNT )
5073 #define P_VDIN1_BLKBAR_IND_RIGHT2_CNT ((VDIN1_OFFSET << 2) + P_VDIN_BLKBAR_IND_RIGHT2_CNT )
5074 #define P_VDIN1_BLKBAR_STATUS0 ((VDIN1_OFFSET << 2) + P_VDIN_BLKBAR_STATUS0 )
5075 #define P_VDIN1_BLKBAR_STATUS1 ((VDIN1_OFFSET << 2) + P_VDIN_BLKBAR_STATUS1 )
5076 #define P_VDIN1_WIN_H_START_END ((VDIN1_OFFSET << 2) + P_VDIN_WIN_H_START_END )
5077 #define P_VDIN1_WIN_V_START_END ((VDIN1_OFFSET << 2) + P_VDIN_WIN_V_START_END )
5078 #define P_VDIN1_ASFIFO_CTRL3 ((VDIN1_OFFSET << 2) + P_VDIN_ASFIFO_CTRL3 )
5079 #define P_VDIN1_COM_GCLK_CTRL2 ((VDIN1_OFFSET << 2) + P_VDIN_COM_GCLK_CTRL2 )
5080 #define P_VDIN1_VSHRK_CTRL ((VDIN1_OFFSET << 2) + P_VDIN_VSHRK_CTRL )
5081 #define P_VDIN1_SYNC_MASK ((VDIN1_OFFSET << 2) + P_VDIN_SYNC_MASK )
5082 #define P_VDIN1_DOLBY_DSC_CTRL0 ((VDIN1_OFFSET << 2) + P_VDIN_DOLBY_DSC_CTRL0 )
5083 #define P_VDIN1_DOLBY_DSC_CTRL1 ((VDIN1_OFFSET << 2) + P_VDIN_DOLBY_DSC_CTRL1 )
5084 #define P_VDIN1_DOLBY_DSC_CTRL2 ((VDIN1_OFFSET << 2) + P_VDIN_DOLBY_DSC_CTRL2 )
5085 #define P_VDIN1_DOLBY_DSC_CTRL3 ((VDIN1_OFFSET << 2) + P_VDIN_DOLBY_DSC_CTRL3 )
5086 #define P_VDIN1_DOLBY_AXI_CTRL0 ((VDIN1_OFFSET << 2) + P_VDIN_DOLBY_AXI_CTRL0 )
5087 #define P_VDIN1_DOLBY_AXI_CTRL1 ((VDIN1_OFFSET << 2) + P_VDIN_DOLBY_AXI_CTRL1 )
5088 #define P_VDIN1_DOLBY_AXI_CTRL2 ((VDIN1_OFFSET << 2) + P_VDIN_DOLBY_AXI_CTRL2 )
5089 #define P_VDIN1_DOLBY_AXI_CTRL3 ((VDIN1_OFFSET << 2) + P_VDIN_DOLBY_AXI_CTRL3 )
5090 #define P_VDIN1_DOLBY_DSC_STATUS0 ((VDIN1_OFFSET << 2) + P_VDIN_DOLBY_DSC_STATUS0)
5091 #define P_VDIN1_DOLBY_DSC_STATUS1 ((VDIN1_OFFSET << 2) + P_VDIN_DOLBY_DSC_STATUS1)
5092 #define P_VDIN1_DOLBY_DSC_STATUS2 ((VDIN1_OFFSET << 2) + P_VDIN_DOLBY_DSC_STATUS2)
5093 #define P_VDIN1_DOLBY_DSC_STATUS3 ((VDIN1_OFFSET << 2) + P_VDIN_DOLBY_DSC_STATUS3)
5094
5095 //`define LCD_VCBUS_BASE 8'h14
5096 //
5097 // Reading file: lcd_regs.h
5098 //
5099 // -----------------------------------------------
5100 // CBUS_BASE: LCD_VCBUS_BASE = 0x14
5101 // -----------------------------------------------
5102 //========================================================================
5103 //LCD DRV 12'h480~12'h4ef
5104 //=======================================================================
5105 #define L_GAMMA_CNTL_PORT (0x1400)
5106 #define P_L_GAMMA_CNTL_PORT (volatile uint32_t *)((0x1400 << 2) + 0xff900000)
5107 #define L_GAMMA_DATA_PORT (0x1401)
5108 #define P_L_GAMMA_DATA_PORT (volatile uint32_t *)((0x1401 << 2) + 0xff900000)
5109 #define L_GAMMA_ADDR_PORT (0x1402)
5110 #define P_L_GAMMA_ADDR_PORT (volatile uint32_t *)((0x1402 << 2) + 0xff900000)
5111 #define L_GAMMA_VCOM_HSWITCH_ADDR (0x1403)
5112 #define P_L_GAMMA_VCOM_HSWITCH_ADDR (volatile uint32_t *)((0x1403 << 2) + 0xff900000)
5113 #define L_RGB_BASE_ADDR (0x1405)
5114 #define P_L_RGB_BASE_ADDR (volatile uint32_t *)((0x1405 << 2) + 0xff900000)
5115 #define L_RGB_COEFF_ADDR (0x1406)
5116 #define P_L_RGB_COEFF_ADDR (volatile uint32_t *)((0x1406 << 2) + 0xff900000)
5117 #define L_POL_CNTL_ADDR (0x1407)
5118 #define P_L_POL_CNTL_ADDR (volatile uint32_t *)((0x1407 << 2) + 0xff900000)
5119 #define L_DITH_CNTL_ADDR (0x1408)
5120 #define P_L_DITH_CNTL_ADDR (volatile uint32_t *)((0x1408 << 2) + 0xff900000)
5121 #define L_GAMMA_PROBE_CTRL (0x1409)
5122 #define P_L_GAMMA_PROBE_CTRL (volatile uint32_t *)((0x1409 << 2) + 0xff900000)
5123 //read only
5124 #define L_GAMMA_PROBE_COLOR_L (0x140a)
5125 #define P_L_GAMMA_PROBE_COLOR_L (volatile uint32_t *)((0x140a << 2) + 0xff900000)
5126 #define L_GAMMA_PROBE_COLOR_H (0x140b)
5127 #define P_L_GAMMA_PROBE_COLOR_H (volatile uint32_t *)((0x140b << 2) + 0xff900000)
5128 #define L_GAMMA_PROBE_HL_COLOR (0x140c)
5129 #define P_L_GAMMA_PROBE_HL_COLOR (volatile uint32_t *)((0x140c << 2) + 0xff900000)
5130 #define L_GAMMA_PROBE_POS_X (0x140d)
5131 #define P_L_GAMMA_PROBE_POS_X (volatile uint32_t *)((0x140d << 2) + 0xff900000)
5132 #define L_GAMMA_PROBE_POS_Y (0x140e)
5133 #define P_L_GAMMA_PROBE_POS_Y (volatile uint32_t *)((0x140e << 2) + 0xff900000)
5134 #define L_STH1_HS_ADDR (0x1410)
5135 #define P_L_STH1_HS_ADDR (volatile uint32_t *)((0x1410 << 2) + 0xff900000)
5136 #define L_STH1_HE_ADDR (0x1411)
5137 #define P_L_STH1_HE_ADDR (volatile uint32_t *)((0x1411 << 2) + 0xff900000)
5138 #define L_STH1_VS_ADDR (0x1412)
5139 #define P_L_STH1_VS_ADDR (volatile uint32_t *)((0x1412 << 2) + 0xff900000)
5140 #define L_STH1_VE_ADDR (0x1413)
5141 #define P_L_STH1_VE_ADDR (volatile uint32_t *)((0x1413 << 2) + 0xff900000)
5142 #define L_STH2_HS_ADDR (0x1414)
5143 #define P_L_STH2_HS_ADDR (volatile uint32_t *)((0x1414 << 2) + 0xff900000)
5144 #define L_STH2_HE_ADDR (0x1415)
5145 #define P_L_STH2_HE_ADDR (volatile uint32_t *)((0x1415 << 2) + 0xff900000)
5146 #define L_STH2_VS_ADDR (0x1416)
5147 #define P_L_STH2_VS_ADDR (volatile uint32_t *)((0x1416 << 2) + 0xff900000)
5148 #define L_STH2_VE_ADDR (0x1417)
5149 #define P_L_STH2_VE_ADDR (volatile uint32_t *)((0x1417 << 2) + 0xff900000)
5150 #define L_OEH_HS_ADDR (0x1418)
5151 #define P_L_OEH_HS_ADDR (volatile uint32_t *)((0x1418 << 2) + 0xff900000)
5152 #define L_OEH_HE_ADDR (0x1419)
5153 #define P_L_OEH_HE_ADDR (volatile uint32_t *)((0x1419 << 2) + 0xff900000)
5154 #define L_OEH_VS_ADDR (0x141a)
5155 #define P_L_OEH_VS_ADDR (volatile uint32_t *)((0x141a << 2) + 0xff900000)
5156 #define L_OEH_VE_ADDR (0x141b)
5157 #define P_L_OEH_VE_ADDR (volatile uint32_t *)((0x141b << 2) + 0xff900000)
5158 #define L_VCOM_HSWITCH_ADDR (0x141c)
5159 #define P_L_VCOM_HSWITCH_ADDR (volatile uint32_t *)((0x141c << 2) + 0xff900000)
5160 #define L_VCOM_VS_ADDR (0x141d)
5161 #define P_L_VCOM_VS_ADDR (volatile uint32_t *)((0x141d << 2) + 0xff900000)
5162 #define L_VCOM_VE_ADDR (0x141e)
5163 #define P_L_VCOM_VE_ADDR (volatile uint32_t *)((0x141e << 2) + 0xff900000)
5164 #define L_CPV1_HS_ADDR (0x141f)
5165 #define P_L_CPV1_HS_ADDR (volatile uint32_t *)((0x141f << 2) + 0xff900000)
5166 #define L_CPV1_HE_ADDR (0x1420)
5167 #define P_L_CPV1_HE_ADDR (volatile uint32_t *)((0x1420 << 2) + 0xff900000)
5168 #define L_CPV1_VS_ADDR (0x1421)
5169 #define P_L_CPV1_VS_ADDR (volatile uint32_t *)((0x1421 << 2) + 0xff900000)
5170 #define L_CPV1_VE_ADDR (0x1422)
5171 #define P_L_CPV1_VE_ADDR (volatile uint32_t *)((0x1422 << 2) + 0xff900000)
5172 #define L_CPV2_HS_ADDR (0x1423)
5173 #define P_L_CPV2_HS_ADDR (volatile uint32_t *)((0x1423 << 2) + 0xff900000)
5174 #define L_CPV2_HE_ADDR (0x1424)
5175 #define P_L_CPV2_HE_ADDR (volatile uint32_t *)((0x1424 << 2) + 0xff900000)
5176 #define L_CPV2_VS_ADDR (0x1425)
5177 #define P_L_CPV2_VS_ADDR (volatile uint32_t *)((0x1425 << 2) + 0xff900000)
5178 #define L_CPV2_VE_ADDR (0x1426)
5179 #define P_L_CPV2_VE_ADDR (volatile uint32_t *)((0x1426 << 2) + 0xff900000)
5180 #define L_STV1_HS_ADDR (0x1427)
5181 #define P_L_STV1_HS_ADDR (volatile uint32_t *)((0x1427 << 2) + 0xff900000)
5182 #define L_STV1_HE_ADDR (0x1428)
5183 #define P_L_STV1_HE_ADDR (volatile uint32_t *)((0x1428 << 2) + 0xff900000)
5184 #define L_STV1_VS_ADDR (0x1429)
5185 #define P_L_STV1_VS_ADDR (volatile uint32_t *)((0x1429 << 2) + 0xff900000)
5186 #define L_STV1_VE_ADDR (0x142a)
5187 #define P_L_STV1_VE_ADDR (volatile uint32_t *)((0x142a << 2) + 0xff900000)
5188 #define L_STV2_HS_ADDR (0x142b)
5189 #define P_L_STV2_HS_ADDR (volatile uint32_t *)((0x142b << 2) + 0xff900000)
5190 #define L_STV2_HE_ADDR (0x142c)
5191 #define P_L_STV2_HE_ADDR (volatile uint32_t *)((0x142c << 2) + 0xff900000)
5192 #define L_STV2_VS_ADDR (0x142d)
5193 #define P_L_STV2_VS_ADDR (volatile uint32_t *)((0x142d << 2) + 0xff900000)
5194 #define L_STV2_VE_ADDR (0x142e)
5195 #define P_L_STV2_VE_ADDR (volatile uint32_t *)((0x142e << 2) + 0xff900000)
5196 #define L_OEV1_HS_ADDR (0x142f)
5197 #define P_L_OEV1_HS_ADDR (volatile uint32_t *)((0x142f << 2) + 0xff900000)
5198 #define L_OEV1_HE_ADDR (0x1430)
5199 #define P_L_OEV1_HE_ADDR (volatile uint32_t *)((0x1430 << 2) + 0xff900000)
5200 #define L_OEV1_VS_ADDR (0x1431)
5201 #define P_L_OEV1_VS_ADDR (volatile uint32_t *)((0x1431 << 2) + 0xff900000)
5202 #define L_OEV1_VE_ADDR (0x1432)
5203 #define P_L_OEV1_VE_ADDR (volatile uint32_t *)((0x1432 << 2) + 0xff900000)
5204 #define L_OEV2_HS_ADDR (0x1433)
5205 #define P_L_OEV2_HS_ADDR (volatile uint32_t *)((0x1433 << 2) + 0xff900000)
5206 #define L_OEV2_HE_ADDR (0x1434)
5207 #define P_L_OEV2_HE_ADDR (volatile uint32_t *)((0x1434 << 2) + 0xff900000)
5208 #define L_OEV2_VS_ADDR (0x1435)
5209 #define P_L_OEV2_VS_ADDR (volatile uint32_t *)((0x1435 << 2) + 0xff900000)
5210 #define L_OEV2_VE_ADDR (0x1436)
5211 #define P_L_OEV2_VE_ADDR (volatile uint32_t *)((0x1436 << 2) + 0xff900000)
5212 #define L_OEV3_HS_ADDR (0x1437)
5213 #define P_L_OEV3_HS_ADDR (volatile uint32_t *)((0x1437 << 2) + 0xff900000)
5214 #define L_OEV3_HE_ADDR (0x1438)
5215 #define P_L_OEV3_HE_ADDR (volatile uint32_t *)((0x1438 << 2) + 0xff900000)
5216 #define L_OEV3_VS_ADDR (0x1439)
5217 #define P_L_OEV3_VS_ADDR (volatile uint32_t *)((0x1439 << 2) + 0xff900000)
5218 #define L_OEV3_VE_ADDR (0x143a)
5219 #define P_L_OEV3_VE_ADDR (volatile uint32_t *)((0x143a << 2) + 0xff900000)
5220 #define L_LCD_PWR_ADDR (0x143b)
5221 #define P_L_LCD_PWR_ADDR (volatile uint32_t *)((0x143b << 2) + 0xff900000)
5222 #define L_LCD_PWM0_LO_ADDR (0x143c)
5223 #define P_L_LCD_PWM0_LO_ADDR (volatile uint32_t *)((0x143c << 2) + 0xff900000)
5224 #define L_LCD_PWM0_HI_ADDR (0x143d)
5225 #define P_L_LCD_PWM0_HI_ADDR (volatile uint32_t *)((0x143d << 2) + 0xff900000)
5226 #define L_LCD_PWM1_LO_ADDR (0x143e)
5227 #define P_L_LCD_PWM1_LO_ADDR (volatile uint32_t *)((0x143e << 2) + 0xff900000)
5228 #define L_LCD_PWM1_HI_ADDR (0x143f)
5229 #define P_L_LCD_PWM1_HI_ADDR (volatile uint32_t *)((0x143f << 2) + 0xff900000)
5230 #define L_INV_CNT_ADDR (0x1440)
5231 #define P_L_INV_CNT_ADDR (volatile uint32_t *)((0x1440 << 2) + 0xff900000)
5232 #define L_TCON_MISC_SEL_ADDR (0x1441)
5233 #define P_L_TCON_MISC_SEL_ADDR (volatile uint32_t *)((0x1441 << 2) + 0xff900000)
5234 #define L_DUAL_PORT_CNTL_ADDR (0x1442)
5235 #define P_L_DUAL_PORT_CNTL_ADDR (volatile uint32_t *)((0x1442 << 2) + 0xff900000)
5236 #define MLVDS_CLK_CTL1_HI (0x1443)
5237 #define P_MLVDS_CLK_CTL1_HI (volatile uint32_t *)((0x1443 << 2) + 0xff900000)
5238 #define MLVDS_CLK_CTL1_LO (0x1444)
5239 #define P_MLVDS_CLK_CTL1_LO (volatile uint32_t *)((0x1444 << 2) + 0xff900000)
5240 // [31:30] enable mlvds clocks
5241 // [24] mlvds_clk_half_delay 24 // Bit 0
5242 // [23:0] mlvds_clk_pattern 0 // Bit 23:0
5243 #define L_TCON_DOUBLE_CTL (0x1449)
5244 #define P_L_TCON_DOUBLE_CTL (volatile uint32_t *)((0x1449 << 2) + 0xff900000)
5245 #define L_TCON_PATTERN_HI (0x144a)
5246 #define P_L_TCON_PATTERN_HI (volatile uint32_t *)((0x144a << 2) + 0xff900000)
5247 #define L_TCON_PATTERN_LO (0x144b)
5248 #define P_L_TCON_PATTERN_LO (volatile uint32_t *)((0x144b << 2) + 0xff900000)
5249 #define LDIM_BL_ADDR_PORT (0x144e)
5250 #define P_LDIM_BL_ADDR_PORT (volatile uint32_t *)((0x144e << 2) + 0xff900000)
5251 #define LDIM_BL_DATA_PORT (0x144f)
5252 #define P_LDIM_BL_DATA_PORT (volatile uint32_t *)((0x144f << 2) + 0xff900000)
5253 #define L_DE_HS_ADDR (0x1451)
5254 #define P_L_DE_HS_ADDR (volatile uint32_t *)((0x1451 << 2) + 0xff900000)
5255 #define L_DE_HE_ADDR (0x1452)
5256 #define P_L_DE_HE_ADDR (volatile uint32_t *)((0x1452 << 2) + 0xff900000)
5257 #define L_DE_VS_ADDR (0x1453)
5258 #define P_L_DE_VS_ADDR (volatile uint32_t *)((0x1453 << 2) + 0xff900000)
5259 #define L_DE_VE_ADDR (0x1454)
5260 #define P_L_DE_VE_ADDR (volatile uint32_t *)((0x1454 << 2) + 0xff900000)
5261 #define L_HSYNC_HS_ADDR (0x1455)
5262 #define P_L_HSYNC_HS_ADDR (volatile uint32_t *)((0x1455 << 2) + 0xff900000)
5263 #define L_HSYNC_HE_ADDR (0x1456)
5264 #define P_L_HSYNC_HE_ADDR (volatile uint32_t *)((0x1456 << 2) + 0xff900000)
5265 #define L_HSYNC_VS_ADDR (0x1457)
5266 #define P_L_HSYNC_VS_ADDR (volatile uint32_t *)((0x1457 << 2) + 0xff900000)
5267 #define L_HSYNC_VE_ADDR (0x1458)
5268 #define P_L_HSYNC_VE_ADDR (volatile uint32_t *)((0x1458 << 2) + 0xff900000)
5269 #define L_VSYNC_HS_ADDR (0x1459)
5270 #define P_L_VSYNC_HS_ADDR (volatile uint32_t *)((0x1459 << 2) + 0xff900000)
5271 #define L_VSYNC_HE_ADDR (0x145a)
5272 #define P_L_VSYNC_HE_ADDR (volatile uint32_t *)((0x145a << 2) + 0xff900000)
5273 #define L_VSYNC_VS_ADDR (0x145b)
5274 #define P_L_VSYNC_VS_ADDR (volatile uint32_t *)((0x145b << 2) + 0xff900000)
5275 #define L_VSYNC_VE_ADDR (0x145c)
5276 #define P_L_VSYNC_VE_ADDR (volatile uint32_t *)((0x145c << 2) + 0xff900000)
5277 // bit 8 -- vfifo_mcu_enable
5278 // bit 7 -- halt_vs_de
5279 // bit 6 -- R8G8B8_format
5280 // bit 5 -- R6G6B6_format (round to 6 bits)
5281 // bit 4 -- R5G6B5_format
5282 // bit 3 -- dac_dith_sel
5283 // bit 2 -- lcd_mcu_enable_de -- ReadOnly
5284 // bit 1 -- lcd_mcu_enable_vsync -- ReadOnly
5285 // bit 0 -- lcd_mcu_enable
5286 #define L_LCD_MCU_CTL (0x145d)
5287 #define P_L_LCD_MCU_CTL (volatile uint32_t *)((0x145d << 2) + 0xff900000)
5288 //**************************************************************************
5289 //* Dual port mLVDS registers
5290 //**************************************************************************
5291 // bit 3 - enable_u_dual_mlvds_dp_clk
5292 // bit 2 - enable_u_map_mlvds_r_clk
5293 // bit 1 - enable_u_map_mlvds_l_clk
5294 // bit 0 - dual_mlvds_en
5295 //`define DUAL_MLVDS_CTL 8'h60
5296 // bit[12:0] - dual_mlvds_line_start
5297 //`define DUAL_MLVDS_LINE_START 8'h61
5298 // bit[12:0] - dual_mlvds_line_end
5299 //`define DUAL_MLVDS_LINE_END 8'h62
5300 // bit[12:0] - dual_mlvds_w_pixel_start_l
5301 //`define DUAL_MLVDS_PIXEL_W_START_L 8'h63
5302 // bit[12:0] - dual_mlvds_w_pixel_end_l
5303 //`define DUAL_MLVDS_PIXEL_W_END_L 8'h64
5304 // bit[12:0] - dual_mlvds_w_pixel_start_r
5305 //`define DUAL_MLVDS_PIXEL_W_START_R 8'h65
5306 // bit[12:0] - dual_mlvds_w_pixel_end_r
5307 //`define DUAL_MLVDS_PIXEL_W_END_R 8'h66
5308 // bit[12:0] - dual_mlvds_r_pixel_start_l
5309 //`define DUAL_MLVDS_PIXEL_R_START_L 8'h67
5310 // bit[12:0] - dual_mlvds_r_pixel_cnt_l
5311 //`define DUAL_MLVDS_PIXEL_R_CNT_L 8'h68
5312 // bit[12:0] - dual_mlvds_r_pixel_start_r
5313 //`define DUAL_MLVDS_PIXEL_R_START_R 8'h69
5314 // bit[12:0] - dual_mlvds_r_pixel_cnt_r
5315 //`define DUAL_MLVDS_PIXEL_R_CNT_R 8'h6a
5316 // bit[15] - v_inversion_en
5317 // bit[12:0] - v_inversion_pixel
5318 //`define V_INVERSION_PIXEL 8'h70
5319 // bit[15] - v_inversion_sync_en
5320 // bit[12:0] - v_inversion_line
5321 //`define V_INVERSION_LINE 8'h71
5322 // bit[15:12] - v_loop_r
5323 // bit[11:10] - v_pattern_1_r
5324 // bit[9:8] - v_pattern_0_r
5325 // bit[7:4] - v_loop_l
5326 // bit[3:2] - v_pattern_1_l
5327 // bit[1:0] - v_pattern_0_l
5328 //`define V_INVERSION_CONTROL 8'h72
5329 //`define MLVDS2_CONTROL 8'h74
5330 #define mLVDS2_RESERVED 15 // 15
5331 #define mLVDS2_double_pattern 14 // 14
5332 #define mLVDS2_ins_reset 8 // 13:8 // each channel has one bit
5333 #define mLVDS2_dual_gate 7
5334 #define mLVDS2_bit_num 6 // 0-6Bits, 1-8Bits
5335 #define mLVDS2_pair_num 5 // 0-3Pairs, 1-6Pairs
5336 #define mLVDS2_msb_first 4
5337 #define mLVDS2_PORT_SWAP 3
5338 #define mLVDS2_MLSB_SWAP 2
5339 #define mLVDS2_PN_SWAP 1
5340 #define mLVDS2_en 0
5341 //`define MLVDS2_CONFIG_HI 8'h75
5342 //`define MLVDS2_CONFIG_LO 8'h76
5343 #define mLVDS2_reset_offset 29 // Bit 31:29
5344 #define mLVDS2_reset_length 23 // Bit 28:23
5345 #define mLVDS2_config_reserved 20 // Bit 22:20
5346 #define mLVDS2_reset_start_bit12 19 // Bit 19
5347 #define mLVDS2_data_write_toggle 18
5348 #define mLVDS2_data_write_ini 17
5349 #define mLVDS2_data_latch_1_toggle 16
5350 #define mLVDS2_data_latch_1_ini 15
5351 #define mLVDS2_data_latch_0_toggle 14
5352 #define mLVDS2_data_latch_0_ini 13
5353 #define mLVDS2_reset_1_select 12 // 0 - same as reset_0, 1 - 1 clock delay of reset_0
5354 #define mLVDS2_reset_start 0 // Bit 11:0
5355 //`define MLVDS2_DUAL_GATE_WR_START 8'h77
5356 // `define mlvds2_dual_gate_wr_start 0 // Bit 12:0
5357 //`define MLVDS2_DUAL_GATE_WR_END 8'h78
5358 // `define mlvds2_dual_gate_wr_end 0 // Bit 12:0
5359 //
5360 //`define MLVDS2_DUAL_GATE_RD_START 8'h79
5361 // `define mlvds2_dual_gate_rd_start 0 // Bit 12:0
5362 //`define MLVDS2_DUAL_GATE_RD_END 8'h7a
5363 // `define mlvds2_dual_gate_rd_end 0 // Bit 12:0
5364 //`define MLVDS2_SECOND_RESET_CTL 8'h7b
5365 // `define mLVDS2_2nd_reset_start 0 // Bit 12:0
5366 //
5367 //`define MLVDS2_DUAL_GATE_CTL_HI 8'h7c
5368 //`define MLVDS2_DUAL_GATE_CTL_LO 8'h7d
5369 // `define mlvds2_tcon_field_en 24 // Bit 7:0
5370 // `define mlvds2_dual_gate_reserved 21 // Bit 2:0
5371 // `define mlvds2_scan_mode_start_line_bit12 20 // Bit 0
5372 // `define mlvds2_scan_mode_odd 16 // Bit 3:0
5373 // `define mlvds2_scan_mode_even 12 // Bit 3:0
5374 // `define mlvds2_scan_mode_start_line 0 // Bit 11:0
5375 //
5376 //`define MLVDS2_RESET_CONFIG_HI 8'h7e
5377 //`define MLVDS2_RESET_CONFIG_LO 8'h7f
5378 // `define mLVDS2_reset_range_enable 31 // Bit 0
5379 // `define mLVDS2_reset_range_inv 30 // Bit 0
5380 // `define mLVDS2_reset_config_res1 29 // Bit 0
5381 // `define mLVDS2_reset_range_line_0 16 // Bit 11:0
5382 // `define mLVDS2_reset_config_res3 13 // Bit 2:0
5383 // `define mLVDS2_reset_range_line_1 0 // Bit 11:0
5384 //
5385 //**************************************************************************
5386 //* Vbyone registers (Note: no MinLVDS in G9tv, share the register)
5387 //**************************************************************************
5388 #define VBO_CTRL_L (0x1460)
5389 #define P_VBO_CTRL_L (volatile uint32_t *)((0x1460 << 2) + 0xff900000)
5390 #define VBO_CTRL_H (0x1461)
5391 #define P_VBO_CTRL_H (volatile uint32_t *)((0x1461 << 2) + 0xff900000)
5392 #define VBO_SOFT_RST (0x1462)
5393 #define P_VBO_SOFT_RST (volatile uint32_t *)((0x1462 << 2) + 0xff900000)
5394 #define VBO_LANES (0x1463)
5395 #define P_VBO_LANES (volatile uint32_t *)((0x1463 << 2) + 0xff900000)
5396 #define VBO_VIN_CTRL (0x1464)
5397 #define P_VBO_VIN_CTRL (volatile uint32_t *)((0x1464 << 2) + 0xff900000)
5398 #define VBO_ACT_VSIZE (0x1465)
5399 #define P_VBO_ACT_VSIZE (volatile uint32_t *)((0x1465 << 2) + 0xff900000)
5400 #define VBO_REGION_00 (0x1466)
5401 #define P_VBO_REGION_00 (volatile uint32_t *)((0x1466 << 2) + 0xff900000)
5402 #define VBO_REGION_01 (0x1467)
5403 #define P_VBO_REGION_01 (volatile uint32_t *)((0x1467 << 2) + 0xff900000)
5404 #define VBO_REGION_02 (0x1468)
5405 #define P_VBO_REGION_02 (volatile uint32_t *)((0x1468 << 2) + 0xff900000)
5406 #define VBO_REGION_03 (0x1469)
5407 #define P_VBO_REGION_03 (volatile uint32_t *)((0x1469 << 2) + 0xff900000)
5408 #define VBO_VBK_CTRL_0 (0x146a)
5409 #define P_VBO_VBK_CTRL_0 (volatile uint32_t *)((0x146a << 2) + 0xff900000)
5410 #define VBO_VBK_CTRL_1 (0x146b)
5411 #define P_VBO_VBK_CTRL_1 (volatile uint32_t *)((0x146b << 2) + 0xff900000)
5412 #define VBO_HBK_CTRL (0x146c)
5413 #define P_VBO_HBK_CTRL (volatile uint32_t *)((0x146c << 2) + 0xff900000)
5414 #define VBO_PXL_CTRL (0x146d)
5415 #define P_VBO_PXL_CTRL (volatile uint32_t *)((0x146d << 2) + 0xff900000)
5416 #define VBO_LANE_SKEW_L (0x146e)
5417 #define P_VBO_LANE_SKEW_L (volatile uint32_t *)((0x146e << 2) + 0xff900000)
5418 #define VBO_LANE_SKEW_H (0x146f)
5419 #define P_VBO_LANE_SKEW_H (volatile uint32_t *)((0x146f << 2) + 0xff900000)
5420 #define VBO_GCLK_LANE_L (0x1470)
5421 #define P_VBO_GCLK_LANE_L (volatile uint32_t *)((0x1470 << 2) + 0xff900000)
5422 #define VBO_GCLK_LANE_H (0x1471)
5423 #define P_VBO_GCLK_LANE_H (volatile uint32_t *)((0x1471 << 2) + 0xff900000)
5424 #define VBO_GCLK_MAIN (0x1472)
5425 #define P_VBO_GCLK_MAIN (volatile uint32_t *)((0x1472 << 2) + 0xff900000)
5426 #define VBO_STATUS_L (0x1473)
5427 #define P_VBO_STATUS_L (volatile uint32_t *)((0x1473 << 2) + 0xff900000)
5428 #define VBO_STATUS_H (0x1474)
5429 #define P_VBO_STATUS_H (volatile uint32_t *)((0x1474 << 2) + 0xff900000)
5430 #define VBO_LANE_OUTPUT (0x1475)
5431 #define P_VBO_LANE_OUTPUT (volatile uint32_t *)((0x1475 << 2) + 0xff900000)
5432 #define LCD_PORT_SWAP (0x1476)
5433 #define P_LCD_PORT_SWAP (volatile uint32_t *)((0x1476 << 2) + 0xff900000)
5434 #define VBO_TMCHK_THRD_L (0x1478)
5435 #define P_VBO_TMCHK_THRD_L (volatile uint32_t *)((0x1478 << 2) + 0xff900000)
5436 #define VBO_TMCHK_THRD_H (0x1479)
5437 #define P_VBO_TMCHK_THRD_H (volatile uint32_t *)((0x1479 << 2) + 0xff900000)
5438 #define VBO_FSM_HOLDER_L (0x147a)
5439 #define P_VBO_FSM_HOLDER_L (volatile uint32_t *)((0x147a << 2) + 0xff900000)
5440 #define VBO_FSM_HOLDER_H (0x147b)
5441 #define P_VBO_FSM_HOLDER_H (volatile uint32_t *)((0x147b << 2) + 0xff900000)
5442 #define VBO_INTR_STATE_CTRL (0x147c)
5443 #define P_VBO_INTR_STATE_CTRL (volatile uint32_t *)((0x147c << 2) + 0xff900000)
5444 #define VBO_INTR_UNMASK (0x147d)
5445 #define P_VBO_INTR_UNMASK (volatile uint32_t *)((0x147d << 2) + 0xff900000)
5446 #define VBO_TMCHK_HSYNC_STATE_L (0x147e)
5447 #define P_VBO_TMCHK_HSYNC_STATE_L (volatile uint32_t *)((0x147e << 2) + 0xff900000)
5448 #define VBO_TMCHK_HSYNC_STATE_H (0x147f)
5449 #define P_VBO_TMCHK_HSYNC_STATE_H (volatile uint32_t *)((0x147f << 2) + 0xff900000)
5450 #define VBO_TMCHK_VSYNC_STATE_L (0x14f4)
5451 #define P_VBO_TMCHK_VSYNC_STATE_L (volatile uint32_t *)((0x14f4 << 2) + 0xff900000)
5452 #define VBO_TMCHK_VSYNC_STATE_H (0x14f5)
5453 #define P_VBO_TMCHK_VSYNC_STATE_H (volatile uint32_t *)((0x14f5 << 2) + 0xff900000)
5454 #define VBO_TMCHK_VDE_STATE_L (0x14f6)
5455 #define P_VBO_TMCHK_VDE_STATE_L (volatile uint32_t *)((0x14f6 << 2) + 0xff900000)
5456 #define VBO_TMCHK_VDE_STATE_H (0x14f7)
5457 #define P_VBO_TMCHK_VDE_STATE_H (volatile uint32_t *)((0x14f7 << 2) + 0xff900000)
5458 #define VBO_INTR_STATE (0x14f8)
5459 #define P_VBO_INTR_STATE (volatile uint32_t *)((0x14f8 << 2) + 0xff900000)
5460 #define VBO_INFILTER_CTRL (0x14f9)
5461 #define P_VBO_INFILTER_CTRL (volatile uint32_t *)((0x14f9 << 2) + 0xff900000)
5462 #define VBO_INSGN_CTRL (0x14fa)
5463 #define P_VBO_INSGN_CTRL (volatile uint32_t *)((0x14fa << 2) + 0xff900000)
5464 //**************************************************************************
5465 //* NOTE:: When Programming the Gamma, please turn off the IRQ service *
5466 //**************************************************************************
5467 #define GAMMA_CNTL_PORT (0x1480)
5468 #define P_GAMMA_CNTL_PORT (volatile uint32_t *)((0x1480 << 2) + 0xff900000)
5469 #define GAMMA_VCOM_POL 7 //RW
5470 #define GAMMA_RVS_OUT 6 //RW
5471 #define ADR_RDY 5 //Read Only
5472 #define WR_RDY 4 //Read Only
5473 #define RD_RDY 3 //Read Only
5474 #define GAMMA_TR 2 //RW
5475 #define GAMMA_SET 1 //RW
5476 #define GAMMA_EN 0 //RW
5477 #define GAMMA_DATA_PORT (0x1481)
5478 #define P_GAMMA_DATA_PORT (volatile uint32_t *)((0x1481 << 2) + 0xff900000)
5479 #define GAMMA_ADDR_PORT (0x1482)
5480 #define P_GAMMA_ADDR_PORT (volatile uint32_t *)((0x1482 << 2) + 0xff900000)
5481 #define H_RD 12
5482 #define H_AUTO_INC 11
5483 #define H_SEL_R 10
5484 #define H_SEL_G 9
5485 #define H_SEL_B 8
5486 #define HADR_MSB 7 //7:0
5487 #define HADR 0 //7:0
5488 #define GAMMA_VCOM_HSWITCH_ADDR (0x1483)
5489 #define P_GAMMA_VCOM_HSWITCH_ADDR (volatile uint32_t *)((0x1483 << 2) + 0xff900000)
5490 #define RGB_BASE_ADDR (0x1485)
5491 #define P_RGB_BASE_ADDR (volatile uint32_t *)((0x1485 << 2) + 0xff900000)
5492 #define RGB_COEFF_ADDR (0x1486)
5493 #define P_RGB_COEFF_ADDR (volatile uint32_t *)((0x1486 << 2) + 0xff900000)
5494 #define POL_CNTL_ADDR (0x1487)
5495 #define P_POL_CNTL_ADDR (volatile uint32_t *)((0x1487 << 2) + 0xff900000)
5496 #define DCLK_SEL 14 //FOR DCLK OUTPUT
5497 #define TCON_VSYNC_SEL_DVI 11 //FOR RGB format DVI output
5498 #define TCON_HSYNC_SEL_DVI 10 //FOR RGB format DVI output
5499 #define TCON_DE_SEL_DVI 9 //FOR RGB format DVI output
5500 #define CPH3_POL 8
5501 #define CPH2_POL 7
5502 #define CPH1_POL 6
5503 #define TCON_DE_SEL 5
5504 #define TCON_VS_SEL 4
5505 #define TCON_HS_SEL 3
5506 #define DE_POL 2
5507 #define VS_POL 1
5508 #define HS_POL 0
5509 #define DITH_CNTL_ADDR (0x1488)
5510 #define P_DITH_CNTL_ADDR (volatile uint32_t *)((0x1488 << 2) + 0xff900000)
5511 #define DITH10_EN 10
5512 #define DITH8_EN 9
5513 #define DITH_MD 8
5514 #define DITH10_CNTL_MSB 7 //7:4
5515 #define DITH10_CNTL 4 //7:4
5516 #define DITH8_CNTL_MSB 3 //3:0
5517 #define DITH8_CNTL 0 //3:0
5518 //Bit 1 highlight_en
5519 //Bit 0 probe_en
5520 #define GAMMA_PROBE_CTRL (0x1489)
5521 #define P_GAMMA_PROBE_CTRL (volatile uint32_t *)((0x1489 << 2) + 0xff900000)
5522 //read only
5523 //Bit [15:0] probe_color[15:0]
5524 #define GAMMA_PROBE_COLOR_L (0x148a)
5525 #define P_GAMMA_PROBE_COLOR_L (volatile uint32_t *)((0x148a << 2) + 0xff900000)
5526 //Read only
5527 //Bit 15: if true valid probed color
5528 //Bit [13:0] probe_color[29:16]
5529 #define GAMMA_PROBE_COLOR_H (0x148b)
5530 #define P_GAMMA_PROBE_COLOR_H (volatile uint32_t *)((0x148b << 2) + 0xff900000)
5531 //bit 15:0, 5:6:5 color
5532 #define GAMMA_PROBE_HL_COLOR (0x148c)
5533 #define P_GAMMA_PROBE_HL_COLOR (volatile uint32_t *)((0x148c << 2) + 0xff900000)
5534 //12:0 pos_x
5535 #define GAMMA_PROBE_POS_X (0x148d)
5536 #define P_GAMMA_PROBE_POS_X (volatile uint32_t *)((0x148d << 2) + 0xff900000)
5537 //12:0 pos_y
5538 #define GAMMA_PROBE_POS_Y (0x148e)
5539 #define P_GAMMA_PROBE_POS_Y (volatile uint32_t *)((0x148e << 2) + 0xff900000)
5540 #define STH1_HS_ADDR (0x1490)
5541 #define P_STH1_HS_ADDR (volatile uint32_t *)((0x1490 << 2) + 0xff900000)
5542 #define STH1_HE_ADDR (0x1491)
5543 #define P_STH1_HE_ADDR (volatile uint32_t *)((0x1491 << 2) + 0xff900000)
5544 #define STH1_VS_ADDR (0x1492)
5545 #define P_STH1_VS_ADDR (volatile uint32_t *)((0x1492 << 2) + 0xff900000)
5546 #define STH1_VE_ADDR (0x1493)
5547 #define P_STH1_VE_ADDR (volatile uint32_t *)((0x1493 << 2) + 0xff900000)
5548 #define STH2_HS_ADDR (0x1494)
5549 #define P_STH2_HS_ADDR (volatile uint32_t *)((0x1494 << 2) + 0xff900000)
5550 #define STH2_HE_ADDR (0x1495)
5551 #define P_STH2_HE_ADDR (volatile uint32_t *)((0x1495 << 2) + 0xff900000)
5552 #define STH2_VS_ADDR (0x1496)
5553 #define P_STH2_VS_ADDR (volatile uint32_t *)((0x1496 << 2) + 0xff900000)
5554 #define STH2_VE_ADDR (0x1497)
5555 #define P_STH2_VE_ADDR (volatile uint32_t *)((0x1497 << 2) + 0xff900000)
5556 #define OEH_HS_ADDR (0x1498)
5557 #define P_OEH_HS_ADDR (volatile uint32_t *)((0x1498 << 2) + 0xff900000)
5558 #define OEH_HE_ADDR (0x1499)
5559 #define P_OEH_HE_ADDR (volatile uint32_t *)((0x1499 << 2) + 0xff900000)
5560 #define OEH_VS_ADDR (0x149a)
5561 #define P_OEH_VS_ADDR (volatile uint32_t *)((0x149a << 2) + 0xff900000)
5562 #define OEH_VE_ADDR (0x149b)
5563 #define P_OEH_VE_ADDR (volatile uint32_t *)((0x149b << 2) + 0xff900000)
5564 #define VCOM_HSWITCH_ADDR (0x149c)
5565 #define P_VCOM_HSWITCH_ADDR (volatile uint32_t *)((0x149c << 2) + 0xff900000)
5566 #define VCOM_VS_ADDR (0x149d)
5567 #define P_VCOM_VS_ADDR (volatile uint32_t *)((0x149d << 2) + 0xff900000)
5568 #define VCOM_VE_ADDR (0x149e)
5569 #define P_VCOM_VE_ADDR (volatile uint32_t *)((0x149e << 2) + 0xff900000)
5570 #define CPV1_HS_ADDR (0x149f)
5571 #define P_CPV1_HS_ADDR (volatile uint32_t *)((0x149f << 2) + 0xff900000)
5572 #define CPV1_HE_ADDR (0x14a0)
5573 #define P_CPV1_HE_ADDR (volatile uint32_t *)((0x14a0 << 2) + 0xff900000)
5574 #define CPV1_VS_ADDR (0x14a1)
5575 #define P_CPV1_VS_ADDR (volatile uint32_t *)((0x14a1 << 2) + 0xff900000)
5576 #define CPV1_VE_ADDR (0x14a2)
5577 #define P_CPV1_VE_ADDR (volatile uint32_t *)((0x14a2 << 2) + 0xff900000)
5578 #define CPV2_HS_ADDR (0x14a3)
5579 #define P_CPV2_HS_ADDR (volatile uint32_t *)((0x14a3 << 2) + 0xff900000)
5580 #define CPV2_HE_ADDR (0x14a4)
5581 #define P_CPV2_HE_ADDR (volatile uint32_t *)((0x14a4 << 2) + 0xff900000)
5582 #define CPV2_VS_ADDR (0x14a5)
5583 #define P_CPV2_VS_ADDR (volatile uint32_t *)((0x14a5 << 2) + 0xff900000)
5584 #define CPV2_VE_ADDR (0x14a6)
5585 #define P_CPV2_VE_ADDR (volatile uint32_t *)((0x14a6 << 2) + 0xff900000)
5586 #define STV1_HS_ADDR (0x14a7)
5587 #define P_STV1_HS_ADDR (volatile uint32_t *)((0x14a7 << 2) + 0xff900000)
5588 #define STV1_HE_ADDR (0x14a8)
5589 #define P_STV1_HE_ADDR (volatile uint32_t *)((0x14a8 << 2) + 0xff900000)
5590 #define STV1_VS_ADDR (0x14a9)
5591 #define P_STV1_VS_ADDR (volatile uint32_t *)((0x14a9 << 2) + 0xff900000)
5592 #define STV1_VE_ADDR (0x14aa)
5593 #define P_STV1_VE_ADDR (volatile uint32_t *)((0x14aa << 2) + 0xff900000)
5594 #define STV2_HS_ADDR (0x14ab)
5595 #define P_STV2_HS_ADDR (volatile uint32_t *)((0x14ab << 2) + 0xff900000)
5596 #define STV2_HE_ADDR (0x14ac)
5597 #define P_STV2_HE_ADDR (volatile uint32_t *)((0x14ac << 2) + 0xff900000)
5598 #define STV2_VS_ADDR (0x14ad)
5599 #define P_STV2_VS_ADDR (volatile uint32_t *)((0x14ad << 2) + 0xff900000)
5600 #define STV2_VE_ADDR (0x14ae)
5601 #define P_STV2_VE_ADDR (volatile uint32_t *)((0x14ae << 2) + 0xff900000)
5602 #define OEV1_HS_ADDR (0x14af)
5603 #define P_OEV1_HS_ADDR (volatile uint32_t *)((0x14af << 2) + 0xff900000)
5604 #define OEV1_HE_ADDR (0x14b0)
5605 #define P_OEV1_HE_ADDR (volatile uint32_t *)((0x14b0 << 2) + 0xff900000)
5606 #define OEV1_VS_ADDR (0x14b1)
5607 #define P_OEV1_VS_ADDR (volatile uint32_t *)((0x14b1 << 2) + 0xff900000)
5608 #define OEV1_VE_ADDR (0x14b2)
5609 #define P_OEV1_VE_ADDR (volatile uint32_t *)((0x14b2 << 2) + 0xff900000)
5610 #define OEV2_HS_ADDR (0x14b3)
5611 #define P_OEV2_HS_ADDR (volatile uint32_t *)((0x14b3 << 2) + 0xff900000)
5612 #define OEV2_HE_ADDR (0x14b4)
5613 #define P_OEV2_HE_ADDR (volatile uint32_t *)((0x14b4 << 2) + 0xff900000)
5614 #define OEV2_VS_ADDR (0x14b5)
5615 #define P_OEV2_VS_ADDR (volatile uint32_t *)((0x14b5 << 2) + 0xff900000)
5616 #define OEV2_VE_ADDR (0x14b6)
5617 #define P_OEV2_VE_ADDR (volatile uint32_t *)((0x14b6 << 2) + 0xff900000)
5618 #define OEV3_HS_ADDR (0x14b7)
5619 #define P_OEV3_HS_ADDR (volatile uint32_t *)((0x14b7 << 2) + 0xff900000)
5620 #define OEV3_HE_ADDR (0x14b8)
5621 #define P_OEV3_HE_ADDR (volatile uint32_t *)((0x14b8 << 2) + 0xff900000)
5622 #define OEV3_VS_ADDR (0x14b9)
5623 #define P_OEV3_VS_ADDR (volatile uint32_t *)((0x14b9 << 2) + 0xff900000)
5624 #define OEV3_VE_ADDR (0x14ba)
5625 #define P_OEV3_VE_ADDR (volatile uint32_t *)((0x14ba << 2) + 0xff900000)
5626 #define LCD_PWR_ADDR (0x14bb)
5627 #define P_LCD_PWR_ADDR (volatile uint32_t *)((0x14bb << 2) + 0xff900000)
5628 #define LCD_VDD 5
5629 #define LCD_VBL 4
5630 #define LCD_GPI_MSB 3
5631 #define LCD_GPIO 0
5632 #define LCD_PWM0_LO_ADDR (0x14bc)
5633 #define P_LCD_PWM0_LO_ADDR (volatile uint32_t *)((0x14bc << 2) + 0xff900000)
5634 #define LCD_PWM0_HI_ADDR (0x14bd)
5635 #define P_LCD_PWM0_HI_ADDR (volatile uint32_t *)((0x14bd << 2) + 0xff900000)
5636 #define LCD_PWM1_LO_ADDR (0x14be)
5637 #define P_LCD_PWM1_LO_ADDR (volatile uint32_t *)((0x14be << 2) + 0xff900000)
5638 #define LCD_PWM1_HI_ADDR (0x14bf)
5639 #define P_LCD_PWM1_HI_ADDR (volatile uint32_t *)((0x14bf << 2) + 0xff900000)
5640 #define INV_CNT_ADDR (0x14c0)
5641 #define P_INV_CNT_ADDR (volatile uint32_t *)((0x14c0 << 2) + 0xff900000)
5642 #define INV_EN 4
5643 #define INV_CNT_MSB 3
5644 #define INV_CNT 0
5645 #define TCON_MISC_SEL_ADDR (0x14c1)
5646 #define P_TCON_MISC_SEL_ADDR (volatile uint32_t *)((0x14c1 << 2) + 0xff900000)
5647 #define STH2_SEL 12
5648 #define STH1_SEL 11
5649 #define OEH_SEL 10
5650 #define VCOM_SEL 9
5651 #define DB_LINE_SW 8
5652 #define CPV2_SEL 7
5653 #define CPV1_SEL 6
5654 #define STV2_SEL 5
5655 #define STV1_SEL 4
5656 #define OEV_UNITE 3
5657 #define OEV3_SEL 2
5658 #define OEV2_SEL 1
5659 #define OEV1_SEL 0
5660 #define DUAL_PORT_CNTL_ADDR (0x14c2)
5661 #define P_DUAL_PORT_CNTL_ADDR (volatile uint32_t *)((0x14c2 << 2) + 0xff900000)
5662 #define OUTPUT_YUV 15
5663 #define DUAL_IDF 12 // 14:12
5664 #define DUAL_ISF 9 // 11:9
5665 #define LCD_ANALOG_SEL_CPH3 8
5666 #define LCD_ANALOG_3PHI_CLK_SEL 7
5667 #define LCD_LVDS_SEL54 6
5668 #define LCD_LVDS_SEL27 5
5669 #define LCD_TTL_SEL 4
5670 #define DUAL_LVDC_EN 3
5671 #define PORT_SWP 2
5672 #define RGB_SWP 1
5673 #define BIT_SWP 0
5674 #define MLVDS_CONTROL (0x14c3)
5675 #define P_MLVDS_CONTROL (volatile uint32_t *)((0x14c3 << 2) + 0xff900000)
5676 #define mLVDS_RESERVED 15 // 15
5677 #define mLVDS_double_pattern 14 // 14
5678 #define mLVDS_ins_reset 8 // 13:8 // each channel has one bit
5679 #define mLVDS_dual_gate 7
5680 #define mLVDS_bit_num 6 // 0-6Bits, 1-8Bits
5681 #define mLVDS_pair_num 5 // 0-3Pairs, 1-6Pairs
5682 #define mLVDS_msb_first 4
5683 #define mLVDS_PORT_SWAP 3
5684 #define mLVDS_MLSB_SWAP 2
5685 #define mLVDS_PN_SWAP 1
5686 #define mLVDS_en 0
5687 #define MLVDS_RESET_PATTERN_HI (0x14c4)
5688 #define P_MLVDS_RESET_PATTERN_HI (volatile uint32_t *)((0x14c4 << 2) + 0xff900000)
5689 #define MLVDS_RESET_PATTERN_LO (0x14c5)
5690 #define P_MLVDS_RESET_PATTERN_LO (volatile uint32_t *)((0x14c5 << 2) + 0xff900000)
5691 #define mLVDS_reset_pattern 0 // Bit 47:16
5692 #define MLVDS_RESET_PATTERN_EXT (0x14c6)
5693 #define P_MLVDS_RESET_PATTERN_EXT (volatile uint32_t *)((0x14c6 << 2) + 0xff900000)
5694 #define mLVDS_reset_pattern_ext 0 // Bit 15:0
5695 #define MLVDS_CONFIG_HI (0x14c7)
5696 #define P_MLVDS_CONFIG_HI (volatile uint32_t *)((0x14c7 << 2) + 0xff900000)
5697 #define MLVDS_CONFIG_LO (0x14c8)
5698 #define P_MLVDS_CONFIG_LO (volatile uint32_t *)((0x14c8 << 2) + 0xff900000)
5699 #define mLVDS_reset_offset 29 // Bit 31:29
5700 #define mLVDS_reset_length 23 // Bit 28:23
5701 #define mLVDS_config_reserved 20 // Bit 22:20
5702 #define mLVDS_reset_start_bit12 19 // Bit 19
5703 #define mLVDS_data_write_toggle 18
5704 #define mLVDS_data_write_ini 17
5705 #define mLVDS_data_latch_1_toggle 16
5706 #define mLVDS_data_latch_1_ini 15
5707 #define mLVDS_data_latch_0_toggle 14
5708 #define mLVDS_data_latch_0_ini 13
5709 #define mLVDS_reset_1_select 12 // 0 - same as reset_0, 1 - 1 clock delay of reset_0
5710 #define mLVDS_reset_start 0 // Bit 11:0
5711 #define TCON_DOUBLE_CTL (0x14c9)
5712 #define P_TCON_DOUBLE_CTL (volatile uint32_t *)((0x14c9 << 2) + 0xff900000)
5713 #define tcon_double_ini 8 // Bit 7:0
5714 #define tcon_double_inv 0 // Bit 7:0
5715 #define TCON_PATTERN_HI (0x14ca)
5716 #define P_TCON_PATTERN_HI (volatile uint32_t *)((0x14ca << 2) + 0xff900000)
5717 #define TCON_PATTERN_LO (0x14cb)
5718 #define P_TCON_PATTERN_LO (volatile uint32_t *)((0x14cb << 2) + 0xff900000)
5719 #define tcon_pattern_loop_data 16 // Bit 15:0
5720 #define tcon_pattern_loop_start 12 // Bit 3:0
5721 #define tcon_pattern_loop_end 8 // Bit 3:0
5722 #define tcon_pattern_enable 0 // Bit 7:0
5723 #define TCON_CONTROL_HI (0x14cc)
5724 #define P_TCON_CONTROL_HI (volatile uint32_t *)((0x14cc << 2) + 0xff900000)
5725 #define TCON_CONTROL_LO (0x14cd)
5726 #define P_TCON_CONTROL_LO (volatile uint32_t *)((0x14cd << 2) + 0xff900000)
5727 #define tcon_pclk_enable 26 // Bit 5:0 (enable pclk on TCON channel 7 to 2)
5728 #define tcon_pclk_div 24 // Bit 1:0 (control phy clok divide 2,4,6,8)
5729 #define tcon_delay 0 // Bit 23:0 (3 bit for each channel)
5730 #define LVDS_BLANK_DATA_HI (0x14ce)
5731 #define P_LVDS_BLANK_DATA_HI (volatile uint32_t *)((0x14ce << 2) + 0xff900000)
5732 #define LVDS_BLANK_DATA_LO (0x14cf)
5733 #define P_LVDS_BLANK_DATA_LO (volatile uint32_t *)((0x14cf << 2) + 0xff900000)
5734 #define LVDS_blank_data_reserved 30 // 31:30
5735 #define LVDS_blank_data_r 20 // 29:20
5736 #define LVDS_blank_data_g 10 // 19:10
5737 #define LVDS_blank_data_b 0 // 9:0
5738 #define LVDS_PACK_CNTL_ADDR (0x14d0)
5739 #define P_LVDS_PACK_CNTL_ADDR (volatile uint32_t *)((0x14d0 << 2) + 0xff900000)
5740 #define LVDS_USE_TCON 7
5741 #define LVDS_DUAL 6
5742 #define PN_SWP 5
5743 #define LSB_FIRST 4
5744 #define LVDS_RESV 3
5745 #define ODD_EVEN_SWP 2
5746 #define LVDS_REPACK 0
5747 // New from M3 :
5748 // Bit 15:12 -- Enable OFFSET Double Generate(TOCN7-TCON4)
5749 // Bit 11:0 -- de_hs(old tcon) second offset_hs (new tcon)
5750 #define DE_HS_ADDR (0x14d1)
5751 #define P_DE_HS_ADDR (volatile uint32_t *)((0x14d1 << 2) + 0xff900000)
5752 // New from M3 :
5753 // Bit 15:12 -- Enable OFFSET Double Generate(TOCN3-TCON0)
5754 #define DE_HE_ADDR (0x14d2)
5755 #define P_DE_HE_ADDR (volatile uint32_t *)((0x14d2 << 2) + 0xff900000)
5756 #define DE_VS_ADDR (0x14d3)
5757 #define P_DE_VS_ADDR (volatile uint32_t *)((0x14d3 << 2) + 0xff900000)
5758 #define DE_VE_ADDR (0x14d4)
5759 #define P_DE_VE_ADDR (volatile uint32_t *)((0x14d4 << 2) + 0xff900000)
5760 #define HSYNC_HS_ADDR (0x14d5)
5761 #define P_HSYNC_HS_ADDR (volatile uint32_t *)((0x14d5 << 2) + 0xff900000)
5762 #define HSYNC_HE_ADDR (0x14d6)
5763 #define P_HSYNC_HE_ADDR (volatile uint32_t *)((0x14d6 << 2) + 0xff900000)
5764 #define HSYNC_VS_ADDR (0x14d7)
5765 #define P_HSYNC_VS_ADDR (volatile uint32_t *)((0x14d7 << 2) + 0xff900000)
5766 #define HSYNC_VE_ADDR (0x14d8)
5767 #define P_HSYNC_VE_ADDR (volatile uint32_t *)((0x14d8 << 2) + 0xff900000)
5768 #define VSYNC_HS_ADDR (0x14d9)
5769 #define P_VSYNC_HS_ADDR (volatile uint32_t *)((0x14d9 << 2) + 0xff900000)
5770 #define VSYNC_HE_ADDR (0x14da)
5771 #define P_VSYNC_HE_ADDR (volatile uint32_t *)((0x14da << 2) + 0xff900000)
5772 #define VSYNC_VS_ADDR (0x14db)
5773 #define P_VSYNC_VS_ADDR (volatile uint32_t *)((0x14db << 2) + 0xff900000)
5774 #define VSYNC_VE_ADDR (0x14dc)
5775 #define P_VSYNC_VE_ADDR (volatile uint32_t *)((0x14dc << 2) + 0xff900000)
5776 // bit 8 -- vfifo_mcu_enable
5777 // bit 7 -- halt_vs_de
5778 // bit 6 -- R8G8B8_format
5779 // bit 5 -- R6G6B6_format (round to 6 bits)
5780 // bit 4 -- R5G6B5_format
5781 // bit 3 -- dac_dith_sel
5782 // bit 2 -- lcd_mcu_enable_de -- ReadOnly
5783 // bit 1 -- lcd_mcu_enable_vsync -- ReadOnly
5784 // bit 0 -- lcd_mcu_enable
5785 #define LCD_MCU_CTL (0x14dd)
5786 #define P_LCD_MCU_CTL (volatile uint32_t *)((0x14dd << 2) + 0xff900000)
5787 // ReadOnly
5788 // R5G6B5 when R5G6B5_format
5789 // G8R8 when R8G8B8_format
5790 // G5R10 Other
5791 #define LCD_MCU_DATA_0 (0x14de)
5792 #define P_LCD_MCU_DATA_0 (volatile uint32_t *)((0x14de << 2) + 0xff900000)
5793 // ReadOnly
5794 // G8B8 when R8G8B8_format
5795 // G5B10 Other
5796 #define LCD_MCU_DATA_1 (0x14df)
5797 #define P_LCD_MCU_DATA_1 (volatile uint32_t *)((0x14df << 2) + 0xff900000)
5798 // LVDS
5799 #define LVDS_GEN_CNTL (0x14e0)
5800 #define P_LVDS_GEN_CNTL (volatile uint32_t *)((0x14e0 << 2) + 0xff900000)
5801 #define LVDS_PHY_CNTL0 (0x14e1)
5802 #define P_LVDS_PHY_CNTL0 (volatile uint32_t *)((0x14e1 << 2) + 0xff900000)
5803 #define LVDS_PHY_CNTL1 (0x14e2)
5804 #define P_LVDS_PHY_CNTL1 (volatile uint32_t *)((0x14e2 << 2) + 0xff900000)
5805 #define LVDS_PHY_CNTL2 (0x14e3)
5806 #define P_LVDS_PHY_CNTL2 (volatile uint32_t *)((0x14e3 << 2) + 0xff900000)
5807 #define LVDS_PHY_CNTL3 (0x14e4)
5808 #define P_LVDS_PHY_CNTL3 (volatile uint32_t *)((0x14e4 << 2) + 0xff900000)
5809 #define LVDS_PHY_CNTL4 (0x14e5)
5810 #define P_LVDS_PHY_CNTL4 (volatile uint32_t *)((0x14e5 << 2) + 0xff900000)
5811 #define LVDS_PHY_CNTL5 (0x14e6)
5812 #define P_LVDS_PHY_CNTL5 (volatile uint32_t *)((0x14e6 << 2) + 0xff900000)
5813 #define LVDS_SRG_TEST (0x14e8)
5814 #define P_LVDS_SRG_TEST (volatile uint32_t *)((0x14e8 << 2) + 0xff900000)
5815 #define LVDS_BIST_MUX0 (0x14e9)
5816 #define P_LVDS_BIST_MUX0 (volatile uint32_t *)((0x14e9 << 2) + 0xff900000)
5817 #define LVDS_BIST_MUX1 (0x14ea)
5818 #define P_LVDS_BIST_MUX1 (volatile uint32_t *)((0x14ea << 2) + 0xff900000)
5819 #define LVDS_BIST_FIXED0 (0x14eb)
5820 #define P_LVDS_BIST_FIXED0 (volatile uint32_t *)((0x14eb << 2) + 0xff900000)
5821 #define LVDS_BIST_FIXED1 (0x14ec)
5822 #define P_LVDS_BIST_FIXED1 (volatile uint32_t *)((0x14ec << 2) + 0xff900000)
5823 #define LVDS_BIST_CNTL0 (0x14ed)
5824 #define P_LVDS_BIST_CNTL0 (volatile uint32_t *)((0x14ed << 2) + 0xff900000)
5825 #define LVDS_CLKB_CLKA (0x14ee)
5826 #define P_LVDS_CLKB_CLKA (volatile uint32_t *)((0x14ee << 2) + 0xff900000)
5827 #define LVDS_PHY_CLK_CNTL (0x14ef)
5828 #define P_LVDS_PHY_CLK_CNTL (volatile uint32_t *)((0x14ef << 2) + 0xff900000)
5829 #define LVDS_SER_EN (0x14f0)
5830 #define P_LVDS_SER_EN (volatile uint32_t *)((0x14f0 << 2) + 0xff900000)
5831 #define LVDS_PHY_CNTL6 (0x14f1)
5832 #define P_LVDS_PHY_CNTL6 (volatile uint32_t *)((0x14f1 << 2) + 0xff900000)
5833 #define LVDS_PHY_CNTL7 (0x14f2)
5834 #define P_LVDS_PHY_CNTL7 (volatile uint32_t *)((0x14f2 << 2) + 0xff900000)
5835 #define LVDS_PHY_CNTL8 (0x14f3)
5836 #define P_LVDS_PHY_CNTL8 (volatile uint32_t *)((0x14f3 << 2) + 0xff900000)
5837 //`define MLVDS_CLK_CTL0_HI 8'hf4
5838 //`define MLVDS_CLK_CTL0_LO 8'hf5
5839 // `define mlvds_clk_pattern_reserved 31 // Bit 31
5840 // `define mpclk_dly 28 // Bit 2:0
5841 // `define mpclk_div 26 // Bit 1:0 (control phy clok divide 2,4,6,8)
5842 // `define use_mpclk 25 // Bit 0
5843 // `define mlvds_clk_half_delay 24 // Bit 0
5844 // `define mlvds_clk_pattern 0 // Bit 23:0
5845 //`define MLVDS_DUAL_GATE_WR_START 8'hf6
5846 // `define mlvds_dual_gate_wr_start 0 // Bit 12:0
5847 //`define MLVDS_DUAL_GATE_WR_END 8'hf7
5848 // `define mlvds_dual_gate_wr_end 0 // Bit 12:0
5849 //
5850 //`define MLVDS_DUAL_GATE_RD_START 8'hf8
5851 // `define mlvds_dual_gate_rd_start 0 // Bit 12:0
5852 //`define MLVDS_DUAL_GATE_RD_END 8'hf9
5853 // `define mlvds_dual_gate_rd_end 0 // Bit 12:0
5854 //`define MLVDS_SECOND_RESET_CTL 8'hfa
5855 // `define mLVDS_2nd_reset_start 0 // Bit 12:0
5856 //
5857 #define MLVDS_DUAL_GATE_CTL_HI (0x14fb)
5858 #define P_MLVDS_DUAL_GATE_CTL_HI (volatile uint32_t *)((0x14fb << 2) + 0xff900000)
5859 #define MLVDS_DUAL_GATE_CTL_LO (0x14fc)
5860 #define P_MLVDS_DUAL_GATE_CTL_LO (volatile uint32_t *)((0x14fc << 2) + 0xff900000)
5861 // `define mlvds_tcon_field_en 24 // Bit 7:0
5862 // `define mlvds_dual_gate_reserved 21 // Bit 2:0
5863 // `define mlvds_scan_mode_start_line_bit12 20 // Bit 0
5864 // `define mlvds_scan_mode_odd 16 // Bit 3:0
5865 // `define mlvds_scan_mode_even 12 // Bit 3:0
5866 // `define mlvds_scan_mode_start_line 0 // Bit 11:0
5867 //
5868 //`define MLVDS_RESET_CONFIG_HI 8'hfd
5869 //`define MLVDS_RESET_CONFIG_LO 8'hfe
5870 // `define mLVDS_reset_range_enable 31 // Bit 0
5871 // `define mLVDS_reset_range_inv 30 // Bit 0
5872 // `define mLVDS_reset_config_res1 29 // Bit 0
5873 // `define mLVDS_reset_range_line_0 16 // Bit 11:0
5874 // `define mLVDS_reset_config_res3 13 // Bit 2:0
5875 // `define mLVDS_reset_range_line_1 0 // Bit 11:0
5876 //===============================================================
5877 //LCD DRIVER BASE END
5878 //===============================================================
5879 //
5880 // Closing file: lcd_regs.h
5881 //
5882 //`define MAD_VCBUS_BASE 8'h17
5883 //
5884 // Reading file: mad_regs.h
5885 //
5886 //DEINTERLACE module start from 8'h90 end to 8'hff
5887 // -----------------------------------------------
5888 // CBUS_BASE: MAD_VCBUS_BASE = 0x17
5889 // -----------------------------------------------
5890 #define DI_PRE_CTRL (0x1700)
5891 #define P_DI_PRE_CTRL (volatile uint32_t *)((0x1700 << 2) + 0xff900000)
5892 // bit 31, cbus_pre_frame_rst
5893 // bit 30, cbus_pre_soft_rst
5894 // bit 29, pre_field_num
5895 // bit 27:26, mode_444c422
5896 // bit 25, di_cont_read_en
5897 // bit 24:23, mode_422c444
5898 // bit 22, mtn_after_nr
5899 // bit 21:16, pre_hold_fifo_lines
5900 // bit 15, nr_wr_by
5901 // bit 14, use_vdin_go_line
5902 // bit 13, di_prevdin_en
5903 // bit 12, di_pre_viu_link
5904 // bit 11, di_pre_repeat
5905 // bit 10, di_pre_drop_1st
5906 // bit 9, di_buf2_en
5907 // bit 8, di_chan2_en
5908 // bit 7, prenr_hist_en
5909 // bit 6, chan2_hist_en
5910 // bit 5, hist_check_en
5911 // bit 4, check_after_nr
5912 // bit 3, check222p_en
5913 // bit 2, check322p_en
5914 // bit 1, mtn_en
5915 // bit 0, nr_en
5916 #define DI_POST_CTRL (0x1701)
5917 #define P_DI_POST_CTRL (volatile uint32_t *)((0x1701 << 2) + 0xff900000)
5918 // bit 31, cbus_post_frame_rst
5919 // bit 30, cbus_post_soft_rst
5920 // bit 29, post_field_num
5921 // bit 21:16, post_hold_fifo_lines
5922 // bit 13, prepost_link
5923 // bit 12, di_post_viu_link
5924 // bit 11, di_post_repeat
5925 // bit 10, di_post_drop_1st
5926 // bit 9, mif0_to_vpp_en
5927 // bit 8, di_vpp_out_en
5928 // bit 7, di_wr_bk_en
5929 // bit 6, di_mux_en
5930 // bit 5, di_blend_en
5931 // bit 4, di_mtnp_read_en
5932 // bit 3, di_mtn_buf_en
5933 // bit 2, di_ei_en
5934 // bit 1, di_buf1_en
5935 // bit 0, di_buf0_en
5936 #define DI_POST_SIZE (0x1702)
5937 #define P_DI_POST_SIZE (volatile uint32_t *)((0x1702 << 2) + 0xff900000)
5938 //bit 28:16, vsize1post
5939 //bit 12:0, hsize1post
5940 #define DI_PRE_SIZE (0x1703)
5941 #define P_DI_PRE_SIZE (volatile uint32_t *)((0x1703 << 2) + 0xff900000)
5942 //bit 28:16, vsize1pre
5943 //bit 12:0, hsize1pre
5944 #define DI_EI_CTRL0 (0x1704)
5945 #define P_DI_EI_CTRL0 (volatile uint32_t *)((0x1704 << 2) + 0xff900000)
5946 //bit 23:16, ei0_filter[2:+] abs_diff_left>filter && ...right>filter && ...top>filter && ...bot>filter -> filter
5947 //bit 15:8, ei0_threshold[2:+]
5948 //bit 3, ei0_vertical
5949 //bit 2, ei0_bpscf2
5950 //bit 1, ei0_bpsfar1
5951 #define DI_EI_CTRL1 (0x1705)
5952 #define P_DI_EI_CTRL1 (volatile uint32_t *)((0x1705 << 2) + 0xff900000)
5953 //bit 31:24, ei0_diff
5954 //bit 23:16, ei0_angle45
5955 //bit 15:8, ei0_peak
5956 //bit 7:0, ei0_cross
5957 #define DI_EI_CTRL2 (0x1706)
5958 #define P_DI_EI_CTRL2 (volatile uint32_t *)((0x1706 << 2) + 0xff900000)
5959 //bit 31:24, ei0_close2
5960 //bit 23:16, ei0_close1
5961 //bit 15:8, ei0_far2
5962 //bit 7:0, ei0_far1
5963 #define DI_NR_CTRL0 (0x1707)
5964 #define P_DI_NR_CTRL0 (volatile uint32_t *)((0x1707 << 2) + 0xff900000)
5965 //bit 26, nr_cue_en
5966 //bit 25, nr2_en
5967 #define DI_NR_CTRL1 (0x1708)
5968 #define P_DI_NR_CTRL1 (volatile uint32_t *)((0x1708 << 2) + 0xff900000)
5969 //bit 31:30, mot_p1txtcore_mode
5970 //bit 29:24, mot_p1txtcore_clmt
5971 //bit 21:16, mot_p1txtcore_ylmt
5972 //bit 15:8, mot_p1txtcore_crate
5973 //bit 7:0, mot_p1txtcore_yrate
5974 #define DI_NR_CTRL2 (0x1709)
5975 #define P_DI_NR_CTRL2 (volatile uint32_t *)((0x1709 << 2) + 0xff900000)
5976 //bit 29:24, mot_curtxtcore_clmt
5977 //bit 21:16, mot_curtxtcore_ylmt
5978 //bit 15:8, mot_curtxtcore_crate
5979 //bit 7:0, mot_curtxtcore_yrate
5980 //`define DI_NR_CTRL3 8'h0a
5981 //no use
5982 //`define DI_MTN_CTRL 8'h0b
5983 //no use
5984 #define DI_CANVAS_URGENT0 (0x170a)
5985 #define P_DI_CANVAS_URGENT0 (volatile uint32_t *)((0x170a << 2) + 0xff900000)
5986 #define DI_CANVAS_URGENT1 (0x170b)
5987 #define P_DI_CANVAS_URGENT1 (volatile uint32_t *)((0x170b << 2) + 0xff900000)
5988 #define DI_MTN_CTRL1 (0x170c)
5989 #define P_DI_MTN_CTRL1 (volatile uint32_t *)((0x170c << 2) + 0xff900000)
5990 //bit 13 , me enable
5991 //bit 12 , me autoenable
5992 //bit 11:8, mtn_paramtnthd
5993 //bit 7:0, mtn_parafltthd
5994 #define DI_BLEND_CTRL (0x170d)
5995 #define P_DI_BLEND_CTRL (volatile uint32_t *)((0x170d << 2) + 0xff900000)
5996 //bit 31, blend_1_en
5997 //bit 30, blend_mtn_lpf
5998 //bit 28, post_mb_en
5999 //bit 27, blend_mtn3p_max
6000 //bit 26, blend_mtn3p_min
6001 //bit 25, blend_mtn3p_ave
6002 //bit 24, blend_mtn3p_maxtb
6003 //bit 23, blend_mtn_flt_en
6004 //bit 22, blend_data_flt_en
6005 //bit 21:20, blend_top_mode
6006 //bit 19, blend_reg3_enable
6007 //bit 18, blend_reg2_enable
6008 //bit 17, blend_reg1_enable
6009 //bit 16, blend_reg0_enable
6010 //bit 15:14, blend_reg3_mode
6011 //bit 13:12, blend_reg2_mode
6012 //bit 11:10, blend_reg1_mode
6013 //bit 9:8, blend_reg0_mode
6014 //bit 7:0, kdeint
6015 //`define DI_BLEND_CTRL1 8'h0e
6016 //no use
6017 #define DI_CANVAS_URGENT2 (0x170e)
6018 #define P_DI_CANVAS_URGENT2 (volatile uint32_t *)((0x170e << 2) + 0xff900000)
6019 //`define DI_BLEND_CTRL2 8'h0f
6020 //no use
6021 #define DI_ARB_CTRL (0x170f)
6022 #define P_DI_ARB_CTRL (volatile uint32_t *)((0x170f << 2) + 0xff900000)
6023 //bit 31:26, di_arb_thd1
6024 //bit 25:20, di_arb_thd0
6025 //bit 19, di_arb_tid_mode
6026 //bit 18, di_arb_arb_mode
6027 //bit 17, di_arb_acq_en
6028 //bit 16, di_arb_disable_clk
6029 //bit 15:0, di_arb_req_en
6030 #define DI_BLEND_REG0_X (0x1710)
6031 #define P_DI_BLEND_REG0_X (volatile uint32_t *)((0x1710 << 2) + 0xff900000)
6032 //bit 27:16, blend_reg0_startx
6033 //bit 11:0, blend_reg0_endx
6034 #define DI_BLEND_REG0_Y (0x1711)
6035 #define P_DI_BLEND_REG0_Y (volatile uint32_t *)((0x1711 << 2) + 0xff900000)
6036 #define DI_BLEND_REG1_X (0x1712)
6037 #define P_DI_BLEND_REG1_X (volatile uint32_t *)((0x1712 << 2) + 0xff900000)
6038 #define DI_BLEND_REG1_Y (0x1713)
6039 #define P_DI_BLEND_REG1_Y (volatile uint32_t *)((0x1713 << 2) + 0xff900000)
6040 #define DI_BLEND_REG2_X (0x1714)
6041 #define P_DI_BLEND_REG2_X (volatile uint32_t *)((0x1714 << 2) + 0xff900000)
6042 #define DI_BLEND_REG2_Y (0x1715)
6043 #define P_DI_BLEND_REG2_Y (volatile uint32_t *)((0x1715 << 2) + 0xff900000)
6044 #define DI_BLEND_REG3_X (0x1716)
6045 #define P_DI_BLEND_REG3_X (volatile uint32_t *)((0x1716 << 2) + 0xff900000)
6046 #define DI_BLEND_REG3_Y (0x1717)
6047 #define P_DI_BLEND_REG3_Y (volatile uint32_t *)((0x1717 << 2) + 0xff900000)
6048 #define DI_CLKG_CTRL (0x1718)
6049 #define P_DI_CLKG_CTRL (volatile uint32_t *)((0x1718 << 2) + 0xff900000)
6050 //bit 31:24, pre_gclk_ctrl no clk gate control. if ==1, module clk is not gated (always on). [3] for pulldown,[2] for mtn_1,[1] for mtn_0,[0] for nr
6051 //bit 23:16, post_gclk_ctrl no clk gate control. [4] for ei_1, [3] for ei_0,[2] for ei_top, [1] for blend_1, [0] for blend_0
6052 //bit 1, di_gate_all clk shut down. if ==1 , all di clock shut down
6053 //bit 0, di_no_clk_gate no clk gate control. if di_gated_all==0 and di_no_clk_gate ==1, all di clock is always working.
6054 #define DI_EI_CTRL3 (0x1719)
6055 #define P_DI_EI_CTRL3 (volatile uint32_t *)((0x1719 << 2) + 0xff900000)
6056 //bit 31, reg_ei_1
6057 //bit 30, reg_demon_en
6058 //bit 26:24, reg_demon_mux
6059 //bit 23:20, reg_right_win
6060 //bit 19:16, reg_left_win
6061 //bit 7:4, reg_ei_sadm_quatize_margin
6062 //bit 1:0, reg_ei_sad_relative_mode
6063 #define DI_EI_CTRL4 (0x171a)
6064 #define P_DI_EI_CTRL4 (volatile uint32_t *)((0x171a << 2) + 0xff900000)
6065 //bit 29, reg_ei_caldrt_ambliike2_biasvertical
6066 //bit 28:24, reg_ei_caldrt_addxla2list_drtmax
6067 //bit 22:20, reg_ei_caldrt_addxla2list_signm0th
6068 //bit 19, reg_ei_caldrt_addxla2list_mode
6069 //bit 18:16, reg_ei_signm_sad_cor_rate
6070 //bit 15:12, reg_ei_signm_sadi_cor_rate
6071 //bit 11:6, reg_ei_signm_sadi_cor_ofst
6072 //bit 5:0, reg_ei_signm_sad_ofst
6073 #define DI_EI_CTRL5 (0x171b)
6074 #define P_DI_EI_CTRL5 (volatile uint32_t *)((0x171b << 2) + 0xff900000)
6075 //bit 30:28, reg_ei_caldrt_cnflcctchk_frcverthrd
6076 //bit 26:24, reg_ei_caldrt_cnflctchk_mg
6077 //bit 23:22, reg_ei_caldrt_cnflctchk_ws
6078 //bit 21, reg_ei_caldrt_cnflctchk_en
6079 //bit 20, reg_ei_caldrt_verfrc_final_en
6080 //bit 19, reg_ei_caldrt_verfrc_retimflt_en
6081 //bit 18:16, reg_ei_caldrt_verftc_eithratemth
6082 //bit 15, reg_ei_caldrt_verfrc_retiming_en
6083 //bit 14:12, reg_ei_caldrt_verfrc_bothratemth
6084 //bit 11:9, reg_ei_caldrt_ver_thrd
6085 //bit 8:4, reg_ei_caldrt_addxla2list_drtmin
6086 //bit 3:0, reg_ei_caldrt_addxla2list_drtlimit
6087 #define DI_EI_CTRL6 (0x171c)
6088 #define P_DI_EI_CTRL6 (volatile uint32_t *)((0x171c << 2) + 0xff900000)
6089 //bit 31:24, reg_ei_caldrt_abext_sad12thhig
6090 //bit 23:16, reg_ei_caldrt_abext_sad00thlow
6091 //bit 15:8, reg_ei_caldrt_abext_sad12thlow
6092 //bit 6:4, reg_ei_caldrt_abext_ratemth
6093 //bit 2:0, reg_ei_caldrt_abext_drtthrd
6094 #define DI_EI_CTRL7 (0x171d)
6095 #define P_DI_EI_CTRL7 (volatile uint32_t *)((0x171d << 2) + 0xff900000)
6096 //bit 29, reg_ei_caldrt_xlanopeak_codien
6097 //bit 28:24, reg_ei_caldrt_xlanopeak_drtmax
6098 //bit 23, reg_ei_caldrt_xlanopeak_en
6099 //bit 28:24, reg_ei_caldrt_abext_monotrnd_alpha
6100 //bit 28:24, reg_ei_caldrt_abext_mononum12_thrd
6101 //bit 28:24, reg_ei_caldrt_abext_mononum00_thrd
6102 //bit 28:24, reg_ei_caldrt_abext_sad00rate
6103 //bit 28:24, reg_ei_caldrt_abext_sad12rate
6104 //bit 28:24, reg_ei_caldrt_abext_sad00thhig
6105 #define DI_EI_CTRL8 (0x171e)
6106 #define P_DI_EI_CTRL8 (volatile uint32_t *)((0x171e << 2) + 0xff900000)
6107 //bit 30:28, reg_ei_assign_headtail_magin
6108 //bit 26:24, reg_ei_retime_lastcurpncnfltchk_mode
6109 //bit 22:21, reg_ei_retime_lastcurpncnfltchk_drtth
6110 //bit 20, reg_ei_caldrt_histchk_cnfid
6111 //bit 19:16, reg_ei_caldrt_histchk_thrd
6112 //bit 15, reg_ei_caldrt_histchk_abext
6113 //bit 14, reg_ei_caldrt_histchk_npen
6114 //bit 13:11, reg_ei_caldrt_amblike2_drtmg
6115 //bit 10:8, reg_ei_caldrt_amblike2_valmg
6116 //bit 7:4, reg_ei_caldrt_amblike2_alpha
6117 //bit 3:0, reg_ei_caldrt_amblike2_drtth
6118 #define DI_EI_CTRL9 (0x171f)
6119 #define P_DI_EI_CTRL9 (volatile uint32_t *)((0x171f << 2) + 0xff900000)
6120 //bit 31:28, reg_ei_caldrt_hcnfcheck_frcvert_xla_th3
6121 //bit 27, reg_ei_caldrt_hcnfcheck_frcvert_xla_en
6122 //bit 26:24, reg_ei_caldrt_conf_drtth
6123 //bit 23:20, reg_ei_caldrt_conf_absdrtth
6124 //bit 19:18, reg_ei_caldrt_abcheck_mode1
6125 //bit 17:16, reg_ei_caldrt_abcheck_mode0
6126 //bit 15:12, reg_ei_caldrt_abcheck_drth1
6127 //bit 11:8, reg_ei_caldrt_abcheck_drth0
6128 //bit 6:4, reg_ei_caldrt_abpnchk1_th
6129 //bit 1, reg_ei_caldrt_abpnchk1_en
6130 //bit 0, reg_ei_caldrt_abpnchk0_en
6131 // DEINTERLACE mode check.
6132 #define DI_MC_REG0_X (0x1720)
6133 #define P_DI_MC_REG0_X (volatile uint32_t *)((0x1720 << 2) + 0xff900000)
6134 //bit 27:16, mc_reg0_start_x
6135 //bit 11:0, mc_reg0_end_x
6136 #define DI_MC_REG0_Y (0x1721)
6137 #define P_DI_MC_REG0_Y (volatile uint32_t *)((0x1721 << 2) + 0xff900000)
6138 #define DI_MC_REG1_X (0x1722)
6139 #define P_DI_MC_REG1_X (volatile uint32_t *)((0x1722 << 2) + 0xff900000)
6140 #define DI_MC_REG1_Y (0x1723)
6141 #define P_DI_MC_REG1_Y (volatile uint32_t *)((0x1723 << 2) + 0xff900000)
6142 #define DI_MC_REG2_X (0x1724)
6143 #define P_DI_MC_REG2_X (volatile uint32_t *)((0x1724 << 2) + 0xff900000)
6144 #define DI_MC_REG2_Y (0x1725)
6145 #define P_DI_MC_REG2_Y (volatile uint32_t *)((0x1725 << 2) + 0xff900000)
6146 #define DI_MC_REG3_X (0x1726)
6147 #define P_DI_MC_REG3_X (volatile uint32_t *)((0x1726 << 2) + 0xff900000)
6148 #define DI_MC_REG3_Y (0x1727)
6149 #define P_DI_MC_REG3_Y (volatile uint32_t *)((0x1727 << 2) + 0xff900000)
6150 #define DI_MC_REG4_X (0x1728)
6151 #define P_DI_MC_REG4_X (volatile uint32_t *)((0x1728 << 2) + 0xff900000)
6152 #define DI_MC_REG4_Y (0x1729)
6153 #define P_DI_MC_REG4_Y (volatile uint32_t *)((0x1729 << 2) + 0xff900000)
6154 #define DI_MC_32LVL0 (0x172a)
6155 #define P_DI_MC_32LVL0 (volatile uint32_t *)((0x172a << 2) + 0xff900000)
6156 //bit 31:24, mc_reg2_32lvl
6157 //bit 23:16, mc_reg1_32lvl
6158 //bit 15:8, mc_reg0_32lvl
6159 //bit 7:0, field_32lvl
6160 #define DI_MC_32LVL1 (0x172b)
6161 #define P_DI_MC_32LVL1 (volatile uint32_t *)((0x172b << 2) + 0xff900000)
6162 //bit 15:8, mc_reg3_32lvl
6163 //bit 7:0, mc_reg4_32lvl
6164 #define DI_MC_22LVL0 (0x172c)
6165 #define P_DI_MC_22LVL0 (volatile uint32_t *)((0x172c << 2) + 0xff900000)
6166 //bit 31:16, mc_reg0_22lvl
6167 //bit 15:0, field_22lvl
6168 #define DI_MC_22LVL1 (0x172d)
6169 #define P_DI_MC_22LVL1 (volatile uint32_t *)((0x172d << 2) + 0xff900000)
6170 //bit 31:16, mc_reg2_22lvl
6171 //bit 15:0, mc_reg1_22lvl
6172 #define DI_MC_22LVL2 (0x172e)
6173 #define P_DI_MC_22LVL2 (volatile uint32_t *)((0x172e << 2) + 0xff900000)
6174 //bit 31:16, mc_reg4_22lvl
6175 //bit 15:0, mc_reg3_22lvl
6176 #define DI_MC_CTRL (0x172f)
6177 #define P_DI_MC_CTRL (volatile uint32_t *)((0x172f << 2) + 0xff900000)
6178 //bit 4, mc_reg4_en
6179 //bit 3, mc_reg3_en
6180 //bit 2, mc_reg2_en
6181 //bit 1, mc_reg1_en
6182 //bit 0, mc_reg0_en
6183 #define DI_INTR_CTRL (0x1730)
6184 #define P_DI_INTR_CTRL (volatile uint32_t *)((0x1730 << 2) + 0xff900000)
6185 #define DI_INFO_ADDR (0x1731)
6186 #define P_DI_INFO_ADDR (volatile uint32_t *)((0x1731 << 2) + 0xff900000)
6187 #define DI_INFO_DATA (0x1732)
6188 #define P_DI_INFO_DATA (volatile uint32_t *)((0x1732 << 2) + 0xff900000)
6189 #define DI_PRE_HOLD (0x1733)
6190 #define P_DI_PRE_HOLD (volatile uint32_t *)((0x1733 << 2) + 0xff900000)
6191 //// DET 3D REG DEFINE BEGIN ////
6192 //// 8'h34~8'h3f
6193 // `define DET3D_MOTN_CFG 8'h34
6194 // //Bit 16, reg_det3d_intr_en Det3d interrupt enable
6195 // //Bit 9:8, reg_Det3D_Motion_Mode U2 Different mode for Motion Calculation of Luma and Chroma:
6196 // // 0: MotY, 1: (2*MotY + (MotU + MotV))/4; 2: Max(MotY, MotU,MotV); 3:Max(MotY, (MotU+MotV)/2)
6197 // //Bit 7:4, reg_Det3D_Motion_Core_Rate U4 K Rate to Edge (HV) details for coring of Motion Calculations, normalized to 32
6198 // //Bit 3:0, reg_Det3D_Motion_Core_Thrd U4 2X: static coring value for Motion Detection.
6199 //
6200 // `define DET3D_CB_CFG 8'h35
6201 // //Bit 7:4, reg_Det3D_ChessBd_NHV_ofst U4, Noise immune offset for NON-Horizotnal or vertical combing detection.
6202 // //Bit 3:0, reg_Det3D_ChessBd_HV_ofst U4, Noise immune offset for Horizotnal or vertical combing detection.
6203 //
6204 // `define DET3D_SPLT_CFG 8'h36
6205 // //Bit 7:4, reg_Det3D_SplitValid_ratio U4, Ratio between max_value and the avg_value of the edge mapping for split line valid detection.
6206 // // The smaller of this value, the easier of the split line detected.
6207 // //Bit 3:0, reg_Det3D_AvgIdx_ratio U4, Ratio to the avg_value of the edge mapping for split line position estimation.
6208 // // The smaller of this value, the more samples will be added to the estimation.
6209 //
6210 // `define DET3D_HV_MUTE 8'h37
6211 // //Bit 23:20, reg_Det3D_Edge_Ver_Mute U4 X2: Horizontal pixels to be mute from H/V Edge calculation Top and Bottom border part.
6212 // //Bit 19:16, reg_Det3D_Edge_Hor_Mute U4 X2: Horizontal pixels to be mute from H/V Edge calculation Left and right border part.
6213 // //Bit 15:12, reg_Det3D_ChessBd_Ver_Mute U4 X2: Horizontal pixels to be mute from ChessBoard statistics calculation in middle part
6214 // //Bit 11:8, reg_Det3D_ChessBd_Hor_Mute U4 X2: Horizontal pixels to be mute from ChessBoard statistics calculation in middle part
6215 // //Bit 7:4, reg_Det3D_STA8X8_Ver_Mute U4 1X: Vertical pixels to be mute from 8x8 statistics calculation in each block.
6216 // //Bit 3:0, reg_Det3D_STA8X8_Hor_Mute U4 1X: Horizontal pixels to be mute from 8x8 statistics calculation in each block.
6217 //
6218 // `define DET3D_MAT_STA_P1M1 8'h38
6219 // //Bit 31:24, reg_Det3D_STA8X8_P1_K0_R8 U8 SAD to SAI ratio to decide P1, normalized to 256 (0.8)
6220 // //Bit 23:16, reg_Det3D_STA8X8_P1_K1_R7 U8 SAD to ENG ratio to decide P1, normalized to 128 (0.5)
6221 // //Bit 15:8, reg_Det3D_STA8X8_M1_K0_R6 U8 SAD to SAI ratio to decide M1, normalized to 64 (1.1)
6222 // //Bit 7:0, reg_Det3D_STA8X8_M1_K1_R6 U8 SAD to ENG ratio to decide M1, normalized to 64 (0.8)
6223 //
6224 // `define DET3D_MAT_STA_P1TH 8'h39
6225 // //Bit 23:16, reg_Det3D_STAYUV_P1_TH_L4 U8 SAD to ENG Thrd offset to decide P1, X16 (100)
6226 // //Bit 15:8, reg_Det3D_STAEDG_P1_TH_L4 U8 SAD to ENG Thrd offset to decide P1, X16 (80)
6227 // //Bit 7:0, reg_Det3D_STAMOT_P1_TH_L4 U8 SAD to ENG Thrd offset to decide P1, X16 (48)
6228 //
6229 // `define DET3D_MAT_STA_M1TH 8'h3a
6230 // //Bit 23:16, reg_Det3D_STAYUV_M1_TH_L4 U8 SAD to ENG Thrd offset to decide M1, X16 (100)
6231 // //Bit 15:8, reg_Det3D_STAEDG_M1_TH_L4 U8 SAD to ENG Thrd offset to decide M1, X16 (80)
6232 // //Bit 7:0, reg_Det3D_STAMOT_M1_TH_L4 U8 SAD to ENG Thrd offset to decide M1, X16 (64)
6233 //
6234 // `define DET3D_MAT_STA_RSFT 8'h3b
6235 // //Bit 5:4, reg_Det3D_STAYUV_RSHFT U2 YUV statistics SAD and SAI calculation result right shift bits to accommodate the 12bits clipping:
6236 // // 0: mainly for images <=720x480: 1: mainly for images <=1366x768: 2: mainly for images <=1920X1080: 2; 3: other higher resolutions
6237 // //Bit 3:2, reg_Det3D_STAEDG_RSHFT U2 Horizontal and Vertical Edge Statistics SAD and SAI calculation result right shift bits to accommodate the 12bits clipping:
6238 // // 0: mainly for images <=720x480: 1: mainly for images <=1366x768: 2: mainly for images <=1920X1080: 2; 3: other higher resolutions
6239 // //Bit 1:0, reg_Det3D_STAMOT_RSHFT U2 Motion SAD and SAI calculation result right shift bits to accommodate the 12bits clipping:
6240 // // 0: mainly for images <=720x480: 1: mainly for images <=1366x768: 2: mainly for images <=1920X1080: 2; 3: other higher resolutions
6241 //
6242 // `define DET3D_MAT_SYMTC_TH 8'h3c
6243 // //Bit 31:24, reg_Det3D_STALUM_symtc_Th U8 threshold to decide if the Luma statistics is TB or LR symmetric.
6244 // //Bit 23:16, reg_Det3D_STACHR_symtc_Th U8 threshold to decide if the Chroma (UV) statistics is TB or LR symmetric.
6245 // //Bit 15:8, reg_Det3D_STAEDG_symtc_Th U8 threshold to decide if the Horizontal and Vertical Edge statistics is TB or LR symmetric.
6246 // //Bit 7:0, reg_Det3D_STAMOT_symtc_Th U8 threshold to decide if the Motion statistics is TB or LR symmetric.
6247 //
6248 // `define DET3D_RO_DET_CB_HOR 8'h3d
6249 // //Bit 31:16, RO_Det3D_ChessBd_NHor_value U16 X64: number of Pixels of Horizontally Surely NOT matching Chessboard pattern.
6250 // //Bit 15:0, RO_Det3D_ChessBd_Hor_value U16 X64: number of Pixels of Horizontally Surely matching Chessboard pattern.
6251 //
6252 // `define DET3D_RO_DET_CB_VER 8'h3e
6253 // //Bit 31:16, RO_Det3D_ChessBd_NVer_value U16 X64: number of Pixels of Vertically Surely NOT matching Chessboard pattern.
6254 // //Bit 15:0, RO_Det3D_ChessBd_Ver_value U16 X64: number of Pixels of Vertically Surely matching Chessboard pattern.
6255 //
6256 // `define DET3D_RO_SPLT_HT 8'h3f
6257 // //Bit 24, RO_Det3D_Split_HT_valid U1 horizontal LR split border detected valid signal for top half picture
6258 // //Bit 20:16, RO_Det3D_Split_HT_pxnum U5 number of pixels included for the LR split position estimation for top half picture
6259 // //Bit 9:0, RO_Det3D_Split_HT_idxX4 S10 X4: horizontal pixel shifts of LR split position to the (ColMax/2) for top half picture
6260 //
6261 // //// DET 3D REG DEFINE END ////
6262 #define DI_MTN_1_CTRL1 (0x1740)
6263 #define P_DI_MTN_1_CTRL1 (volatile uint32_t *)((0x1740 << 2) + 0xff900000)
6264 //bit 31, mtn_1_en
6265 //bit 30, mtn_init
6266 //bit 29, di2nr_txt_en
6267 //bit 28, reserved
6268 //bit 27:24, mtn_def
6269 //bit 23:16, mtn_adp_yc
6270 //bit 15:8, mtn_adp_2c
6271 //bit 7:0, mtn_adp_2y
6272 #define DI_MTN_1_CTRL2 (0x1741)
6273 #define P_DI_MTN_1_CTRL2 (volatile uint32_t *)((0x1741 << 2) + 0xff900000)
6274 //bit 31:24, mtn_ykinter
6275 //bit 23:16, mtn_ckinter
6276 //bit 15:8, mtn_ykintra
6277 //bit 7:0, mtn_ckintra
6278 #define DI_MTN_1_CTRL3 (0x1742)
6279 #define P_DI_MTN_1_CTRL3 (volatile uint32_t *)((0x1742 << 2) + 0xff900000)
6280 //bit 31:24, mtn_tyrate
6281 //bit 23:16, mtn_tcrate
6282 //bit 15: 8, mtn_mxcmby
6283 //bit 7: 0, mtn_mxcmbc
6284 #define DI_MTN_1_CTRL4 (0x1743)
6285 #define P_DI_MTN_1_CTRL4 (volatile uint32_t *)((0x1743 << 2) + 0xff900000)
6286 //bit 31:24, mtn_tcorey
6287 //bit 23:16, mtn_tcorec
6288 //bit 15: 8, mtn_minth
6289 //bit 7: 0, mtn_maxth
6290 #define DI_MTN_1_CTRL5 (0x1744)
6291 #define P_DI_MTN_1_CTRL5 (volatile uint32_t *)((0x1744 << 2) + 0xff900000)
6292 //bit 31:28, mtn_m1b_extnd
6293 //bit 27:24, mtn_m1b_errod
6294 //bit 21:20, mtn_mot_txt_mode
6295 //bit 19:18, mtn_replace_cbyy
6296 //bit 17:16, mtn_replace_ybyc
6297 //bit 15: 8, mtn_core_ykinter
6298 //bit 7: 0, mtn_core_ckinter
6299 //// NR2 REG DEFINE BEGIN////
6300 #define NR2_MET_NM_CTRL (0x1745)
6301 #define P_NR2_MET_NM_CTRL (volatile uint32_t *)((0x1745 << 2) + 0xff900000)
6302 //Bit 28, reg_NM_reset Reset to the status of the Loop filter.
6303 //Bit 27:24, reg_NM_calc_length Length mode of the Noise measurement sample number for statistics.
6304 // 0: 256 samples; 1: 512 samples; 2: 1024 samples; 隆颅X: 2^(8+x) samples
6305 //Bit 23:20, reg_NM_inc_step Loop filter input gain increase step.
6306 //Bit 19:16, reg_NM_dec_step Loop filter input gain decrease step.
6307 //Bit 15:8, reg_NM_YHPmot_thrd Luma channel HP portion motion for condition of pixels included in Luma Noise measurement.
6308 //Bit 7:0, reg_NM_CHPmot_thrd Chroma channel HP portion motion for condition of pixels included in Chroma Noise measurement.
6309 #define NR2_MET_NM_YCTRL (0x1746)
6310 #define P_NR2_MET_NM_YCTRL (volatile uint32_t *)((0x1746 << 2) + 0xff900000)
6311 //Bit 31:28, reg_NM_YPLL_target Target rate of NM_Ynoise_thrd to mean of the Luma Noise
6312 //Bit 27:24, reg_NM_YLPmot_thrd Luma channel LP portion motion for condition of pixels included in Luma Noise measurement.
6313 //Bit 23:16, reg_NM_YHPmot_thrd_min Minimum threshold for Luma channel HP portion motion to decide whether the pixel will be included in Luma noise measurement.
6314 //Bit 15:8, reg_NM_YHPmot_thrd_max Maximum threshold for Luma channel HP portion motion to decide whether the pixel will be included in Luma noise measurement.
6315 //Bit 7:0, reg_NM_Ylock_rate Rate to decide whether the Luma noise measurement is lock or not.
6316 #define NR2_MET_NM_CCTRL (0x1747)
6317 #define P_NR2_MET_NM_CCTRL (volatile uint32_t *)((0x1747 << 2) + 0xff900000)
6318 //Bit 31:28, reg_NM_CPLL_target Target rate of NM_Cnoise_thrd to mean of the Chroma Noise
6319 //Bit 27:24, reg_NM_CLPmot_thrd Chroma channel LP portion motion for condition of pixels included in Chroma Noise measurement.
6320 //Bit 23:16, reg_NM_CHPmot_thrd_min Minimum threshold for Chroma channel HP portion motion to decide whether the pixel will be included in Chroma noise measurement.
6321 //Bit 15:8, reg_NM_CHPmot_thrd_max Maximum threshold for Chroma channel HP portion motion to decide whether the pixel will be included in Chroma noise measurement.
6322 //Bit 7:0, reg_NM_Clock_rate Rate to decide whether the Chroma noise measurement is lock or not;
6323 #define NR2_MET_NM_TNR (0x1748)
6324 #define P_NR2_MET_NM_TNR (volatile uint32_t *)((0x1748 << 2) + 0xff900000)
6325 //Bit 25, ro_NM_TNR_Ylock Read-only register to tell ifLuma channel noise measurement is locked or not.
6326 //Bit 24, ro_NM_TNR_Clock Read-only register to tell if Chroma channel noise measurement is locked or not.
6327 //Bit 23:12, ro_NM_TNR_Ylevel Read-only register to give Luma channel noise level. It was 16x of pixel difference in 8 bits of YHPmot.
6328 //Bit 11:0, ro_NM_TNR_Clevel Read-only register to give Chroma channel noise level. It was 16x of pixel difference in 8 bits of CHPmot.
6329 #define NR2_MET_NMFRM_TNR_YLEV (0x1749)
6330 #define P_NR2_MET_NMFRM_TNR_YLEV (volatile uint32_t *)((0x1749 << 2) + 0xff900000)
6331 //Bit 28:0, ro_NMFrm_TNR_Ylevel Frame based Read-only register to give Luma channel noise level within one frame/field.
6332 #define NR2_MET_NMFRM_TNR_YCNT (0x174a)
6333 #define P_NR2_MET_NMFRM_TNR_YCNT (volatile uint32_t *)((0x174a << 2) + 0xff900000)
6334 //Bit 23:0, ro_NMFrm_TNR_Ycount Number ofLuma channel pixels included in Frame/Field based noise level measurement.
6335 #define NR2_MET_NMFRM_TNR_CLEV (0x174b)
6336 #define P_NR2_MET_NMFRM_TNR_CLEV (volatile uint32_t *)((0x174b << 2) + 0xff900000)
6337 //Bit 28:0, ro_NMFrm_TNR_Clevel Frame based Read-only register to give Chroma channel noise level within one frame/field.
6338 #define NR2_MET_NMFRM_TNR_CCNT (0x174c)
6339 #define P_NR2_MET_NMFRM_TNR_CCNT (volatile uint32_t *)((0x174c << 2) + 0xff900000)
6340 //Bit 23:0, ro_NMFrm_TNR_Ccount Number of Chroma channel pixels included in Frame/Field based noise level measurement.
6341 #define NR2_3DEN_MODE (0x174d)
6342 #define P_NR2_3DEN_MODE (volatile uint32_t *)((0x174d << 2) + 0xff900000)
6343 //Bit 6:4, Blend_3dnr_en_r
6344 //Bit 2:0, Blend_3dnr_en_l
6345 // `define NR2_IIR_CTRL 8'h4e
6346 // //Bit 15:14, reg_LP_IIR_8bit_mode LP IIR membitwidth mode:0: 10bits will be store in memory;1: 9bits will be store in memory;
6347 // // 2: 8bits will be store in memory;3: 7bits will be store in memory;
6348 // //Bit 13:12, reg_LP_IIR_mute_mode Mode for the LP IIR mute,
6349 // //Bit 11:8, reg_LP_IIR_mute_thrd Threshold of LP IIR mute to avoid ghost:
6350 // //Bit 7:6, reg_HP_IIR_8bit_mode IIR membitwidth mode:0: 10bits will be store in memory;1: 9bits will be store in memory;
6351 // // 2: 8bits will be store in memory;3: 7bits will be store in memory;
6352 // //Bit 5:4, reg_HP_IIR_mute_mode Mode for theLP IIR mute
6353 // //Bit 3:0, reg_HP_IIR_mute_thrd Threshold of HP IIR mute to avoid ghost
6354 // //
6355 #define NR2_SW_EN (0x174f)
6356 #define P_NR2_SW_EN (volatile uint32_t *)((0x174f << 2) + 0xff900000)
6357 //Bit 17:8, Clk_gate_ctrl
6358 //Bit 7, Cfr_enable
6359 //Bit 5, Det3d_en
6360 //Bit 4, Nr2_proc_en
6361 //Bit 0, Nr2_sw_en
6362 #define NR2_FRM_SIZE (0x1750)
6363 #define P_NR2_FRM_SIZE (volatile uint32_t *)((0x1750 << 2) + 0xff900000)
6364 //Bit 27:16, Frm_heigh Frame/field height
6365 //Bit 11: 0, Frm_width Frame/field width
6366 // `define NR2_SNR_SAD_CFG 8'h51
6367 // //Bit 12, reg_MATNR_SNR_SAD_CenRPL U1, Enable signal for Current pixel position SAD to be replaced by SAD_min.0: do not replace Current pixel position SAD by SAD_min;1: do replacements
6368 // //Bit 11:8, reg_MATNR_SNR_SAD_coring Coring value of the intra-frame SAD. sum = (sum - reg_MATNR_SNR_SAD_coring);sum = (sum<0) ? 0: (sum>255)? 255: sum;
6369 // //Bit 6:5, reg_MATNR_SNR_SAD_WinMod Unsigned, Intra-frame SAD matching window mode:0: 1x1; 1: [1 1 1] 2: [1 2 1]; 3: [1 2 2 2 1];
6370 // //Bit 4:0, Sad_coef_num Sad coeffient
6371 //
6372 // `define NR2_MATNR_SNR_OS 8'h52
6373 // //Bit 7:4, reg_MATNR_SNR_COS SNR Filter overshoot control margin for UV channel (X2 to u10 scale)
6374 // //Bit 3:0, reg_MATNR_SNR_YOS SNR Filter overshoot control margin for luma channel (X2 to u10 scale)
6375 //
6376 // `define NR2_MATNR_SNR_NRM_CFG 8'h53
6377 // //Bit 23:16, reg_MATNR_SNR_NRM_ofst Edge based SNR boosting normalization offset to SAD_max ;
6378 // //Bit 15:8, reg_MATNR_SNR_NRM_max Edge based SNR boosting normalization Max value
6379 // //Bit 7:0, reg_MATNR_SNR_NRM_min Edge based SNR boosting normalization Min value
6380 //
6381 // `define NR2_MATNR_SNR_NRM_GAIN 8'h54
6382 // //Bit 15:8, reg_MATNR_SNR_NRM_Cgain Edge based SNR boosting normalization Gain for Chrm channel (norm 32 as 1)
6383 // //Bit 7:0, reg_MATNR_SNR_NRM_Ygain Edge based SNR boosting normalization Gain for Luma channel (norm 32 as 1)
6384 //
6385 // `define NR2_MATNR_SNR_LPF_CFG 8'h55
6386 // //Bit 23:16,reg_MATNR_SNRLPF_SADmaxTH U8, Threshold to SADmax to use TNRLPF to replace SNRLPF. i.e.if (SAD_max<reg_MATNR_SNRLPF_SADmaxTH) SNRLPF_yuv[k] = TNRLPF_yuv[k];
6387 // //Bit 13:11,reg_MATNR_SNRLPF_Cmode LPF based SNR filtering mode on CHRM channel:
6388 // // 0: gradient LPF [1 1]/2, 1: gradient LPF [2 1 1]/4; 2: gradient LPF [3 3 2]/8; 3: gradient LPF [5 4 4 3]/16;
6389 // // 4: TNRLPF; 5 : CurLPF3x3_yuv[]; 6: CurLPF3o3_yuv[] 7: CurLPF3x5_yuv[]
6390 // //Bit 10:8, reg_MATNR_SNRLPF_Ymode LPF based SNR filtering mode on LUMA channel:
6391 // // 0: gradient LPF //Bit [1 1]/2, 1: gradient LPF [2 1 1]/4; 2: gradient LPF [3 3 2]/8;3: gradient LPF [5 4 4 3]/16;
6392 // // 4: TNRLPF; 5 : CurLPF3x3_yuv[]; 6: CurLPF3o3_yuv[] 7: CurLPF3x5_yuv[]
6393 // //Bit 7:4, reg_MATNR_SNRLPF_SADmin3TH Offset threshold to SAD_min to Discard SAD_min3 corresponding pixel in LPF SNR filtering. (X8 to u8 scale)
6394 // //Bit 3:0, reg_MATNR_SNRLPF_SADmin2TH Offset threshold to SAD_min to Discard SAD_min2 corresponding pixel in LPF SNR filtering. (X8 to u8 scale)
6395 //
6396 // `define NR2_MATNR_SNR_USF_GAIN 8'h56
6397 // //Bit 15:8, reg_MATNR_SNR_USF_Cgain Un-sharp (HP) compensate back Chrm portion gain, (norm 64 as 1)
6398 // //Bit 7:0, reg_MATNR_SNR_USF_Ygain Un-sharp (HP) compensate back Luma portion gain, (norm 64 as 1)
6399 //
6400 // `define NR2_MATNR_SNR_EDGE2B 8'h57
6401 // //Bit 15:8, reg_MATNR_SNR_Edge2Beta_ofst U8, Offset for Beta based on Edge.
6402 // //Bit 7:0, reg_MATNR_SNR_Edge2Beta_gain U8. Gain to SAD_min for Beta based on Edge. (norm 16 as 1)
6403 //
6404 // `define NR2_MATNR_BETA_EGAIN 8'h58
6405 // //Bit 15:8, reg_MATNR_CBeta_Egain U8, Gain to Edge based Beta for Chrm channel. (normalized to 32 as 1)
6406 // //Bit 7:0, reg_MATNR_YBeta_Egain U8, Gain to Edge based Beta for Luma channel. (normalized to 32 as 1)
6407 //
6408 // `define NR2_MATNR_BETA_BRT 8'h59
6409 // //Bit 31:28, reg_MATNR_beta_BRT_limt_hi U4, Beta adjustment based on Brightness high side Limit. (X16 to u8 scale)
6410 // //Bit 27:24, reg_MATNR_beta_BRT_slop_hi U4, Beta adjustment based on Brightness high side slope. Normalized to 16 as 1
6411 // //Bit 23:16, reg_MATNR_beta_BRT_thrd_hi U8, Beta adjustment based on Brightness high threshold.(u8 scale)
6412 // //Bit 15:12, reg_MATNR_beta_BRT_limt_lo U4, Beta adjustment based on Brightness low side Limit. (X16 to u8 scale)
6413 // //Bit 11:8, reg_MATNR_beta_BRT_slop_lo U4, Beta adjustment based on Brightness low side slope. Normalized to 16 as 1
6414 // //Bit 7:0, reg_MATNR_beta_BRT_thrd_lo U8, Beta adjustment based on Brightness low threshold.(u8 scale)
6415 // `define NR2_MATNR_XBETA_CFG 8'h5a
6416 // //Bit 19:18, reg_MATNR_CBeta_use_mode U2, Beta options (mux) from beta_motion and beta_edge for Chrm channel;
6417 // //Bit 17:16, reg_MATNR_YBeta_use_mode U2, Beta options (mux) from beta_motion and beta_edge for Luma channel;
6418 // //Bit 15: 8, reg_MATNR_CBeta_Ofst U8, Offset to Beta for Chrm channel.(after beta_edge and beta_motion mux)
6419 // //Bit 7: 0, reg_MATNR_YBeta_Ofst U8, Offset to Beta for Luma channel.(after beta_edge and beta_motion mux)
6420 // `define NR2_MATNR_YBETA_SCL 8'h5b
6421 // //Bit 31:24, reg_MATNR_YBeta_scale_min U8, Final step Beta scale low limit for Luma channel;
6422 // //Bit 23:16, reg_MATNR_YBeta_scale_max U8, Final step Beta scale high limit for Luma channe;
6423 // //Bit 15: 8, reg_MATNR_YBeta_scale_gain U8, Final step Beta scale Gain for Luma channel (normalized 32 to 1);
6424 // //Bit 7 : 0, reg_MATNR_YBeta_scale_ofst S8, Final step Beta scale offset for Luma channel ;
6425 // `define NR2_MATNR_CBETA_SCL 8'h5c
6426 // //Bit 31:24, reg_MATNR_CBeta_scale_min Final step Beta scale low limit for Chrm channel.Similar to Y
6427 // //Bit 23:16, reg_MATNR_CBeta_scale_max U8, Final step Beta scale high limit for Chrm channel.Similar to Y
6428 // //Bit 15: 8, reg_MATNR_CBeta_scale_gain U8, Final step Beta scale Gain for Chrm channel Similar to Y
6429 // //Bit 7: 0, reg_MATNR_CBeta_scale_ofst S8, Final step Beta scale offset for Chrm channel Similar to Y
6430 // `define NR2_SNR_MASK 8'h5d
6431 // //Bit 20:0, SAD_MSK Valid signal in the 3x7 SAD surface
6432 // `define NR2_SAD2NORM_LUT0 8'h5e
6433 // //Bit 31:24, reg_MATNR_SAD2Norm_LUT_3 SAD convert normal LUT node 3
6434 // //Bit 23:16, reg_MATNR_SAD2Norm_LUT_2 SAD convert normal LUT node 2
6435 // //Bit 15: 8, reg_MATNR_SAD2Norm_LUT_1 SAD convert normal LUT node 1
6436 // //Bit 7: 0, reg_MATNR_SAD2Norm_LUT_0 SAD convert normal LUT node 0
6437 // `define NR2_SAD2NORM_LUT1 8'h5f
6438 // //Bit 31:24, reg_MATNR_SAD2Norm_LUT_7 SAD convert normal LUT node 7
6439 // //Bit 23:16, reg_MATNR_SAD2Norm_LUT_6 SAD convert normal LUT node 6
6440 // //Bit 15: 8, reg_MATNR_SAD2Norm_LUT_5 SAD convert normal LUT node 5
6441 // //Bit 7: 0, reg_MATNR_SAD2Norm_LUT_4 SAD convert normal LUT node 4
6442 // `define NR2_SAD2NORM_LUT2 8'h60
6443 // //Bit 31:24, reg_MATNR_SAD2Norm_LUT_11 SAD convert normal LUT node 11
6444 // //Bit 23:16, reg_MATNR_SAD2Norm_LUT_10 SAD convert normal LUT node 10
6445 // //Bit 15: 8, reg_MATNR_SAD2Norm_LUT_9 SAD convert normal LUT node 9
6446 // //Bit 7: 0, reg_MATNR_SAD2Norm_LUT_8 SAD convert normal LUT node 8
6447 // `define NR2_SAD2NORM_LUT3 8'h61
6448 // //Bit 31:24, reg_MATNR_SAD2Norm_LUT_15 SAD convert normal LUT node 15
6449 // //Bit 23:16, reg_MATNR_SAD2Norm_LUT_14 SAD convert normal LUT node 14
6450 // //Bit 15:8, reg_MATNR_SAD2Norm_LUT_13 SAD convert normal LUT node 13
6451 // //Bit 7:0, reg_MATNR_SAD2Norm_LUT_12 SAD convert normal LUT node 12
6452 // `define NR2_EDGE2BETA_LUT0 8'h62
6453 // //Bit 31:24, reg_MATNR_Edge2Beta_LUT_3 Edge convert beta LUT node 3
6454 // //Bit 23:16, reg_MATNR_Edge2Beta_LUT_2 Edge convert beta LUT node 2
6455 // //Bit 15: 8, reg_MATNR_Edge2Beta_LUT_1 Edge convert beta LUT node 1
6456 // //Bit 7: 0, reg_MATNR_Edge2Beta_LUT_0 Edge convert beta LUT node 0
6457 // `define NR2_EDGE2BETA_LUT1 8'h63
6458 // //Bit 31:24, reg_MATNR_Edge2Beta_LUT_7 Edge convert beta LUT node 7
6459 // //Bit 23:16, reg_MATNR_Edge2Beta_LUT_6 Edge convert beta LUT node 6
6460 // //Bit 15: 8, reg_MATNR_Edge2Beta_LUT_5 Edge convert beta LUT node 5
6461 // //Bit 7: 0, reg_MATNR_Edge2Beta_LUT_4 Edge convert beta LUT node 4
6462 // `define NR2_EDGE2BETA_LUT2 8'h64
6463 // //Bit 31:24, reg_MATNR_Edge2Beta_LUT_11 Edge convert beta LUT node 11
6464 // //Bit 23:16, reg_MATNR_Edge2Beta_LUT_10 Edge convert beta LUT node 10
6465 // //Bit 15: 8, reg_MATNR_Edge2Beta_LUT_9 Edge convert beta LUT node 9
6466 // //Bit 7: 0, reg_MATNR_Edge2Beta_LUT_8 Edge convert beta LUT node 8
6467 // `define NR2_EDGE2BETA_LUT3 8'h65
6468 // //Bit 31:24, reg_MATNR_Edge2Beta_LUT_15 Edge convert beta LUT node 15
6469 // //Bit 23:16, reg_MATNR_Edge2Beta_LUT_14 Edge convert beta LUT node 14
6470 // //Bit 15: 8, reg_MATNR_Edge2Beta_LUT_13 Edge convert beta LUT node 13
6471 // //Bit 7: 0, reg_MATNR_Edge2Beta_LUT_12 Edge convert beta LUT node 12
6472 // `define NR2_MOTION2BETA_LUT0 8'h66
6473 // //Bit 31:24, reg_MATNR_Mot2Beta_LUT_3 Motion convert beta LUT node 3
6474 // //Bit 23:16, reg_MATNR_Mot2Beta_LUT_2 Motion convert beta LUT node 2
6475 // //Bit 15: 8, reg_MATNR_Mot2Beta_LUT_1 Motion convert beta LUT node 1
6476 // //Bit 7: 0, reg_MATNR_Mot2Beta_LUT_0 Motion convert beta LUT node 0
6477 // `define NR2_MOTION2BETA_LUT1 8'h67
6478 // //Bit 31:24, reg_MATNR_Mot2Beta_LUT_7 Motion convert beta LUT node 7
6479 // //Bit 23:16, reg_MATNR_Mot2Beta_LUT_6 Motion convert beta LUT node 6
6480 // //Bit 15: 8, reg_MATNR_Mot2Beta_LUT_5 Motion convert beta LUT node 5
6481 // //Bit 7: 0, reg_MATNR_Mot2Beta_LUT_4 Motion convert beta LUT node 4
6482 // `define NR2_MOTION2BETA_LUT2 8'h68
6483 // //Bit 31:24, reg_MATNR_Mot2Beta_LUT_11 Motion convert beta LUT node 11
6484 // //Bit 23:16, reg_MATNR_Mot2Beta_LUT_10 Motion convert beta LUT node 10
6485 // //Bit 15: 8, reg_MATNR_Mot2Beta_LUT_9 Motion convert beta LUT node 9
6486 // //Bit 7: 0, reg_MATNR_Mot2Beta_LUT_8 Motion convert beta LUT node 8
6487 // `define NR2_MOTION2BETA_LUT3 8'h69
6488 // //Bit 31:24, reg_MATNR_Mot2Beta_LUT_15 Motion convert beta LUT node 15
6489 // //Bit 23:16, reg_MATNR_Mot2Beta_LUT_14 Motion convert beta LUT node 14
6490 // //Bit 15: 8, reg_MATNR_Mot2Beta_LUT_13 Motion convert beta LUT node 13
6491 // //Bit 7: 0, reg_MATNR_Mot2Beta_LUT_12 Motion convert beta LUT node 12
6492 // `define NR2_MATNR_MTN_CRTL 8'h6a
6493 // //Bit 25:24, reg_MATNR_Vmtn_use_mode Motion_yuvV channel motion selection mode:0: Vmot;1:Ymot/2 + (Umot+Vmot)/4; 2:Ymot/2 + max(Umot,Vmot)/2; 3: max(Ymot,Umot, Vmot)
6494 // //Bit 21:20, reg_MATNR_Umtn_use_mode Motion_yuvU channel motion selection mode:0:Umot;1:Ymot/2 + (Umot+Vmot)/4; 2:Ymot/2 + max(Umot,Vmot)/2; 3: max(Ymot,Umot, Vmot)
6495 // //Bit 17:16, reg_MATNR_Ymtn_use_mode Motion_yuvLuma channel motion selection mode:0: Ymot, 1: Ymot/2 + (Umot+Vmot)/4; 2: Ymot/2 + max(Umot,Vmot)/2; 3: max(Ymot,Umot, Vmot)
6496 // //Bit 13:12, reg_MATNR_mtn_txt_mode Texture detection mode for adaptive coring of HP motion
6497 // //Bit 9: 8, reg_MATNR_mtn_cor_mode Coring selection mode based on texture detection;
6498 // //Bit 6: 4, reg_MATNR_mtn_hpf_mode video mode of current and previous frame/field for MotHPF_yuv[k] calculation:
6499 // //Bit 2: 0, reg_MATNR_mtn_lpf_mode LPF video mode of current and previous frame/field for MotLPF_yuv[k] calculation:
6500 // `define NR2_MATNR_MTN_CRTL2 8'h6b
6501 // //Bit 18:16, reg_MATNR_iir_BS_Ymode IIR TNR filter Band split filter mode for Luma LPF result generation (Cur and Prev);
6502 // //Bit 15: 8, reg_MATNR_mtnb_alpLP_Cgain Scale of motion_brthp_uv to motion_brtlp_uv, normalized to 32 as 1
6503 // //Bit 7: 0, reg_MATNR_mtnb_alpLP_Ygain Scale of motion_brthp_y to motion_brtlp_y, normalized to 32 as 1
6504 // `define NR2_MATNR_MTN_COR 8'h6c
6505 // //Bit 15:12, reg_MATNR_mtn_cor_Cofst Coring Offset for Chroma Motion.
6506 // //Bit 11: 8, reg_MATNR_mtn_cor_Cgain Gain to texture based coring for Chroma Motion. Normalized to 16 as 1
6507 // //Bit 7: 4, reg_MATNR_mtn_cor_Yofst Coring Offset for Luma Motion.
6508 // //Bit 3: 0, reg_MATNR_mtn_cor_Ygain Gain to texture based coring for Luma Motion. Normalized to 16 as 1
6509 // `define NR2_MATNR_MTN_GAIN 8'h6d
6510 // //Bit 31:24, reg_MATNR_mtn_hp_Cgain Gain to MotHPF_yuv[k] Chrm channel for motion calculation, normalized to 64 as 1
6511 // //Bit 23:16, reg_MATNR_mtn_hp_Ygain Gain to MotHPF_yuv[k] Luma channel for motion calculation, normalized to 64 as 1
6512 // //Bit 15: 8, reg_MATNR_mtn_lp_Cgain Gain to MotLPF_yuv[k] Chrm channel for motion calculation, normalized to 32 as 1
6513 // //Bit 7: 0, reg_MATNR_mtn_lp_Ygain Gain to MotLPF_yuv[k] Luma channel for motion calculation, normalized to 32 as 1
6514 // `define NR2_MATNR_DEGHOST 8'h6e
6515 // //Bit 8, reg_MATNR_DeGhost_En Enable signal for DeGhost function:0: disable; 1: enable
6516 // //Bit 7:4, reg_MATNR_DeGhost_COS DeGhost Overshoot margin for UV channel, (X2 to u10 scale)
6517 // //Bit 3:0, reg_MATNR_DeGhost_YOS DeGhost Overshoot margin for Luma channel, (X2 to u10 scale)
6518 //
6519 // `define NR2_MATNR_ALPHALP_LUT0 8'h6f
6520 // //Bit 31:24, reg_MATNR_AlphaLP_LUT_3 Matnr low-pass filter alpha LUT node 3
6521 // //Bit 23:16, reg_MATNR_AlphaLP_LUT_2 Matnr low-pass filter alpha LUT node 2
6522 // //Bit 15: 8, reg_MATNR_AlphaLP_LUT_1 Matnr low-pass filter alpha LUT node 1
6523 // //Bit 7: 0, reg_MATNR_AlphaLP_LUT_0 Matnr low-pass filter alpha LUT node 0
6524 // `define NR2_MATNR_ALPHALP_LUT1 8'h70
6525 // //Bit 31:24, reg_MATNR_AlphaLP_LUT_7 Matnr low-pass filter alpha LUT node 7
6526 // //Bit 23:16, reg_MATNR_AlphaLP_LUT_6 Matnr low-pass filter alpha LUT node 6
6527 // //Bit 15: 8, reg_MATNR_AlphaLP_LUT_5 Matnr low-pass filter alpha LUT node 5
6528 // //Bit 7: 0, reg_MATNR_AlphaLP_LUT_4 Matnr low-pass filter alpha LUT node 4
6529 // `define NR2_MATNR_ALPHALP_LUT2 8'h71
6530 // //Bit 31:24, reg_MATNR_AlphaLP_LUT_11 Matnr low-pass filter alpha LUT node 11
6531 // //Bit 23:16, reg_MATNR_AlphaLP_LUT_10 Matnr low-pass filter alpha LUT node 10
6532 // //Bit 15: 8, reg_MATNR_AlphaLP_LUT_9 Matnr low-pass filter alpha LUT node 9
6533 // //Bit 7: 0, reg_MATNR_AlphaLP_LUT_8 Matnr low-pass filter alpha LUT node 8
6534 // `define NR2_MATNR_ALPHALP_LUT3 8'h72
6535 // //Bit 31:24, reg_MATNR_AlphaLP_LUT_15 Matnr low-pass filter alpha LUT node 15
6536 // //Bit 23:16, reg_MATNR_AlphaLP_LUT_14 Matnr low-pass filter alpha LUT node 14
6537 // //Bit 15: 8, reg_MATNR_AlphaLP_LUT_13 Matnr low-pass filter alpha LUT node 13
6538 // //Bit 7: 0, reg_MATNR_AlphaLP_LUT_12 Matnr low-pass filter alpha LUT node 12
6539 // `define NR2_MATNR_ALPHAHP_LUT0 8'h73
6540 // //Bit 31:24, reg_MATNR_AlphaHP_LUT_3 Matnr high-pass filter alpha LUT node 3
6541 // //Bit 23:16, reg_MATNR_AlphaHP_LUT_2 Matnr high-pass filter alpha LUT node 2
6542 // //Bit 15: 8, reg_MATNR_AlphaHP_LUT_1 Matnr high-pass filter alpha LUT node 1
6543 // //Bit 7: 0, reg_MATNR_AlphaHP_LUT_0 Matnr high-pass filter alpha LUT node 0
6544 // `define NR2_MATNR_ALPHAHP_LUT1 8'h74
6545 // //Bit 31:24, reg_MATNR_AlphaHP_LUT_7 Matnr high-pass filter alpha LUT node 7
6546 // //Bit 23:16, reg_MATNR_AlphaHP_LUT_6 Matnr high-pass filter alpha LUT node 6
6547 // //Bit 15: 8, reg_MATNR_AlphaHP_LUT_5 Matnr high-pass filter alpha LUT node 5
6548 // //Bit 7: 0, reg_MATNR_AlphaHP_LUT_4 Matnr high-pass filter alpha LUT node 4
6549 // `define NR2_MATNR_ALPHAHP_LUT2 8'h75
6550 // //Bit 31:24, reg_MATNR_AlphaHP_LUT_11 Matnr high-pass filter alpha LUT node 11
6551 // //Bit 23:16, reg_MATNR_AlphaHP_LUT_10 Matnr high-pass filter alpha LUT node 10
6552 // //Bit 15: 8, reg_MATNR_AlphaHP_LUT_9 Matnr high-pass filter alpha LUT node 9
6553 // //Bit 7: 0, reg_MATNR_AlphaHP_LUT_8 Matnr high-pass filter alpha LUT node 8
6554 // `define NR2_MATNR_ALPHAHP_LUT3 8'h76
6555 // //Bit 31:24, reg_MATNR_AlphaHP_LUT_15 Matnr high-pass filter alpha LUT node 15
6556 // //Bit 23:16, reg_MATNR_AlphaHP_LUT_14 Matnr high-pass filter alpha LUT node 14
6557 // //Bit 15: 8, reg_MATNR_AlphaHP_LUT_13 Matnr high-pass filter alpha LUT node 13
6558 // //Bit 7: 0, reg_MATNR_AlphaHP_LUT_12 Matnr high-pass filter alpha LUT node 12
6559 //
6560 // `define NR2_MATNR_MTNB_BRT 8'h77
6561 // //Bit 31:28, reg_MATNR_mtnb_BRT_limt_hi Motion adjustment based on Brightness high side Limit. (X16 to u8 scale)
6562 // //Bit 27:24, reg_MATNR_mtnb_BRT_slop_hi Motion adjustment based on Brightness high side slope. Normalized to 16 as 1
6563 // //Bit 23:16, reg_MATNR_mtnb_BRT_thrd_hi Motion adjustment based on Brightness high threshold.(u8 scale)
6564 // //Bit 15:12, reg_MATNR_mtnb_BRT_limt_lo Motion adjustment based on Brightness low side Limit. (X16 to u8 scale)
6565 // //Bit 11: 8, reg_MATNR_mtnb_BRT_slop_lo Motion adjustment based on Brightness low side slope. Normalized to 16 as 1
6566 // //Bit 7: 0, reg_MATNR_mtnb_BRT_thrd_lo Motion adjustment based on Brightness low threshold.(u8 scale)
6567 // 0x51 - 0x69 | 0x4e | 0x6a - 0x77
6568 //
6569 // Reading file: nr2_regs.h
6570 //
6571 // synopsys translate_off
6572 // synopsys translate_on
6573 //========== nr2_snr_regs register begin ==========//
6574 #define NR2_SNR_SAD_CFG (0x1751)
6575 #define P_NR2_SNR_SAD_CFG (volatile uint32_t *)((0x1751 << 2) + 0xff900000)
6576 //Bit 31:13 reserved
6577 //Bit 12 reg_matnr_snr_sad_cenrpl // unsigned , default = 1
6578 //Bit 11: 8 reg_matnr_snr_sad_coring // unsigned , default = 3
6579 //Bit 7 reserved
6580 //Bit 6: 5 reg_matnr_snr_sad_winmod // unsigned , default = 1 0: 1x1; 1: [1 1 1] 2: [1 2 1]; 3: [1 2 2 2 1];
6581 //Bit 4: 0 sad_coef_num // unsigned , default = 1 0: 1x1; 1: [1 1 1] 2: [1 2 1]; 3: [1 2 2 2 1];
6582 #define NR2_MATNR_SNR_OS (0x1752)
6583 #define P_NR2_MATNR_SNR_OS (volatile uint32_t *)((0x1752 << 2) + 0xff900000)
6584 //Bit 31: 8 reserved
6585 //Bit 7: 4 reg_matnr_snr_cos // unsigned , default = 8
6586 //Bit 3: 0 reg_matnr_snr_yos // unsigned , default = 13
6587 #define NR2_MATNR_SNR_NRM_CFG (0x1753)
6588 #define P_NR2_MATNR_SNR_NRM_CFG (volatile uint32_t *)((0x1753 << 2) + 0xff900000)
6589 //Bit 31:24 reserved
6590 //Bit 23:16 reg_matnr_snr_nrm_ofst // signed , default = 64
6591 //Bit 15: 8 reg_matnr_snr_nrm_max // unsigned , default = 255
6592 //Bit 7: 0 reg_matnr_snr_nrm_min // unsigned , default = 0
6593 #define NR2_MATNR_SNR_NRM_GAIN (0x1754)
6594 #define P_NR2_MATNR_SNR_NRM_GAIN (volatile uint32_t *)((0x1754 << 2) + 0xff900000)
6595 //Bit 31:16 reserved
6596 //Bit 15: 8 reg_matnr_snr_nrm_cgain // unsigned , default = 0 norm 32
6597 //Bit 7: 0 reg_matnr_snr_nrm_ygain // unsigned , default = 32 norm 32
6598 #define NR2_MATNR_SNR_LPF_CFG (0x1755)
6599 #define P_NR2_MATNR_SNR_LPF_CFG (volatile uint32_t *)((0x1755 << 2) + 0xff900000)
6600 //Bit 31:24 reserved
6601 //Bit 23:16 reg_matnr_snrlpf_sadmaxth // unsigned , default = 12
6602 //Bit 15:14 reserved
6603 //Bit 13:11 reg_matnr_snrlpf_cmode // unsigned , default = 2 0: gradient LPF [1 1]/2, 1: gradient LPF [2 1 1]/4; 2: gradient LPF [3 3 2]/8; 3: gradient LPF [5 5 4 3]/16;
6604 //Bit 10: 8 reg_matnr_snrlpf_ymode // unsigned , default = 2 0: gradient LPF [1 1]/2, 1: gradient LPF [2 1 1]/4; 2: gradient LPF [3 3 2]/8; 3: gradient LPF [5 5 4 3]/16;
6605 //Bit 7: 4 reg_matnr_snrlpf_sadmin3th // unsigned , default = 6 X8
6606 //Bit 3: 0 reg_matnr_snrlpf_sadmin2th // unsigned , default = 4 X8
6607 #define NR2_MATNR_SNR_USF_GAIN (0x1756)
6608 #define P_NR2_MATNR_SNR_USF_GAIN (volatile uint32_t *)((0x1756 << 2) + 0xff900000)
6609 //Bit 31:16 reserved
6610 //Bit 15: 8 reg_matnr_snr_usf_cgain // unsigned , default = 0 norm 64
6611 //Bit 7: 0 reg_matnr_snr_usf_ygain // unsigned , default = 0 norm 64
6612 #define NR2_MATNR_SNR_EDGE2B (0x1757)
6613 #define P_NR2_MATNR_SNR_EDGE2B (volatile uint32_t *)((0x1757 << 2) + 0xff900000)
6614 //Bit 31:16 reserved
6615 //Bit 15: 8 reg_matnr_snr_edge2beta_ofst // unsigned , default = 128
6616 //Bit 7: 0 reg_matnr_snr_edge2beta_gain // unsigned , default = 16
6617 #define NR2_MATNR_BETA_EGAIN (0x1758)
6618 #define P_NR2_MATNR_BETA_EGAIN (volatile uint32_t *)((0x1758 << 2) + 0xff900000)
6619 //Bit 31:16 reserved
6620 //Bit 15: 8 reg_matnr_cbeta_egain // unsigned , default = 32 normalized to 32
6621 //Bit 7: 0 reg_matnr_ybeta_egain // unsigned , default = 32 normalized to 32
6622 #define NR2_MATNR_BETA_BRT (0x1759)
6623 #define P_NR2_MATNR_BETA_BRT (volatile uint32_t *)((0x1759 << 2) + 0xff900000)
6624 //Bit 31:28 reg_matnr_beta_brt_limt_hi // unsigned , default = 0
6625 //Bit 27:24 reg_matnr_beta_brt_slop_hi // unsigned , default = 0
6626 //Bit 23:16 reg_matnr_beta_brt_thrd_hi // unsigned , default = 160
6627 //Bit 15:12 reg_matnr_beta_brt_limt_lo // unsigned , default = 6
6628 //Bit 11: 8 reg_matnr_beta_brt_slop_lo // unsigned , default = 6
6629 //Bit 7: 0 reg_matnr_beta_brt_thrd_lo // unsigned , default = 100
6630 #define NR2_MATNR_XBETA_CFG (0x175a)
6631 #define P_NR2_MATNR_XBETA_CFG (volatile uint32_t *)((0x175a << 2) + 0xff900000)
6632 //Bit 31:20 reserved
6633 //Bit 19:18 reg_matnr_cbeta_use_mode // unsigned , default = 0 0: beta_motion; 1: beta_edge; 2: min(beta_mot,beta_edge); 3: (beta_mot + beta_edge)/2
6634 //Bit 17:16 reg_matnr_ybeta_use_mode // unsigned , default = 0 0: beta_motion; 1: beta_edge; 2: min(beta_mot,beta_edge); 3: (beta_mot + beta_edge)/2;
6635 //Bit 15: 8 reg_matnr_cbeta_ofst // unsigned , default = 0
6636 //Bit 7: 0 reg_matnr_ybeta_ofst // unsigned , default = 0
6637 #define NR2_MATNR_YBETA_SCL (0x175b)
6638 #define P_NR2_MATNR_YBETA_SCL (volatile uint32_t *)((0x175b << 2) + 0xff900000)
6639 //Bit 31:24 reg_matnr_ybeta_scale_min // unsigned , default = 60
6640 //Bit 23:16 reg_matnr_ybeta_scale_max // unsigned , default = 255
6641 //Bit 15: 8 reg_matnr_ybeta_scale_gain // unsigned , default = 32 normalized 32 to 1.0
6642 //Bit 7: 0 reg_matnr_ybeta_scale_ofst // signed , default = 0
6643 #define NR2_MATNR_CBETA_SCL (0x175c)
6644 #define P_NR2_MATNR_CBETA_SCL (volatile uint32_t *)((0x175c << 2) + 0xff900000)
6645 //Bit 31:24 reg_matnr_cbeta_scale_min // unsigned , default = 0
6646 //Bit 23:16 reg_matnr_cbeta_scale_max // unsigned , default = 255
6647 //Bit 15: 8 reg_matnr_cbeta_scale_gain // unsigned , default = 32 normalized 32 to 1.0
6648 //Bit 7: 0 reg_matnr_cbeta_scale_ofst // signed , default = 0
6649 #define NR2_SNR_MASK (0x175d)
6650 #define P_NR2_SNR_MASK (volatile uint32_t *)((0x175d << 2) + 0xff900000)
6651 //Bit 31:21 reserved
6652 //Bit 20: 0 sad_msk // unsigned , default = 0x0f9f3e
6653 #define NR2_SAD2NORM_LUT0 (0x175e)
6654 #define P_NR2_SAD2NORM_LUT0 (volatile uint32_t *)((0x175e << 2) + 0xff900000)
6655 //Bit 31:24 reg_matnr_sad2norm_lut3 // unsigned , default = 114
6656 //Bit 23:16 reg_matnr_sad2norm_lut2 // unsigned , default = 146
6657 //Bit 15: 8 reg_matnr_sad2norm_lut1 // unsigned , default = 171
6658 //Bit 7: 0 reg_matnr_sad2norm_lut0 // unsigned , default = 205
6659 #define NR2_SAD2NORM_LUT1 (0x175f)
6660 #define P_NR2_SAD2NORM_LUT1 (volatile uint32_t *)((0x175f << 2) + 0xff900000)
6661 //Bit 31:24 reg_matnr_sad2norm_lut7 // unsigned , default = 28
6662 //Bit 23:16 reg_matnr_sad2norm_lut6 // unsigned , default = 35
6663 //Bit 15: 8 reg_matnr_sad2norm_lut5 // unsigned , default = 49
6664 //Bit 7: 0 reg_matnr_sad2norm_lut4 // unsigned , default = 79
6665 #define NR2_SAD2NORM_LUT2 (0x1760)
6666 #define P_NR2_SAD2NORM_LUT2 (volatile uint32_t *)((0x1760 << 2) + 0xff900000)
6667 //Bit 31:24 reg_matnr_sad2norm_lut11 // unsigned , default = 15
6668 //Bit 23:16 reg_matnr_sad2norm_lut10 // unsigned , default = 17
6669 //Bit 15: 8 reg_matnr_sad2norm_lut9 // unsigned , default = 19
6670 //Bit 7: 0 reg_matnr_sad2norm_lut8 // unsigned , default = 23
6671 #define NR2_SAD2NORM_LUT3 (0x1761)
6672 #define P_NR2_SAD2NORM_LUT3 (volatile uint32_t *)((0x1761 << 2) + 0xff900000)
6673 //Bit 31:24 reg_matnr_sad2norm_lut15 // unsigned , default = 8
6674 //Bit 23:16 reg_matnr_sad2norm_lut14 // unsigned , default = 9
6675 //Bit 15: 8 reg_matnr_sad2norm_lut13 // unsigned , default = 10
6676 //Bit 7: 0 reg_matnr_sad2norm_lut12 // unsigned , default = 12
6677 #define NR2_EDGE2BETA_LUT0 (0x1762)
6678 #define P_NR2_EDGE2BETA_LUT0 (volatile uint32_t *)((0x1762 << 2) + 0xff900000)
6679 //Bit 31:24 reg_matnr_edge2beta_lut3 // unsigned , default = 128
6680 //Bit 23:16 reg_matnr_edge2beta_lut2 // unsigned , default = 160
6681 //Bit 15: 8 reg_matnr_edge2beta_lut1 // unsigned , default = 224
6682 //Bit 7: 0 reg_matnr_edge2beta_lut0 // unsigned , default = 255
6683 #define NR2_EDGE2BETA_LUT1 (0x1763)
6684 #define P_NR2_EDGE2BETA_LUT1 (volatile uint32_t *)((0x1763 << 2) + 0xff900000)
6685 //Bit 31:24 reg_matnr_edge2beta_lut7 // unsigned , default = 4
6686 //Bit 23:16 reg_matnr_edge2beta_lut6 // unsigned , default = 16
6687 //Bit 15: 8 reg_matnr_edge2beta_lut5 // unsigned , default = 32
6688 //Bit 7: 0 reg_matnr_edge2beta_lut4 // unsigned , default = 80
6689 #define NR2_EDGE2BETA_LUT2 (0x1764)
6690 #define P_NR2_EDGE2BETA_LUT2 (volatile uint32_t *)((0x1764 << 2) + 0xff900000)
6691 //Bit 31:24 reg_matnr_edge2beta_lut11 // unsigned , default = 0
6692 //Bit 23:16 reg_matnr_edge2beta_lut10 // unsigned , default = 0
6693 //Bit 15: 8 reg_matnr_edge2beta_lut9 // unsigned , default = 0
6694 //Bit 7: 0 reg_matnr_edge2beta_lut8 // unsigned , default = 2
6695 #define NR2_EDGE2BETA_LUT3 (0x1765)
6696 #define P_NR2_EDGE2BETA_LUT3 (volatile uint32_t *)((0x1765 << 2) + 0xff900000)
6697 //Bit 31:24 reg_matnr_edge2beta_lut15 // unsigned , default = 0
6698 //Bit 23:16 reg_matnr_edge2beta_lut14 // unsigned , default = 0
6699 //Bit 15: 8 reg_matnr_edge2beta_lut13 // unsigned , default = 0
6700 //Bit 7: 0 reg_matnr_edge2beta_lut12 // unsigned , default = 0
6701 #define NR2_MOTION2BETA_LUT0 (0x1766)
6702 #define P_NR2_MOTION2BETA_LUT0 (volatile uint32_t *)((0x1766 << 2) + 0xff900000)
6703 //Bit 31:24 reg_matnr_mot2beta_lut3 // unsigned , default = 32
6704 //Bit 23:16 reg_matnr_mot2beta_lut2 // unsigned , default = 16
6705 //Bit 15: 8 reg_matnr_mot2beta_lut1 // unsigned , default = 4
6706 //Bit 7: 0 reg_matnr_mot2beta_lut0 // unsigned , default = 0
6707 #define NR2_MOTION2BETA_LUT1 (0x1767)
6708 #define P_NR2_MOTION2BETA_LUT1 (volatile uint32_t *)((0x1767 << 2) + 0xff900000)
6709 //Bit 31:24 reg_matnr_mot2beta_lut7 // unsigned , default = 196
6710 //Bit 23:16 reg_matnr_mot2beta_lut6 // unsigned , default = 128
6711 //Bit 15: 8 reg_matnr_mot2beta_lut5 // unsigned , default = 64
6712 //Bit 7: 0 reg_matnr_mot2beta_lut4 // unsigned , default = 48
6713 #define NR2_MOTION2BETA_LUT2 (0x1768)
6714 #define P_NR2_MOTION2BETA_LUT2 (volatile uint32_t *)((0x1768 << 2) + 0xff900000)
6715 //Bit 31:24 reg_matnr_mot2beta_lut11 // unsigned , default = 255
6716 //Bit 23:16 reg_matnr_mot2beta_lut10 // unsigned , default = 255
6717 //Bit 15: 8 reg_matnr_mot2beta_lut9 // unsigned , default = 240
6718 //Bit 7: 0 reg_matnr_mot2beta_lut8 // unsigned , default = 224
6719 #define NR2_MOTION2BETA_LUT3 (0x1769)
6720 #define P_NR2_MOTION2BETA_LUT3 (volatile uint32_t *)((0x1769 << 2) + 0xff900000)
6721 //Bit 31:24 reg_matnr_mot2beta_lut15 // unsigned , default = 255
6722 //Bit 23:16 reg_matnr_mot2beta_lut14 // unsigned , default = 255
6723 //Bit 15: 8 reg_matnr_mot2beta_lut13 // unsigned , default = 255
6724 //Bit 7: 0 reg_matnr_mot2beta_lut12 // unsigned , default = 255
6725 //========== nr2_snr_regs register end ==========//
6726 //========== nr2_tnr_regs register begin ==========//
6727 #define NR2_IIR_CTRL (0x174e)
6728 #define P_NR2_IIR_CTRL (volatile uint32_t *)((0x174e << 2) + 0xff900000)
6729 //Bit 31:16 reserved
6730 //Bit 15:14 reg_lp_iir_8bit_mode // unsigned , default = 0 10bits; 1: 9bits; 2: 8bits 3: 7bits
6731 //Bit 13:12 reg_hp_iir_mute_mode // unsigned , default = 0
6732 //Bit 11: 8 reg_hp_iir_mute_thrd // unsigned , default = 0
6733 //Bit 7: 6 reg_hp_iir_8bit_mode // unsigned , default = 0
6734 //Bit 5: 4 reg_lp_iir_mute_mode // unsigned , default = 0
6735 //Bit 3: 0 reg_lp_iir_mute_thrd // unsigned , default = 0
6736 #define NR2_MATNR_MTN_CRTL (0x176a)
6737 #define P_NR2_MATNR_MTN_CRTL (volatile uint32_t *)((0x176a << 2) + 0xff900000)
6738 //Bit 31:20 reserved
6739 //Bit 19:18 reg_matnr_vmtn_use_mode // unsigned , default = 0 0- Vmot, 1- Ymot/2 + (Umot+Vmot)/4; 2- Ymot/2 + max(Umot,Vmot)/2; 3- max(Ymot,Umot, Vmot)
6740 //Bit 17:16 reg_matnr_umtn_use_mode // unsigned , default = 0 0- Umot, 1- Ymot/2 + (Umot+Vmot)/4; 2- Ymot/2 + max(Umot,Vmot)/2; 3- max(Ymot,Umot, Vmot)
6741 //Bit 15:14 reg_matnr_ymtn_use_mode // unsigned , default = 0 0- Ymot, 1- Ymot/2 + (Umot+Vmot)/4; 2- Ymot/2 + max(Umot,Vmot)/2; 3- max(Ymot,Umot, Vmot)
6742 //Bit 13:12 reg_matnr_mtn_txt_mode // unsigned , default = 1
6743 //Bit 11 reserved
6744 //Bit 10: 8 reg_matnr_mtn_cor_mode // unsigned , default = 1 changes)
6745 //Bit 7: 4 reg_matnr_mtn_hpf_mode // unsigned , default = 8 extend to u4 for nr4, 0- 1x1; 1: 1x3; 2: 1x5; 3: 3x3; 4: 3o3; 5: 3x5, 6:3x3 SAD, 7: 5x3 SAD, 8-15: drt adaptive
6746 //Bit 3 reserved
6747 //Bit 2: 0 reg_matnr_mtn_lpf_mode // unsigned , default = 6 0- 1x1; 1: 1x3; 2: 1x5; 3: 3x3; 4: 3o3; 5: 3x5, 6,7: drt adaptive
6748 #define NR2_MATNR_MTN_CRTL2 (0x176b)
6749 #define P_NR2_MATNR_MTN_CRTL2 (volatile uint32_t *)((0x176b << 2) + 0xff900000)
6750 //Bit 31:19 reserved
6751 //Bit 18:16 reg_matnr_iir_bs_ymode // unsigned , default = 6 LPF~~ 0- 1x1; 1: 1x3; 2: 1x5; 3: 3x3; 4: 3o3; 5: 3x5; 6/7: 0
6752 //Bit 15: 8 reg_matnr_mtnb_alplp_cgain // unsigned , default = 64 to 32
6753 //Bit 7: 0 reg_matnr_mtnb_alplp_ygain // unsigned , default = 64 to 32
6754 #define NR2_MATNR_MTN_COR (0x176c)
6755 #define P_NR2_MATNR_MTN_COR (volatile uint32_t *)((0x176c << 2) + 0xff900000)
6756 //Bit 31:16 reserved
6757 //Bit 15:12 reg_matnr_mtn_cor_cofst // unsigned , default = 3 Offset for Chroma Motion.
6758 //Bit 11: 8 reg_matnr_mtn_cor_cgain // unsigned , default = 3 to texture based coring for Chroma Motion. Normalized to 16 as 1
6759 //Bit 7: 4 reg_matnr_mtn_cor_yofst // unsigned , default = 3 Offset for Luma Motion.
6760 //Bit 3: 0 reg_matnr_mtn_cor_ygain // unsigned , default = 3 to texture based coring for Luma Motion. Normalized to 16 as 1
6761 #define NR2_MATNR_MTN_GAIN (0x176d)
6762 #define P_NR2_MATNR_MTN_GAIN (volatile uint32_t *)((0x176d << 2) + 0xff900000)
6763 //Bit 31:24 reg_matnr_mtn_hp_cgain // unsigned , default = 64 to MotHPF_yuv[k] Chrm channel for motion calculation, normalized to 64 as 1
6764 //Bit 23:16 reg_matnr_mtn_hp_ygain // unsigned , default = 64 to MotHPF_yuv[k] Luma channel for motion calculation, normalized to 64 as 1
6765 //Bit 15: 8 reg_matnr_mtn_lp_cgain // unsigned , default = 64 to MotLPF_yuv[k] Chrm channel for motion calculation, normalized to 32 as 1
6766 //Bit 7: 0 reg_matnr_mtn_lp_ygain // unsigned , default = 64 to MotLPF_yuv[k] Luma channel for motion calculation, normalized to 32 as 1
6767 #define NR2_MATNR_DEGHOST (0x176e)
6768 #define P_NR2_MATNR_DEGHOST (volatile uint32_t *)((0x176e << 2) + 0xff900000)
6769 //Bit 31 reserved
6770 //Bit 30:28 reg_matnr_deghost_mode // unsigned , default = 0 0:old_deghost; 1:soft_denoise & strong_deghost; 2:strong_denoise & soft_deghost; 3:strong_denoise & strong_deghost
6771 //Bit 27:25 reserved
6772 //Bit 24:20 reg_matnr_deghost_ygain // unsigned , default = 4
6773 //Bit 19:17 reserved
6774 //Bit 16:12 reg_matnr_deghost_cgain // unsigned , default = 4
6775 //Bit 11: 9 reserved
6776 //Bit 8 reg_matnr_deghost_en // unsigned , default = 1 0: disable; 1: enable Enable signal for DeGhost function:0: disable; 1: enable
6777 //Bit 7: 4 reg_matnr_deghost_cos // unsigned , default = 3 DeGhost Overshoot margin for UV channel, (X2 to u10 scale)
6778 //Bit 3: 0 reg_matnr_deghost_yos // unsigned , default = 3 DeGhost Overshoot margin for Luma channel, (X2 to u10 scale)
6779 #define NR2_MATNR_ALPHALP_LUT0 (0x176f)
6780 #define P_NR2_MATNR_ALPHALP_LUT0 (volatile uint32_t *)((0x176f << 2) + 0xff900000)
6781 //Bit 31:24 reg_matnr_alphalp_lut3 // unsigned , default = 64 low-pass filter alpha LUT
6782 //Bit 23:16 reg_matnr_alphalp_lut2 // unsigned , default = 128 low-pass filter alpha LUT
6783 //Bit 15: 8 reg_matnr_alphalp_lut1 // unsigned , default = 128 low-pass filter alpha LUT
6784 //Bit 7: 0 reg_matnr_alphalp_lut0 // unsigned , default = 128 low-pass filter alpha LUT
6785 #define NR2_MATNR_ALPHALP_LUT1 (0x1770)
6786 #define P_NR2_MATNR_ALPHALP_LUT1 (volatile uint32_t *)((0x1770 << 2) + 0xff900000)
6787 //Bit 31:24 reg_matnr_alphalp_lut7 // unsigned , default = 255 low-pass filter alpha LUT
6788 //Bit 23:16 reg_matnr_alphalp_lut6 // unsigned , default = 128 low-pass filter alpha LUT
6789 //Bit 15: 8 reg_matnr_alphalp_lut5 // unsigned , default = 80 low-pass filter alpha LUT
6790 //Bit 7: 0 reg_matnr_alphalp_lut4 // unsigned , default = 64 low-pass filter alpha LUT
6791 #define NR2_MATNR_ALPHALP_LUT2 (0x1771)
6792 #define P_NR2_MATNR_ALPHALP_LUT2 (volatile uint32_t *)((0x1771 << 2) + 0xff900000)
6793 //Bit 31:24 reg_matnr_alphalp_lut11 // unsigned , default = 255 low-pass filter alpha LUT
6794 //Bit 23:16 reg_matnr_alphalp_lut10 // unsigned , default = 255 low-pass filter alpha LUT
6795 //Bit 15: 8 reg_matnr_alphalp_lut9 // unsigned , default = 255 low-pass filter alpha LUT
6796 //Bit 7: 0 reg_matnr_alphalp_lut8 // unsigned , default = 255 low-pass filter alpha LUT
6797 #define NR2_MATNR_ALPHALP_LUT3 (0x1772)
6798 #define P_NR2_MATNR_ALPHALP_LUT3 (volatile uint32_t *)((0x1772 << 2) + 0xff900000)
6799 //Bit 31:24 reg_matnr_alphalp_lut15 // unsigned , default = 255 low-pass filter alpha LUT
6800 //Bit 23:16 reg_matnr_alphalp_lut14 // unsigned , default = 255 low-pass filter alpha LUT
6801 //Bit 15: 8 reg_matnr_alphalp_lut13 // unsigned , default = 255 low-pass filter alpha LUT
6802 //Bit 7: 0 reg_matnr_alphalp_lut12 // unsigned , default = 255 low-pass filter alpha LUT
6803 #define NR2_MATNR_ALPHAHP_LUT0 (0x1773)
6804 #define P_NR2_MATNR_ALPHAHP_LUT0 (volatile uint32_t *)((0x1773 << 2) + 0xff900000)
6805 //Bit 31:24 reg_matnr_alphahp_lut3 // unsigned , default = 64 high-pass filter alpha LUT
6806 //Bit 23:16 reg_matnr_alphahp_lut2 // unsigned , default = 128 high-pass filter alpha LUT
6807 //Bit 15: 8 reg_matnr_alphahp_lut1 // unsigned , default = 128 high-pass filter alpha LUT
6808 //Bit 7: 0 reg_matnr_alphahp_lut0 // unsigned , default = 128 high-pass filter alpha LUT
6809 #define NR2_MATNR_ALPHAHP_LUT1 (0x1774)
6810 #define P_NR2_MATNR_ALPHAHP_LUT1 (volatile uint32_t *)((0x1774 << 2) + 0xff900000)
6811 //Bit 31:24 reg_matnr_alphahp_lut7 // unsigned , default = 255 high-pass filter alpha LUT
6812 //Bit 23:16 reg_matnr_alphahp_lut6 // unsigned , default = 128 high-pass filter alpha LUT
6813 //Bit 15: 8 reg_matnr_alphahp_lut5 // unsigned , default = 80 high-pass filter alpha LUT
6814 //Bit 7: 0 reg_matnr_alphahp_lut4 // unsigned , default = 64 high-pass filter alpha LUT
6815 #define NR2_MATNR_ALPHAHP_LUT2 (0x1775)
6816 #define P_NR2_MATNR_ALPHAHP_LUT2 (volatile uint32_t *)((0x1775 << 2) + 0xff900000)
6817 //Bit 31:24 reg_matnr_alphahp_lut11 // unsigned , default = 255 high-pass filter alpha LUT
6818 //Bit 23:16 reg_matnr_alphahp_lut10 // unsigned , default = 255 high-pass filter alpha LUT
6819 //Bit 15: 8 reg_matnr_alphahp_lut9 // unsigned , default = 255 high-pass filter alpha LUT
6820 //Bit 7: 0 reg_matnr_alphahp_lut8 // unsigned , default = 255 high-pass filter alpha LUT
6821 #define NR2_MATNR_ALPHAHP_LUT3 (0x1776)
6822 #define P_NR2_MATNR_ALPHAHP_LUT3 (volatile uint32_t *)((0x1776 << 2) + 0xff900000)
6823 //Bit 31:24 reg_matnr_alphahp_lut15 // unsigned , default = 255 high-pass filter alpha LUT
6824 //Bit 23:16 reg_matnr_alphahp_lut14 // unsigned , default = 255 high-pass filter alpha LUT
6825 //Bit 15: 8 reg_matnr_alphahp_lut13 // unsigned , default = 255 high-pass filter alpha LUT
6826 //Bit 7: 0 reg_matnr_alphahp_lut12 // unsigned , default = 255 high-pass filter alpha LUT
6827 #define NR2_MATNR_MTNB_BRT (0x1777)
6828 #define P_NR2_MATNR_MTNB_BRT (volatile uint32_t *)((0x1777 << 2) + 0xff900000)
6829 //Bit 31:28 reg_matnr_mtnb_brt_limt_hi // unsigned , default = 0
6830 //Bit 27:24 reg_matnr_mtnb_brt_slop_hi // unsigned , default = 0
6831 //Bit 23:16 reg_matnr_mtnb_brt_thrd_hi // unsigned , default = 160
6832 //Bit 15:12 reg_matnr_mtnb_brt_limt_lo // unsigned , default = 6
6833 //Bit 11: 8 reg_matnr_mtnb_brt_slop_lo // unsigned , default = 6
6834 //Bit 7: 0 reg_matnr_mtnb_brt_thrd_lo // unsigned , default = 100
6835 //========== nr2_tnr_regs register end ==========//
6836 // synopsys translate_off
6837 // synopsys translate_on
6838 //
6839 // Closing file: nr2_regs.h
6840 //
6841 #define DI_EI_DRT_CTRL (0x1778)
6842 #define P_DI_EI_DRT_CTRL (volatile uint32_t *)((0x1778 << 2) + 0xff900000)
6843 //Bit 31, reg_rectg_en ;u1
6844 //Bit 30, reg_recbld_en ;u1
6845 //Bit 29:28, reg_rectg_ws ;u2
6846 //Bit 27, reserved
6847 //Bit 26:24, reg_abq_margin ;u3
6848 //Bit 23, reserved
6849 //Bit 22:20, reg_trend_mg ;u3
6850 //Bit 19:16, reg_int_d16xc1 ;u4
6851 //Bit 15:14, reserved
6852 //Bit 13: 8, reg_int_chlmt1 ;u6
6853 //Bit 7, reserved
6854 //Bit 6: 4, reg_nscheck_thrd ;u3
6855 //Bit 3, reserved
6856 //Bit 2: 0, reg_horsl_ws ;u3
6857 #define DI_EI_DRT_PIXTH (0x1779)
6858 #define P_DI_EI_DRT_PIXTH (volatile uint32_t *)((0x1779 << 2) + 0xff900000)
6859 //Bit 31:24, reg_min_pix ;u8
6860 //Bit 23:16, reg_max_pix ;u8
6861 //Bit 15: 8, reg_dmaxmin_thrdma ;u8
6862 //Bit 7: 0, reg_dmaxmin_thrdmi ;u8
6863 #define DI_EI_DRT_CORRPIXTH (0x177a)
6864 #define P_DI_EI_DRT_CORRPIXTH (volatile uint32_t *)((0x177a << 2) + 0xff900000)
6865 //Bit 31:24, reg_newcorrpix_maxthrd ;u8
6866 //Bit 23:16, reg_corrpix_diffthrd ;u8
6867 //Bit 15: 8, reg_corrpix_minthrd ;u8
6868 //Bit 7: 0, reg_corrpix_maxthrd ;u8
6869 #define DI_EI_DRT_RECTG_WAVE (0x177b)
6870 #define P_DI_EI_DRT_RECTG_WAVE (volatile uint32_t *)((0x177b << 2) + 0xff900000)
6871 //Bit 31:29, reserved
6872 //Bit 28:24, reg_max_pixwave ;u5
6873 //Bit 23:21, reserved
6874 //Bit 20:16, reg_pix_wave ;u5
6875 //Bit 15:14, reserved
6876 //Bit 13: 8, reg_maxdrt_thrd ;u6
6877 //Bit 7: 0, reg_wave_thrd ;u8
6878 #define DI_EI_DRT_PIX_DIFFTH (0x177c)
6879 #define P_DI_EI_DRT_PIX_DIFFTH (volatile uint32_t *)((0x177c << 2) + 0xff900000)
6880 //Bit 31:24, reg_newraw_thrd ;u8
6881 //Bit 23:16, reg_tb_max_thrd ;u8
6882 //Bit 15: 8, reg_diffpix_thrd ;u8
6883 //Bit 7: 6, reserved
6884 //Bit 5: 0, reg_bilt_trendnumt ;u8
6885 #define DI_EI_DRT_UNBITREND_TH (0x177d)
6886 #define P_DI_EI_DRT_UNBITREND_TH (volatile uint32_t *)((0x177d << 2) + 0xff900000)
6887 //Bit 31:29, reserved
6888 //Bit 28:24, reg_trend_numb ;u5
6889 //Bit 23:21, reserved
6890 //Bit 20:16, reg_bilt_trendnum ;u5
6891 //Bit 15:13, reserved
6892 //Bit 12: 8, reg_unil_trendnumt ;u5
6893 //Bit 7: 5, reserved
6894 //Bit 4: 0, reg_trend_num ;u5
6895 #define NR2_CONV_MODE (0x177f)
6896 #define P_NR2_CONV_MODE (volatile uint32_t *)((0x177f << 2) + 0xff900000)
6897 //Bit 3:2, Conv_c444_mode The format convert mode about 422 to 444 when data read out line buffer
6898 //Bit 1:0, Conv_c422_mode the format convert mode about 444 to 422 when data write to line buffer
6899 //// NR2 REG DEFINE END ////
6900 //// DET 3D REG DEFINE BEGIN ////
6901 //// 8'h34~8'h3f | 8'h80~8'h8f | 0x9a-0x9b
6902 //
6903 // Reading file: det3d_regs.h
6904 //
6905 //// DET 3D REG DEFINE BEGIN ////
6906 //// 8'h34~8'h3f
6907 //// DET 3D REG DEFINE END ////
6908 #define DET3D_MOTN_CFG (0x1734)
6909 #define P_DET3D_MOTN_CFG (volatile uint32_t *)((0x1734 << 2) + 0xff900000)
6910 //Bit 16, reg_det3d_intr_en Det3d interrupt enable
6911 //Bit 9:8, reg_Det3D_Motion_Mode U2 Different mode for Motion Calculation of Luma and Chroma:
6912 // 0: MotY, 1: (2*MotY + (MotU + MotV))/4; 2: Max(MotY, MotU,MotV); 3:Max(MotY, (MotU+MotV)/2)
6913 //Bit 7:4, reg_Det3D_Motion_Core_Rate U4 K Rate to Edge (HV) details for coring of Motion Calculations, normalized to 32
6914 //Bit 3:0, reg_Det3D_Motion_Core_Thrd U4 2X: static coring value for Motion Detection.
6915 #define DET3D_CB_CFG (0x1735)
6916 #define P_DET3D_CB_CFG (volatile uint32_t *)((0x1735 << 2) + 0xff900000)
6917 //Bit 7:4, reg_Det3D_ChessBd_HV_ofst U4, Noise immune offset for Horizotnal or vertical combing detection.
6918 //Bit 3:0, reg_Det3D_ChessBd_NHV_ofst U4, Noise immune offset for NON-Horizotnal or vertical combing detection.
6919 #define DET3D_SPLT_CFG (0x1736)
6920 #define P_DET3D_SPLT_CFG (volatile uint32_t *)((0x1736 << 2) + 0xff900000)
6921 //Bit 7:4, reg_Det3D_SplitValid_ratio U4, Ratio between max_value and the avg_value of the edge mapping for split line valid detection.
6922 // The smaller of this value, the easier of the split line detected.
6923 //Bit 3:0, reg_Det3D_AvgIdx_ratio U4, Ratio to the avg_value of the edge mapping for split line position estimation.
6924 // The smaller of this value, the more samples will be added to the estimation.
6925 #define DET3D_HV_MUTE (0x1737)
6926 #define P_DET3D_HV_MUTE (volatile uint32_t *)((0x1737 << 2) + 0xff900000)
6927 //Bit 23:20, reg_Det3D_Edge_Ver_Mute U4 X2: Horizontal pixels to be mute from H/V Edge calculation Top and Bottom border part.
6928 //Bit 19:16, reg_Det3D_Edge_Hor_Mute U4 X2: Horizontal pixels to be mute from H/V Edge calculation Left and right border part.
6929 //Bit 15:12, reg_Det3D_ChessBd_Ver_Mute U4 X2: Horizontal pixels to be mute from ChessBoard statistics calculation in middle part
6930 //Bit 11:8, reg_Det3D_ChessBd_Hor_Mute U4 X2: Horizontal pixels to be mute from ChessBoard statistics calculation in middle part
6931 //Bit 7:4, reg_Det3D_STA8X8_Ver_Mute U4 1X: Vertical pixels to be mute from 8x8 statistics calculation in each block.
6932 //Bit 3:0, reg_Det3D_STA8X8_Hor_Mute U4 1X: Horizontal pixels to be mute from 8x8 statistics calculation in each block.
6933 #define DET3D_MAT_STA_P1M1 (0x1738)
6934 #define P_DET3D_MAT_STA_P1M1 (volatile uint32_t *)((0x1738 << 2) + 0xff900000)
6935 //Bit 31:24, reg_Det3D_STA8X8_P1_K0_R8 U8 SAD to SAI ratio to decide P1, normalized to 256 (0.8)
6936 //Bit 23:16, reg_Det3D_STA8X8_P1_K1_R7 U8 SAD to ENG ratio to decide P1, normalized to 128 (0.5)
6937 //Bit 15:8, reg_Det3D_STA8X8_M1_K0_R6 U8 SAD to SAI ratio to decide M1, normalized to 64 (1.1)
6938 //Bit 7:0, reg_Det3D_STA8X8_M1_K1_R6 U8 SAD to ENG ratio to decide M1, normalized to 64 (0.8)
6939 #define DET3D_MAT_STA_P1TH (0x1739)
6940 #define P_DET3D_MAT_STA_P1TH (volatile uint32_t *)((0x1739 << 2) + 0xff900000)
6941 //Bit 23:16, reg_Det3D_STAYUV_P1_TH_L4 U8 SAD to ENG Thrd offset to decide P1, X16 (100)
6942 //Bit 15:8, reg_Det3D_STAEDG_P1_TH_L4 U8 SAD to ENG Thrd offset to decide P1, X16 (80)
6943 //Bit 7:0, reg_Det3D_STAMOT_P1_TH_L4 U8 SAD to ENG Thrd offset to decide P1, X16 (48)
6944 #define DET3D_MAT_STA_M1TH (0x173a)
6945 #define P_DET3D_MAT_STA_M1TH (volatile uint32_t *)((0x173a << 2) + 0xff900000)
6946 //Bit 23:16, reg_Det3D_STAYUV_M1_TH_L4 U8 SAD to ENG Thrd offset to decide M1, X16 (100)
6947 //Bit 15:8, reg_Det3D_STAEDG_M1_TH_L4 U8 SAD to ENG Thrd offset to decide M1, X16 (80)
6948 //Bit 7:0, reg_Det3D_STAMOT_M1_TH_L4 U8 SAD to ENG Thrd offset to decide M1, X16 (64)
6949 #define DET3D_MAT_STA_RSFT (0x173b)
6950 #define P_DET3D_MAT_STA_RSFT (volatile uint32_t *)((0x173b << 2) + 0xff900000)
6951 //Bit 5:4, reg_Det3D_STAYUV_RSHFT U2 YUV statistics SAD and SAI calculation result right shift bits to accommodate the 12bits clipping:
6952 // 0: mainly for images <=720x480: 1: mainly for images <=1366x768: 2: mainly for images <=1920X1080: 2; 3: other higher resolutions
6953 //Bit 3:2, reg_Det3D_STAEDG_RSHFT U2 Horizontal and Vertical Edge Statistics SAD and SAI calculation result right shift bits to accommodate the 12bits clipping:
6954 // 0: mainly for images <=720x480: 1: mainly for images <=1366x768: 2: mainly for images <=1920X1080: 2; 3: other higher resolutions
6955 //Bit 1:0, reg_Det3D_STAMOT_RSHFT U2 Motion SAD and SAI calculation result right shift bits to accommodate the 12bits clipping:
6956 // 0: mainly for images <=720x480: 1: mainly for images <=1366x768: 2: mainly for images <=1920X1080: 2; 3: other higher resolutions
6957 #define DET3D_MAT_SYMTC_TH (0x173c)
6958 #define P_DET3D_MAT_SYMTC_TH (volatile uint32_t *)((0x173c << 2) + 0xff900000)
6959 //Bit 31:24, reg_Det3D_STALUM_symtc_Th U8 threshold to decide if the Luma statistics is TB or LR symmetric.
6960 //Bit 23:16, reg_Det3D_STACHR_symtc_Th U8 threshold to decide if the Chroma (UV) statistics is TB or LR symmetric.
6961 //Bit 15:8, reg_Det3D_STAEDG_symtc_Th U8 threshold to decide if the Horizontal and Vertical Edge statistics is TB or LR symmetric.
6962 //Bit 7:0, reg_Det3D_STAMOT_symtc_Th U8 threshold to decide if the Motion statistics is TB or LR symmetric.
6963 #define DET3D_RO_DET_CB_HOR (0x173d)
6964 #define P_DET3D_RO_DET_CB_HOR (volatile uint32_t *)((0x173d << 2) + 0xff900000)
6965 //Bit 31:16, RO_Det3D_ChessBd_NHor_value U16 X64: number of Pixels of Horizontally Surely NOT matching Chessboard pattern.
6966 //Bit 15:0, RO_Det3D_ChessBd_Hor_value U16 X64: number of Pixels of Horizontally Surely matching Chessboard pattern.
6967 #define DET3D_RO_DET_CB_VER (0x173e)
6968 #define P_DET3D_RO_DET_CB_VER (volatile uint32_t *)((0x173e << 2) + 0xff900000)
6969 //Bit 31:16, RO_Det3D_ChessBd_NVer_value U16 X64: number of Pixels of Vertically Surely NOT matching Chessboard pattern.
6970 //Bit 15:0, RO_Det3D_ChessBd_Ver_value U16 X64: number of Pixels of Vertically Surely matching Chessboard pattern.
6971 #define DET3D_RO_SPLT_HT (0x173f)
6972 #define P_DET3D_RO_SPLT_HT (volatile uint32_t *)((0x173f << 2) + 0xff900000)
6973 //Bit 24, RO_Det3D_Split_HT_valid U1 horizontal LR split border detected valid signal for top half picture
6974 //Bit 20:16, RO_Det3D_Split_HT_pxnum U5 number of pixels included for the LR split position estimation for top half picture
6975 //Bit 9:0, RO_Det3D_Split_HT_idxX4 S10 X4: horizontal pixel shifts of LR split position to the (ColMax/2) for top half picture
6976 //// DET 3D REG DEFINE BEGIN ////
6977 //// 8'h80~8'h8f
6978 #define DET3D_RO_SPLT_HB (0x1780)
6979 #define P_DET3D_RO_SPLT_HB (volatile uint32_t *)((0x1780 << 2) + 0xff900000)
6980 //Bit 24, RO_Det3D_Split_HB_valid U1 horizontal LR split border detected valid signal for top half picture
6981 //Bit 20:16, RO_Det3D_Split_HB_pxnum U5 number of pixels included for the LR split position estimation for top half picture
6982 //Bit 9: 0, RO_Det3D_Split_HB_idxX4 S10 X4: horizontal pixel shifts of LR split position to the (ColMax/2) for top half picture
6983 #define DET3D_RO_SPLT_VL (0x1781)
6984 #define P_DET3D_RO_SPLT_VL (volatile uint32_t *)((0x1781 << 2) + 0xff900000)
6985 //Bit 24, RO_Det3D_Split_VL_valid U1 horizontal LR split border detected valid signal for top half picture
6986 //Bit 20:16, RO_Det3D_Split_VL_pxnum U5 number of pixels included for the LR split position estimation for top half picture
6987 //Bit 9: 0, RO_Det3D_Split_VL_idxX4 S10 X4: horizontal pixel shifts of LR split position to the (ColMax/2) for top half picture
6988 #define DET3D_RO_SPLT_VR (0x1782)
6989 #define P_DET3D_RO_SPLT_VR (volatile uint32_t *)((0x1782 << 2) + 0xff900000)
6990 //Bit 24 , RO_Det3D_Split_VR_valid U1 horizontal LR split border detected valid signal for top half picture
6991 //Bit 20:16, RO_Det3D_Split_VR_pxnum U5 number of pixels included for the LR split position estimation for top half picture
6992 //Bit 9: 0, RO_Det3D_Split_VR_idxX4 S10 X4: horizontal pixel shifts of LR split position to the (ColMax/2) for top half picture
6993 #define DET3D_RO_MAT_LUMA_LR (0x1783)
6994 #define P_DET3D_RO_MAT_LUMA_LR (volatile uint32_t *)((0x1783 << 2) + 0xff900000)
6995 //Bit 15:0, RO_Luma_LR_score S2*8 LUMA statistics left right decision score for each band (8bands vertically),
6996 // it can be -1/0/1:-1: most likely not LR symmetric 0: not sure 1: most likely LR symmetric
6997 //Bit 7:0, RO_Luma_LR_symtc U1*8 Luma statistics left right pure symmetric for each band (8bands vertically),
6998 // it can be 0/1: 0: not sure 1: most likely LR is pure symmetric
6999 //Bit 4:0, RO_Luma_LR_sum S5 Total score of 8x8 Luma statistics for LR like decision,
7000 // the larger this score, the more confidence that this is a LR 3D video. It is sum of RO_Luma_LR_score[0~7]
7001 #define DET3D_RO_MAT_LUMA_TB (0x1784)
7002 #define P_DET3D_RO_MAT_LUMA_TB (volatile uint32_t *)((0x1784 << 2) + 0xff900000)
7003 //Bit 15:0, RO_Luma_TB_score S2*8 LUMA statistics Top/Bottom decision score for each band (8bands Horizontally),
7004 //Bit 7:0, RO_Luma_TB_symtc Luma statistics Top/Bottompure symmetric for each band (8bands Horizontally),
7005 //Bit 4:0, RO_Luma_TB_sum Total score of 8x8 Luma statistics for TB like decision,
7006 #define DET3D_RO_MAT_CHRU_LR (0x1785)
7007 #define P_DET3D_RO_MAT_CHRU_LR (volatile uint32_t *)((0x1785 << 2) + 0xff900000)
7008 //Bit 15:0, RO_ChrU_LR_score S2*8 LUMA statistics left right decision score for each band (8bands vertically),
7009 //Bit 7:0, RO_ChrU_LR_symtc CHRU statistics left right pure symmetric for each band (8bands vertically),
7010 //Bit 4:0, RO_ChrU_LR_sum Total score of 8x8 ChrU statistics for LR like decision,
7011 #define DET3D_RO_MAT_CHRU_TB (0x1786)
7012 #define P_DET3D_RO_MAT_CHRU_TB (volatile uint32_t *)((0x1786 << 2) + 0xff900000)
7013 //Bit 15:0, RO_ChrU_TB_score S2*8 CHRU statistics Top/Bottom decision score for each band (8bands Horizontally)
7014 //Bit 7:0, RO_ChrU_TB_symtc CHRU statistics Top/Bottompure symmetric for each band (8bands Horizontally)
7015 //Bit 4:0, RO_ChrU_TB_sum Total score of 8x8 ChrU statistics for TB like decision
7016 #define DET3D_RO_MAT_CHRV_LR (0x1787)
7017 #define P_DET3D_RO_MAT_CHRV_LR (volatile uint32_t *)((0x1787 << 2) + 0xff900000)
7018 //Bit 15:0, RO_ChrV_LR_score S2*8 CHRUstatistics left right decision score for each band (8bands vertically)
7019 //Bit 7:0, RO_ChrV_LR_symtc CHRV statistics left right pure symmetric for each band (8bands vertically)
7020 //Bit 4:0, RO_ChrV_LR_sum Total score of 8x8 ChrV statistics for LR like decision
7021 #define DET3D_RO_MAT_CHRV_TB (0x1788)
7022 #define P_DET3D_RO_MAT_CHRV_TB (volatile uint32_t *)((0x1788 << 2) + 0xff900000)
7023 //Bit 15:0, RO_ChrV_TB_score CHRV statistics Top/Bottom decision score for each band (8bands Horizontally)
7024 //Bit 7:0, RO_ChrV_TB_symtc CHRV statistics Top/Bottompure symmetric for each band (8bands Horizontally)
7025 //Bit 4:0, RO_ChrV_TB_sum Total score of 8x8 ChrV statistics for TB like decision
7026 #define DET3D_RO_MAT_HEDG_LR (0x1789)
7027 #define P_DET3D_RO_MAT_HEDG_LR (volatile uint32_t *)((0x1789 << 2) + 0xff900000)
7028 //Bit 15:0, RO_Hedg_LR_score Horizontal Edge statistics left right decision score for each band (8bands vertically)
7029 //Bit 7:0, RO_Hedg_LR_symtc Horizontal Edge statistics left right pure symmetric for each band (8bands vertically)
7030 //Bit 4:0, RO_Hedg_LR_sum Total score of 8x8 Hedg statistics for LR like decision
7031 #define DET3D_RO_MAT_HEDG_TB (0x178a)
7032 #define P_DET3D_RO_MAT_HEDG_TB (volatile uint32_t *)((0x178a << 2) + 0xff900000)
7033 //Bit 15:0, RO_Hedg_TB_score Horizontal Edge statistics Top/Bottom decision score for each band (8bands Horizontally)
7034 //Bit 7:0, RO_Hedg_TB_symtc Horizontal Edge statistics Top/Bottompure symmetric for each band (8bands Horizontally)
7035 //Bit 4:0, RO_Hedg_TB_sum Total score of 8x8 Hedg statistics for TB like decision
7036 #define DET3D_RO_MAT_VEDG_LR (0x178b)
7037 #define P_DET3D_RO_MAT_VEDG_LR (volatile uint32_t *)((0x178b << 2) + 0xff900000)
7038 //Bit 15:0, RO_Vedg_LR_score Vertical Edge statistics left right decision score for each band (8bands vertically)
7039 //Bit 7:0, RO_Vedg_LR_symtc Vertical Edge statistics left right pure symmetric for each band (8bands vertically)
7040 //Bit 4:0, RO_Vedg_LR_sum Total score of 8x8 Vedg statistics for LR like decision
7041 #define DET3D_RO_MAT_VEDG_TB (0x178c)
7042 #define P_DET3D_RO_MAT_VEDG_TB (volatile uint32_t *)((0x178c << 2) + 0xff900000)
7043 //Bit 15:0, RO_Vedg_TB_score Vertical Edge statistics Top/Bottom decision score for each band (8bands Horizontally)
7044 //Bit 7:0, RO_Vedg_TB_symtc Vertical Edge statistics Top/Bottompure symmetric for each band (8bands Horizontally)
7045 //Bit 4:0, RO_Vedg_TB_sum Total score of 8x8 Vedg statistics for TB like decision
7046 #define DET3D_RO_MAT_MOTN_LR (0x178d)
7047 #define P_DET3D_RO_MAT_MOTN_LR (volatile uint32_t *)((0x178d << 2) + 0xff900000)
7048 //Bit 15:0, RO_Motn_LR_score Motion statistics left right decision score for each band (8bands vertically)
7049 //Bit 7:0, RO_Motn_LR_symtc Motion statistics left right pure symmetric for each band (8bands vertically)
7050 //Bit 4:0, RO_Motn_LR_sum Total score of 8x8 Motion statistics for LR like decision
7051 #define DET3D_RO_MAT_MOTN_TB (0x178e)
7052 #define P_DET3D_RO_MAT_MOTN_TB (volatile uint32_t *)((0x178e << 2) + 0xff900000)
7053 //Bit 15:0, RO_Motn_TB_score Motion statistics Top/Bottom decision score for each band (8bands Horizontally)
7054 //Bit 7:0, RO_Motn_TB_symtc Motion statistics Top/Bottompure symmetric for each band (8bands Horizontally)
7055 //Bit 4:0, RO_Motn_TB_sum Total score of 8x8 Motion statistics for TB like decision
7056 #define DET3D_RO_FRM_MOTN (0x178f)
7057 #define P_DET3D_RO_FRM_MOTN (volatile uint32_t *)((0x178f << 2) + 0xff900000)
7058 //Bit 15:0, RO_Det3D_Frame_Motion U16 frame based motion value sum for still image decision in FW.
7059 /// mat ram read enter addr
7060 #define DET3D_RAMRD_ADDR_PORT (0x179a)
7061 #define P_DET3D_RAMRD_ADDR_PORT (volatile uint32_t *)((0x179a << 2) + 0xff900000)
7062 #define DET3D_RAMRD_DATA_PORT (0x179b)
7063 #define P_DET3D_RAMRD_DATA_PORT (volatile uint32_t *)((0x179b << 2) + 0xff900000)
7064 //
7065 // Closing file: det3d_regs.h
7066 //
7067 // `define DET3D_RO_SPLT_HB 8'h80
7068 // //Bit 24, RO_Det3D_Split_HB_valid U1 horizontal LR split border detected valid signal for top half picture
7069 // //Bit 20:16, RO_Det3D_Split_HB_pxnum U5 number of pixels included for the LR split position estimation for top half picture
7070 // //Bit 9: 0, RO_Det3D_Split_HB_idxX4 S10 X4: horizontal pixel shifts of LR split position to the (ColMax/2) for top half picture
7071 // `define DET3D_RO_SPLT_VL 8'h81
7072 // //Bit 24, RO_Det3D_Split_VL_valid U1 horizontal LR split border detected valid signal for top half picture
7073 // //Bit 20:16, RO_Det3D_Split_VL_pxnum U5 number of pixels included for the LR split position estimation for top half picture
7074 // //Bit 9: 0, RO_Det3D_Split_VL_idxX4 S10 X4: horizontal pixel shifts of LR split position to the (ColMax/2) for top half picture
7075 // `define DET3D_RO_SPLT_VR 8'h82
7076 // //Bit 24 , RO_Det3D_Split_VR_valid U1 horizontal LR split border detected valid signal for top half picture
7077 // //Bit 20:16, RO_Det3D_Split_VR_pxnum U5 number of pixels included for the LR split position estimation for top half picture
7078 // //Bit 9: 0, RO_Det3D_Split_VR_idxX4 S10 X4: horizontal pixel shifts of LR split position to the (ColMax/2) for top half picture
7079 // `define DET3D_RO_MAT_LUMA_LR 8'h83
7080 // //Bit 15:0, RO_Luma_LR_score S2*8 LUMA statistics left right decision score for each band (8bands vertically),
7081 // // it can be -1/0/1:-1: most likely not LR symmetric 0: not sure 1: most likely LR symmetric
7082 // //Bit 7:0, RO_Luma_LR_symtc U1*8 Luma statistics left right pure symmetric for each band (8bands vertically),
7083 // // it can be 0/1: 0: not sure 1: most likely LR is pure symmetric
7084 // //Bit 4:0, RO_Luma_LR_sum S5 Total score of 8x8 Luma statistics for LR like decision,
7085 // // the larger this score, the more confidence that this is a LR 3D video. It is sum of RO_Luma_LR_score[0~7]
7086 // `define DET3D_RO_MAT_LUMA_TB 8'h84
7087 // //Bit 15:0, RO_Luma_TB_score S2*8 LUMA statistics Top/Bottom decision score for each band (8bands Horizontally),
7088 // //Bit 7:0, RO_Luma_TB_symtc Luma statistics Top/Bottompure symmetric for each band (8bands Horizontally),
7089 // //Bit 4:0, RO_Luma_TB_sum Total score of 8x8 Luma statistics for TB like decision,
7090 // `define DET3D_RO_MAT_CHRU_LR 8'h85
7091 // //Bit 15:0, RO_ChrU_LR_score S2*8 LUMA statistics left right decision score for each band (8bands vertically),
7092 // //Bit 7:0, RO_ChrU_LR_symtc CHRU statistics left right pure symmetric for each band (8bands vertically),
7093 // //Bit 4:0, RO_ChrU_LR_sum Total score of 8x8 ChrU statistics for LR like decision,
7094 // `define DET3D_RO_MAT_CHRU_TB 8'h86
7095 // //Bit 15:0, RO_ChrU_TB_score S2*8 CHRU statistics Top/Bottom decision score for each band (8bands Horizontally)
7096 // //Bit 7:0, RO_ChrU_TB_symtc CHRU statistics Top/Bottompure symmetric for each band (8bands Horizontally)
7097 // //Bit 4:0, RO_ChrU_TB_sum Total score of 8x8 ChrU statistics for TB like decision
7098 // `define DET3D_RO_MAT_CHRV_LR 8'h87
7099 // //Bit 15:0, RO_ChrV_LR_score S2*8 CHRUstatistics left right decision score for each band (8bands vertically)
7100 // //Bit 7:0, RO_ChrV_LR_symtc CHRV statistics left right pure symmetric for each band (8bands vertically)
7101 // //Bit 4:0, RO_ChrV_LR_sum Total score of 8x8 ChrV statistics for LR like decision
7102 // `define DET3D_RO_MAT_CHRV_TB 8'h88
7103 // //Bit 15:0, RO_ChrV_TB_score CHRV statistics Top/Bottom decision score for each band (8bands Horizontally)
7104 // //Bit 7:0, RO_ChrV_TB_symtc CHRV statistics Top/Bottompure symmetric for each band (8bands Horizontally)
7105 // //Bit 4:0, RO_ChrV_TB_sum Total score of 8x8 ChrV statistics for TB like decision
7106 // `define DET3D_RO_MAT_HEDG_LR 8'h89
7107 // //Bit 15:0, RO_Hedg_LR_score Horizontal Edge statistics left right decision score for each band (8bands vertically)
7108 // //Bit 7:0, RO_Hedg_LR_symtc Horizontal Edge statistics left right pure symmetric for each band (8bands vertically)
7109 // //Bit 4:0, RO_Hedg_LR_sum Total score of 8x8 Hedg statistics for LR like decision
7110 // `define DET3D_RO_MAT_HEDG_TB 8'h8a
7111 // //Bit 15:0, RO_Hedg_TB_score Horizontal Edge statistics Top/Bottom decision score for each band (8bands Horizontally)
7112 // //Bit 7:0, RO_Hedg_TB_symtc Horizontal Edge statistics Top/Bottompure symmetric for each band (8bands Horizontally)
7113 // //Bit 4:0, RO_Hedg_TB_sum Total score of 8x8 Hedg statistics for TB like decision
7114 // `define DET3D_RO_MAT_VEDG_LR 8'h8b
7115 // //Bit 15:0, RO_Vedg_LR_score Vertical Edge statistics left right decision score for each band (8bands vertically)
7116 // //Bit 7:0, RO_Vedg_LR_symtc Vertical Edge statistics left right pure symmetric for each band (8bands vertically)
7117 // //Bit 4:0, RO_Vedg_LR_sum Total score of 8x8 Vedg statistics for LR like decision
7118 // `define DET3D_RO_MAT_VEDG_TB 8'h8c
7119 // //Bit 15:0, RO_Vedg_TB_score Vertical Edge statistics Top/Bottom decision score for each band (8bands Horizontally)
7120 // //Bit 7:0, RO_Vedg_TB_symtc Vertical Edge statistics Top/Bottompure symmetric for each band (8bands Horizontally)
7121 // //Bit 4:0, RO_Vedg_TB_sum Total score of 8x8 Vedg statistics for TB like decision
7122 // `define DET3D_RO_MAT_MOTN_LR 8'h8d
7123 // //Bit 15:0, RO_Motn_LR_score Motion statistics left right decision score for each band (8bands vertically)
7124 // //Bit 7:0, RO_Motn_LR_symtc Motion statistics left right pure symmetric for each band (8bands vertically)
7125 // //Bit 4:0, RO_Motn_LR_sum Total score of 8x8 Motion statistics for LR like decision
7126 // `define DET3D_RO_MAT_MOTN_TB 8'h8e
7127 // //Bit 15:0, RO_Motn_TB_score Motion statistics Top/Bottom decision score for each band (8bands Horizontally)
7128 // //Bit 7:0, RO_Motn_TB_symtc Motion statistics Top/Bottompure symmetric for each band (8bands Horizontally)
7129 // //Bit 4:0, RO_Motn_TB_sum Total score of 8x8 Motion statistics for TB like decision
7130 // `define DET3D_RO_FRM_MOTN 8'h8f
7131 // //Bit 15:0, RO_Det3D_Frame_Motion U16 frame based motion value sum for still image decision in FW.
7132 #define DI_EI_CTRL10 (0x1793)
7133 #define P_DI_EI_CTRL10 (volatile uint32_t *)((0x1793 << 2) + 0xff900000)
7134 //bit 31:28, reg_ei_caldrt_hstrrgchk_drtth
7135 //bit 27:24, reg_ei_caldrt_hstrrgchk_frcverthrd
7136 //bit 23:20, reg_ei_caldrt_hstrrgchk_mg
7137 //bit 19, reg_ei_caldrt_hstrrgchk_1sidnul
7138 //bit 18, reg_ei_caldrt_hstrrgchk_excpcnf
7139 //bit 17:16, reg_ei_caldrt_hstrrgchk_ws
7140 //bit 15, reg_ei_caldrt_hstrrgchk_en
7141 //bit 14:13, reg_ei_caldrt_hpncheck_mode
7142 //bit 12, reg_ei_caldrt_hpncheck_mute
7143 //bit 11:9, reg_ei_caldrt_hcnfcheck_mg2
7144 //bit 8:6, reg_ei_caldrt_hcnfcheck_mg1
7145 //bit 5:4, reg_ei_caldrt_hcnfcheck_mode
7146 //bit 3:0, reg_ei_caldrt_hcnfcheck_mg2
7147 #define DI_NR_1_CTRL0 (0x1794)
7148 #define P_DI_NR_1_CTRL0 (volatile uint32_t *)((0x1794 << 2) + 0xff900000)
7149 #define DI_NR_1_CTRL1 (0x1795)
7150 #define P_DI_NR_1_CTRL1 (volatile uint32_t *)((0x1795 << 2) + 0xff900000)
7151 #define DI_NR_1_CTRL2 (0x1796)
7152 #define P_DI_NR_1_CTRL2 (volatile uint32_t *)((0x1796 << 2) + 0xff900000)
7153 #define DI_NR_1_CTRL3 (0x1797)
7154 #define P_DI_NR_1_CTRL3 (volatile uint32_t *)((0x1797 << 2) + 0xff900000)
7155 #define DI_EI_XWIN0 (0x1798)
7156 #define P_DI_EI_XWIN0 (volatile uint32_t *)((0x1798 << 2) + 0xff900000)
7157 //bit 27:16, ei_xend0
7158 //bit 11:0, ei_xstart0
7159 #define DI_EI_XWIN1 (0x1799)
7160 #define P_DI_EI_XWIN1 (volatile uint32_t *)((0x1799 << 2) + 0xff900000)
7161 /// mat ram read enter addr
7162 // `define DET3D_RAMRD_ADDR_PORT 8'h9a
7163 // `define DET3D_RAMRD_DATA_PORT 8'h9b
7164 #define NR2_CFR_PARA_CFG0 (0x179c)
7165 #define P_NR2_CFR_PARA_CFG0 (volatile uint32_t *)((0x179c << 2) + 0xff900000)
7166 //Bit 8, reg_CFR_CurDif_luma_mode Current Field Top/Bot line Luma difference calculation mode
7167 //Bit 7:6, reg_MACFR_frm_phase U2 This will be a field based phase register that need to be set by FW phase to phase:
7168 // this will be calculated based on dbdr_phase of the specific line of this frame.
7169 // u1: dbdr_phase=1, center line is DB in current line; dbdr_phase=2, center line is Dr in current line;
7170 //Bit 5:4, reg_CFR_CurDif_tran_mode U2 Current Field Top/Bot line Luma/Chroma transition level calculation mode,
7171 //Bit 3:2, reg_CFR_alpha_mode U2 Alpha selection mode for CFR block from curAlp and motAlp i.e. 0: motAlp; 1: (motAlp+curAlp)/2; 2: min(motAlp,curAlp); 3: max(motAlp,curAlp);
7172 //Bit 1:0, reg_CFR_Motion_Luma_mode U2 LumaMotion Calculation mode for MA-CFR. 0: top/bot Lumma motion; 1: middle Luma Motion 2: top/bot + middle motion; 3: max(top/tot motion, middle motion)
7173 #define NR2_CFR_PARA_CFG1 (0x179d)
7174 #define P_NR2_CFR_PARA_CFG1 (volatile uint32_t *)((0x179d << 2) + 0xff900000)
7175 //Bit 23:16, reg_CFR_alpha_gain gain to map muxed curAlp and motAlp to alpha that will be used for final blending.
7176 //Bit 15: 8, reg_CFR_Motion_ofst Offset to Motion to calculate the motAlp, e,g:motAlp= reg_CFR_Motion_ofst- Motion;This register can be seen as the level of motion that we consider it at moving.
7177 //Bit 7: 0, reg_CFR_CurDif_gain gain to CurDif to map to alpha, normalized to 32;
7178 //// DET 3D REG DEFINE END ////
7179 #define DI_EI_CTRL11 (0x179e)
7180 #define P_DI_EI_CTRL11 (volatile uint32_t *)((0x179e << 2) + 0xff900000)
7181 //bit 30:29, reg_ei_amb_detect_mode
7182 //bit 28:24, reg_ei_amb_detect_winth
7183 //bit 23:21, reg_ei_amb_decide_rppth
7184 //bit 20:19, reg_ei_retime_lastmappncnfltchk_drtth
7185 //bit 18:16, reg_ei_retime_lastmappncnfltchk_mode
7186 //bit 15:14, reg_ei_retime_lastmapvertfrcchk_mode
7187 //bit 13:12, reg_ei_retime_lastvertfrcchk_mode
7188 //bit 11:8, reg_ei_retime_lastpnchk_drtth
7189 //bit 6, reg_ei_retime_lastpnchk_en
7190 //bit 5:4, reg_ei_retime_mode
7191 //bit 3, reg_ei_retime_last_en
7192 //bit 2, reg_ei_retime_ab_en
7193 //bit 1, reg_ei_caldrt_hstrvertfrcchk_en
7194 //bit 0, reg_ei_caldrt_hstrrgchk_mode
7195 #define DI_EI_CTRL12 (0x179f)
7196 #define P_DI_EI_CTRL12 (volatile uint32_t *)((0x179f << 2) + 0xff900000)
7197 //bit 31:28, reg_ei_drtdelay2_lmt
7198 //bit 27:26, reg_ei_drtdelay2_notver_lrwin
7199 //bit 25:24, reg_ei_drtdelay_mode
7200 //bit 23, reg_ei_drtdelay2_mode
7201 //bit 22:20, reg_ei_assign_xla_signm0th
7202 //bit 19, reg_ei_assign_pkbiasvert_en
7203 //bit 18, reg_ei_assign_xla_en
7204 //bit 17:16, reg_ei_assign_xla_mode
7205 //bit 15:12, reg_ei_assign_nlfilter_magin
7206 //bit 11:8, reg_ei_localsearch_maxrange
7207 //bit 7:4, reg_ei_xla_drtth
7208 //bit 3:0, reg_ei_flatmsad_thrd
7209 #define DI_CONTWR_X (0x17a0)
7210 #define P_DI_CONTWR_X (volatile uint32_t *)((0x17a0 << 2) + 0xff900000)
7211 #define DI_CONTWR_Y (0x17a1)
7212 #define P_DI_CONTWR_Y (volatile uint32_t *)((0x17a1 << 2) + 0xff900000)
7213 #define DI_CONTWR_CTRL (0x17a2)
7214 #define P_DI_CONTWR_CTRL (volatile uint32_t *)((0x17a2 << 2) + 0xff900000)
7215 #define DI_CONTPRD_X (0x17a3)
7216 #define P_DI_CONTPRD_X (volatile uint32_t *)((0x17a3 << 2) + 0xff900000)
7217 #define DI_CONTPRD_Y (0x17a4)
7218 #define P_DI_CONTPRD_Y (volatile uint32_t *)((0x17a4 << 2) + 0xff900000)
7219 #define DI_CONTP2RD_X (0x17a5)
7220 #define P_DI_CONTP2RD_X (volatile uint32_t *)((0x17a5 << 2) + 0xff900000)
7221 #define DI_CONTP2RD_Y (0x17a6)
7222 #define P_DI_CONTP2RD_Y (volatile uint32_t *)((0x17a6 << 2) + 0xff900000)
7223 #define DI_CONTRD_CTRL (0x17a7)
7224 #define P_DI_CONTRD_CTRL (volatile uint32_t *)((0x17a7 << 2) + 0xff900000)
7225 #define DI_EI_CTRL13 (0x17a8)
7226 #define P_DI_EI_CTRL13 (volatile uint32_t *)((0x17a8 << 2) + 0xff900000)
7227 //bit 27:24, reg_ei_int_drt2x_chrdrt_limit
7228 //bit 23:20, reg_ei_int_drt16x_core
7229 //bit 19:16, reg_ei_int_drtdelay2_notver_cancv
7230 //bit 15:8, reg_ei_int_drtdelay2_notver_sadth
7231 //bit 7:0, reg_ei_int_drtdelay2_vlddrt_sadth
7232 #define DI_MTN_1_CTRL6 (0x17a9)
7233 #define P_DI_MTN_1_CTRL6 (volatile uint32_t *)((0x17a9 << 2) + 0xff900000)
7234 //bit 31:24, mtn_m1b_extnd
7235 //bit 23:16, mtn_m1b_errod
7236 //bit 15: 8, mtn_core_ykinter
7237 //bit 7: 0, mtn_core_ckinter
7238 #define DI_MTN_1_CTRL7 (0x17aa)
7239 #define P_DI_MTN_1_CTRL7 (volatile uint32_t *)((0x17aa << 2) + 0xff900000)
7240 //bit 31:24, mtn_core_mxcmby
7241 //bit 23:16, mtn_core_mxcmbc
7242 //bit 15: 8, mtn_core_y
7243 //bit 7: 0, mtn_core_c
7244 #define DI_MTN_1_CTRL8 (0x17ab)
7245 #define P_DI_MTN_1_CTRL8 (volatile uint32_t *)((0x17ab << 2) + 0xff900000)
7246 //bit 31:24, mtn_fcore_ykinter
7247 //bit 23:16, mtn_fcore_ckinter
7248 //bit 15: 8, mtn_fcore_ykintra
7249 //bit 7: 0, mtn_fcore_ckintra
7250 #define DI_MTN_1_CTRL9 (0x17ac)
7251 #define P_DI_MTN_1_CTRL9 (volatile uint32_t *)((0x17ac << 2) + 0xff900000)
7252 //bit 31:24, mtn_fcore_2yrate
7253 //bit 23:16, mtn_fcore_2crate
7254 //bit 15: 8, mtn_fcore_y
7255 //bit 7: 0, mtn_fcore_c
7256 #define DI_MTN_1_CTRL10 (0x17ad)
7257 #define P_DI_MTN_1_CTRL10 (volatile uint32_t *)((0x17ad << 2) + 0xff900000)
7258 //bit 27:24, mtn_motfld0
7259 //bit 19:16, mtn_stlfld0
7260 //bit 11: 8, mtn_motfld1
7261 //bit 3: 0, mtn_stlfld1
7262 #define DI_MTN_1_CTRL11 (0x17ae)
7263 #define P_DI_MTN_1_CTRL11 (volatile uint32_t *)((0x17ae << 2) + 0xff900000)
7264 //bit 27:24, mtn_smotevn
7265 //bit 20:16, mtn_smotodd
7266 //bit 11: 8, mtn_sstlevn
7267 //bit 4: 0, mtn_sstlodd
7268 #define DI_MTN_1_CTRL12 (0x17af)
7269 #define P_DI_MTN_1_CTRL12 (volatile uint32_t *)((0x17af << 2) + 0xff900000)
7270 //bit 31:24, mtn_mgain
7271 //bit 17:16, mtn_mmode
7272 //bit 15: 8, mtn_sthrd
7273 //bit 4: 0, mtn_sgain
7274 #define DI_NRWR_X (0x17c0)
7275 #define P_DI_NRWR_X (volatile uint32_t *)((0x17c0 << 2) + 0xff900000)
7276 #define DI_NRWR_Y (0x17c1)
7277 #define P_DI_NRWR_Y (volatile uint32_t *)((0x17c1 << 2) + 0xff900000)
7278 //bit 31:30 nrwr_words_lim
7279 //bit 29 nrwr_rev_y
7280 //bit 28:16 nrwr_start_y
7281 //bit 15 nrwr_ext_en
7282 //bit 12:0 nrwr_end_y
7283 #define DI_NRWR_CTRL (0x17c2)
7284 #define P_DI_NRWR_CTRL (volatile uint32_t *)((0x17c2 << 2) + 0xff900000)
7285 //bit 31 pending_ddr_wrrsp_diwr
7286 //bit 30 nrwr_reg_swap
7287 //bit 29:26 nrwr_burst_lim
7288 //bit 25 nrwr_canvas_syncen
7289 //bit 24 nrwr_no_clk_gate
7290 //bit 23:22 nrwr_rgb_mode 0:422 to one canvas;1:4:4:4 to one canvas;
7291 //bit 21:20 nrwr_hconv_mode
7292 //bit 19:18 nrwr_vconv_mode
7293 //bit 17 nrwr_swap_cbcr
7294 //bit 16 nrwr_urgent
7295 //bit 15:8 nrwr_canvas_index_chroma
7296 //bit 7:0 nrwr_canvas_index_luma
7297 #define DI_MTNWR_X (0x17c3)
7298 #define P_DI_MTNWR_X (volatile uint32_t *)((0x17c3 << 2) + 0xff900000)
7299 #define DI_MTNWR_Y (0x17c4)
7300 #define P_DI_MTNWR_Y (volatile uint32_t *)((0x17c4 << 2) + 0xff900000)
7301 #define DI_MTNWR_CTRL (0x17c5)
7302 #define P_DI_MTNWR_CTRL (volatile uint32_t *)((0x17c5 << 2) + 0xff900000)
7303 #define DI_DIWR_X (0x17c6)
7304 #define P_DI_DIWR_X (volatile uint32_t *)((0x17c6 << 2) + 0xff900000)
7305 #define DI_DIWR_Y (0x17c7)
7306 #define P_DI_DIWR_Y (volatile uint32_t *)((0x17c7 << 2) + 0xff900000)
7307 //bit 31:30 diwr_words_lim
7308 //bit 29 diwr_rev_y
7309 //bit 28:16 diwr_start_y
7310 //bit 15 diwr_ext_en
7311 //bit 12:0 diwr_end_y
7312 #define DI_DIWR_CTRL (0x17c8)
7313 #define P_DI_DIWR_CTRL (volatile uint32_t *)((0x17c8 << 2) + 0xff900000)
7314 //bit 31 pending_ddr_wrrsp_diwr
7315 //bit 30 diwr_reg_swap
7316 //bit 29:26 diwr_burst_lim
7317 //bit 25 diwr_canvas_syncen
7318 //bit 24 diwr_no_clk_gate
7319 //bit 23:22 diwr_rgb_mode 0:422 to one canvas;1:4:4:4 to one canvas;
7320 //bit 21:20 diwr_hconv_mode
7321 //bit 19:18 diwr_vconv_mode
7322 //bit 17 diwr_swap_cbcr
7323 //bit 16 diwr_urgent
7324 //bit 15:8 diwr_canvas_index_chroma
7325 //bit 7:0 diwr_canvas_index_luma
7326 //`define DI_MTNCRD_X 8'hc9
7327 //`define DI_MTNCRD_Y 8'hca
7328 #define DI_MTNPRD_X (0x17cb)
7329 #define P_DI_MTNPRD_X (volatile uint32_t *)((0x17cb << 2) + 0xff900000)
7330 #define DI_MTNPRD_Y (0x17cc)
7331 #define P_DI_MTNPRD_Y (volatile uint32_t *)((0x17cc << 2) + 0xff900000)
7332 #define DI_MTNRD_CTRL (0x17cd)
7333 #define P_DI_MTNRD_CTRL (volatile uint32_t *)((0x17cd << 2) + 0xff900000)
7334 #define DI_INP_GEN_REG (0x17ce)
7335 #define P_DI_INP_GEN_REG (volatile uint32_t *)((0x17ce << 2) + 0xff900000)
7336 #define DI_INP_CANVAS0 (0x17cf)
7337 #define P_DI_INP_CANVAS0 (volatile uint32_t *)((0x17cf << 2) + 0xff900000)
7338 #define DI_INP_LUMA_X0 (0x17d0)
7339 #define P_DI_INP_LUMA_X0 (volatile uint32_t *)((0x17d0 << 2) + 0xff900000)
7340 #define DI_INP_LUMA_Y0 (0x17d1)
7341 #define P_DI_INP_LUMA_Y0 (volatile uint32_t *)((0x17d1 << 2) + 0xff900000)
7342 #define DI_INP_CHROMA_X0 (0x17d2)
7343 #define P_DI_INP_CHROMA_X0 (volatile uint32_t *)((0x17d2 << 2) + 0xff900000)
7344 #define DI_INP_CHROMA_Y0 (0x17d3)
7345 #define P_DI_INP_CHROMA_Y0 (volatile uint32_t *)((0x17d3 << 2) + 0xff900000)
7346 #define DI_INP_RPT_LOOP (0x17d4)
7347 #define P_DI_INP_RPT_LOOP (volatile uint32_t *)((0x17d4 << 2) + 0xff900000)
7348 #define DI_INP_LUMA0_RPT_PAT (0x17d5)
7349 #define P_DI_INP_LUMA0_RPT_PAT (volatile uint32_t *)((0x17d5 << 2) + 0xff900000)
7350 #define DI_INP_CHROMA0_RPT_PAT (0x17d6)
7351 #define P_DI_INP_CHROMA0_RPT_PAT (volatile uint32_t *)((0x17d6 << 2) + 0xff900000)
7352 #define DI_INP_DUMMY_PIXEL (0x17d7)
7353 #define P_DI_INP_DUMMY_PIXEL (volatile uint32_t *)((0x17d7 << 2) + 0xff900000)
7354 #define DI_INP_LUMA_FIFO_SIZE (0x17d8)
7355 #define P_DI_INP_LUMA_FIFO_SIZE (volatile uint32_t *)((0x17d8 << 2) + 0xff900000)
7356 #define DI_INP_RANGE_MAP_Y (0x17ba)
7357 #define P_DI_INP_RANGE_MAP_Y (volatile uint32_t *)((0x17ba << 2) + 0xff900000)
7358 #define DI_INP_RANGE_MAP_CB (0x17bb)
7359 #define P_DI_INP_RANGE_MAP_CB (volatile uint32_t *)((0x17bb << 2) + 0xff900000)
7360 #define DI_INP_RANGE_MAP_CR (0x17bc)
7361 #define P_DI_INP_RANGE_MAP_CR (volatile uint32_t *)((0x17bc << 2) + 0xff900000)
7362 #define DI_INP_GEN_REG2 (0x1791)
7363 #define P_DI_INP_GEN_REG2 (volatile uint32_t *)((0x1791 << 2) + 0xff900000)
7364 #define DI_INP_FMT_CTRL (0x17d9)
7365 #define P_DI_INP_FMT_CTRL (volatile uint32_t *)((0x17d9 << 2) + 0xff900000)
7366 #define DI_INP_FMT_W (0x17da)
7367 #define P_DI_INP_FMT_W (volatile uint32_t *)((0x17da << 2) + 0xff900000)
7368 #define DI_MEM_GEN_REG (0x17db)
7369 #define P_DI_MEM_GEN_REG (volatile uint32_t *)((0x17db << 2) + 0xff900000)
7370 #define DI_MEM_CANVAS0 (0x17dc)
7371 #define P_DI_MEM_CANVAS0 (volatile uint32_t *)((0x17dc << 2) + 0xff900000)
7372 #define DI_MEM_LUMA_X0 (0x17dd)
7373 #define P_DI_MEM_LUMA_X0 (volatile uint32_t *)((0x17dd << 2) + 0xff900000)
7374 #define DI_MEM_LUMA_Y0 (0x17de)
7375 #define P_DI_MEM_LUMA_Y0 (volatile uint32_t *)((0x17de << 2) + 0xff900000)
7376 #define DI_MEM_CHROMA_X0 (0x17df)
7377 #define P_DI_MEM_CHROMA_X0 (volatile uint32_t *)((0x17df << 2) + 0xff900000)
7378 #define DI_MEM_CHROMA_Y0 (0x17e0)
7379 #define P_DI_MEM_CHROMA_Y0 (volatile uint32_t *)((0x17e0 << 2) + 0xff900000)
7380 #define DI_MEM_RPT_LOOP (0x17e1)
7381 #define P_DI_MEM_RPT_LOOP (volatile uint32_t *)((0x17e1 << 2) + 0xff900000)
7382 #define DI_MEM_LUMA0_RPT_PAT (0x17e2)
7383 #define P_DI_MEM_LUMA0_RPT_PAT (volatile uint32_t *)((0x17e2 << 2) + 0xff900000)
7384 #define DI_MEM_CHROMA0_RPT_PAT (0x17e3)
7385 #define P_DI_MEM_CHROMA0_RPT_PAT (volatile uint32_t *)((0x17e3 << 2) + 0xff900000)
7386 #define DI_MEM_DUMMY_PIXEL (0x17e4)
7387 #define P_DI_MEM_DUMMY_PIXEL (volatile uint32_t *)((0x17e4 << 2) + 0xff900000)
7388 #define DI_MEM_LUMA_FIFO_SIZE (0x17e5)
7389 #define P_DI_MEM_LUMA_FIFO_SIZE (volatile uint32_t *)((0x17e5 << 2) + 0xff900000)
7390 #define DI_MEM_RANGE_MAP_Y (0x17bd)
7391 #define P_DI_MEM_RANGE_MAP_Y (volatile uint32_t *)((0x17bd << 2) + 0xff900000)
7392 #define DI_MEM_RANGE_MAP_CB (0x17be)
7393 #define P_DI_MEM_RANGE_MAP_CB (volatile uint32_t *)((0x17be << 2) + 0xff900000)
7394 #define DI_MEM_RANGE_MAP_CR (0x17bf)
7395 #define P_DI_MEM_RANGE_MAP_CR (volatile uint32_t *)((0x17bf << 2) + 0xff900000)
7396 #define DI_MEM_GEN_REG2 (0x1792)
7397 #define P_DI_MEM_GEN_REG2 (volatile uint32_t *)((0x1792 << 2) + 0xff900000)
7398 #define DI_MEM_FMT_CTRL (0x17e6)
7399 #define P_DI_MEM_FMT_CTRL (volatile uint32_t *)((0x17e6 << 2) + 0xff900000)
7400 #define DI_MEM_FMT_W (0x17e7)
7401 #define P_DI_MEM_FMT_W (volatile uint32_t *)((0x17e7 << 2) + 0xff900000)
7402 #define DI_IF1_GEN_REG (0x17e8)
7403 #define P_DI_IF1_GEN_REG (volatile uint32_t *)((0x17e8 << 2) + 0xff900000)
7404 #define DI_IF1_CANVAS0 (0x17e9)
7405 #define P_DI_IF1_CANVAS0 (volatile uint32_t *)((0x17e9 << 2) + 0xff900000)
7406 #define DI_IF1_LUMA_X0 (0x17ea)
7407 #define P_DI_IF1_LUMA_X0 (volatile uint32_t *)((0x17ea << 2) + 0xff900000)
7408 #define DI_IF1_LUMA_Y0 (0x17eb)
7409 #define P_DI_IF1_LUMA_Y0 (volatile uint32_t *)((0x17eb << 2) + 0xff900000)
7410 #define DI_IF1_CHROMA_X0 (0x17ec)
7411 #define P_DI_IF1_CHROMA_X0 (volatile uint32_t *)((0x17ec << 2) + 0xff900000)
7412 #define DI_IF1_CHROMA_Y0 (0x17ed)
7413 #define P_DI_IF1_CHROMA_Y0 (volatile uint32_t *)((0x17ed << 2) + 0xff900000)
7414 #define DI_IF1_RPT_LOOP (0x17ee)
7415 #define P_DI_IF1_RPT_LOOP (volatile uint32_t *)((0x17ee << 2) + 0xff900000)
7416 #define DI_IF1_LUMA0_RPT_PAT (0x17ef)
7417 #define P_DI_IF1_LUMA0_RPT_PAT (volatile uint32_t *)((0x17ef << 2) + 0xff900000)
7418 #define DI_IF1_CHROMA0_RPT_PAT (0x17f0)
7419 #define P_DI_IF1_CHROMA0_RPT_PAT (volatile uint32_t *)((0x17f0 << 2) + 0xff900000)
7420 #define DI_IF1_DUMMY_PIXEL (0x17f1)
7421 #define P_DI_IF1_DUMMY_PIXEL (volatile uint32_t *)((0x17f1 << 2) + 0xff900000)
7422 #define DI_IF1_LUMA_FIFO_SIZE (0x17f2)
7423 #define P_DI_IF1_LUMA_FIFO_SIZE (volatile uint32_t *)((0x17f2 << 2) + 0xff900000)
7424 #define DI_IF1_RANGE_MAP_Y (0x17fc)
7425 #define P_DI_IF1_RANGE_MAP_Y (volatile uint32_t *)((0x17fc << 2) + 0xff900000)
7426 #define DI_IF1_RANGE_MAP_CB (0x17fd)
7427 #define P_DI_IF1_RANGE_MAP_CB (volatile uint32_t *)((0x17fd << 2) + 0xff900000)
7428 #define DI_IF1_RANGE_MAP_CR (0x17fe)
7429 #define P_DI_IF1_RANGE_MAP_CR (volatile uint32_t *)((0x17fe << 2) + 0xff900000)
7430 #define DI_IF1_GEN_REG2 (0x1790)
7431 #define P_DI_IF1_GEN_REG2 (volatile uint32_t *)((0x1790 << 2) + 0xff900000)
7432 #define DI_IF1_FMT_CTRL (0x17f3)
7433 #define P_DI_IF1_FMT_CTRL (volatile uint32_t *)((0x17f3 << 2) + 0xff900000)
7434 #define DI_IF1_FMT_W (0x17f4)
7435 #define P_DI_IF1_FMT_W (volatile uint32_t *)((0x17f4 << 2) + 0xff900000)
7436 #define DI_CHAN2_GEN_REG (0x17f5)
7437 #define P_DI_CHAN2_GEN_REG (volatile uint32_t *)((0x17f5 << 2) + 0xff900000)
7438 #define DI_CHAN2_CANVAS0 (0x17f6)
7439 #define P_DI_CHAN2_CANVAS0 (volatile uint32_t *)((0x17f6 << 2) + 0xff900000)
7440 #define DI_CHAN2_LUMA_X0 (0x17f7)
7441 #define P_DI_CHAN2_LUMA_X0 (volatile uint32_t *)((0x17f7 << 2) + 0xff900000)
7442 #define DI_CHAN2_LUMA_Y0 (0x17f8)
7443 #define P_DI_CHAN2_LUMA_Y0 (volatile uint32_t *)((0x17f8 << 2) + 0xff900000)
7444 #define DI_CHAN2_CHROMA_X0 (0x17f9)
7445 #define P_DI_CHAN2_CHROMA_X0 (volatile uint32_t *)((0x17f9 << 2) + 0xff900000)
7446 #define DI_CHAN2_CHROMA_Y0 (0x17fa)
7447 #define P_DI_CHAN2_CHROMA_Y0 (volatile uint32_t *)((0x17fa << 2) + 0xff900000)
7448 #define DI_CHAN2_RPT_LOOP (0x17fb)
7449 #define P_DI_CHAN2_RPT_LOOP (volatile uint32_t *)((0x17fb << 2) + 0xff900000)
7450 #define DI_CHAN2_LUMA0_RPT_PAT (0x17b0)
7451 #define P_DI_CHAN2_LUMA0_RPT_PAT (volatile uint32_t *)((0x17b0 << 2) + 0xff900000)
7452 #define DI_CHAN2_CHROMA0_RPT_PAT (0x17b1)
7453 #define P_DI_CHAN2_CHROMA0_RPT_PAT (volatile uint32_t *)((0x17b1 << 2) + 0xff900000)
7454 #define DI_CHAN2_DUMMY_PIXEL (0x17b2)
7455 #define P_DI_CHAN2_DUMMY_PIXEL (volatile uint32_t *)((0x17b2 << 2) + 0xff900000)
7456 #define DI_CHAN2_LUMA_FIFO_SIZE (0x17b3)
7457 #define P_DI_CHAN2_LUMA_FIFO_SIZE (volatile uint32_t *)((0x17b3 << 2) + 0xff900000)
7458 #define DI_CHAN2_RANGE_MAP_Y (0x17b4)
7459 #define P_DI_CHAN2_RANGE_MAP_Y (volatile uint32_t *)((0x17b4 << 2) + 0xff900000)
7460 #define DI_CHAN2_RANGE_MAP_CB (0x17b5)
7461 #define P_DI_CHAN2_RANGE_MAP_CB (volatile uint32_t *)((0x17b5 << 2) + 0xff900000)
7462 #define DI_CHAN2_RANGE_MAP_CR (0x17b6)
7463 #define P_DI_CHAN2_RANGE_MAP_CR (volatile uint32_t *)((0x17b6 << 2) + 0xff900000)
7464 #define DI_CHAN2_GEN_REG2 (0x17b7)
7465 #define P_DI_CHAN2_GEN_REG2 (volatile uint32_t *)((0x17b7 << 2) + 0xff900000)
7466 #define DI_CHAN2_FMT_CTRL (0x17b8)
7467 #define P_DI_CHAN2_FMT_CTRL (volatile uint32_t *)((0x17b8 << 2) + 0xff900000)
7468 #define DI_CHAN2_FMT_W (0x17b9)
7469 #define P_DI_CHAN2_FMT_W (volatile uint32_t *)((0x17b9 << 2) + 0xff900000)
7470 //
7471 // Closing file: mad_regs.h
7472 //
7473 //`define VPP2_VCBUS_BASE 8'h19
7474 //
7475 // Reading file: vpp2_regs.h
7476 //
7477 // synopsys translate_off
7478 // synopsys translate_on
7479 // -----------------------------------------------
7480 // CBUS_BASE: VPP2_VCBUS_BASE = 0x19
7481 // -----------------------------------------------
7482 //===========================================================================
7483 // Video postprocesing Registers
7484 //===========================================================================
7485 // dummy data used in the VPP preblend and scaler
7486 // Bit 23:16
7487 // Bit 15:8 CB
7488 // Bit 7:0 CR
7489 #define VPP2_DUMMY_DATA (0x1900)
7490 #define P_VPP2_DUMMY_DATA (volatile uint32_t *)((0x1900 << 2) + 0xff900000)
7491 //input line length used in VPP
7492 #define VPP2_LINE_IN_LENGTH (0x1901)
7493 #define P_VPP2_LINE_IN_LENGTH (volatile uint32_t *)((0x1901 << 2) + 0xff900000)
7494 //input Picture height used in VPP
7495 #define VPP2_PIC_IN_HEIGHT (0x1902)
7496 #define P_VPP2_PIC_IN_HEIGHT (volatile uint32_t *)((0x1902 << 2) + 0xff900000)
7497 //Because there are many coefficients used in the vertical filter and horizontal filters,
7498 //indirect access the coefficients of vertical filter and horizontal filter is used.
7499 //For vertical filter, there are 33x4 coefficients
7500 //For horizontal filter, there are 33x4 coefficients
7501 //Bit 15 index increment, if bit9 == 1 then (0: index increase 1, 1: index increase 2) else (index increase 2)
7502 //Bit 14 1: read coef through cbus enable, just for debug purpose in case when we wanna check the coef in ram in correct or not
7503 //Bit 13 if true, vertical separated coef enable
7504 //Bit 9 if true, use 9bit resolution coef, other use 8bit resolution coef
7505 //Bit 8:7 type of index, 00: vertical coef, 01: vertical chroma coef: 10: horizontal coef, 11: resevered
7506 //Bit 6:0 coef index
7507 #define VPP2_SCALE_COEF_IDX (0x1903)
7508 #define P_VPP2_SCALE_COEF_IDX (volatile uint32_t *)((0x1903 << 2) + 0xff900000)
7509 //coefficients for vertical filter and horizontal filter
7510 #define VPP2_SCALE_COEF (0x1904)
7511 #define P_VPP2_SCALE_COEF (volatile uint32_t *)((0x1904 << 2) + 0xff900000)
7512 //these following registers are the absolute line address pointer for output divided screen
7513 //The output divided screen is shown in the following:
7514 //
7515 // -------------------------- <------ line zero
7516 // .
7517 // .
7518 // . region0 <---------- nonlinear region or nonscaling region
7519 // .
7520 // ---------------------------
7521 // --------------------------- <------ region1_startp
7522 // .
7523 // . region1 <---------- nonlinear region
7524 // .
7525 // .
7526 // ---------------------------
7527 // --------------------------- <------ region2_startp
7528 // .
7529 // . region2 <---------- linear region
7530 // .
7531 // .
7532 // ---------------------------
7533 // --------------------------- <------ region3_startp
7534 // .
7535 // . region3 <---------- nonlinear region
7536 // .
7537 // .
7538 // ---------------------------
7539 // --------------------------- <------ region4_startp
7540 // .
7541 // . region4 <---------- nonlinear region or nonoscaling region
7542 // .
7543 // .
7544 // --------------------------- <------ region4_endp
7545 //Bit 28:16 region1 startp
7546 //Bit 12:0 region2 startp
7547 #define VPP2_VSC_REGION12_STARTP (0x1905)
7548 #define P_VPP2_VSC_REGION12_STARTP (volatile uint32_t *)((0x1905 << 2) + 0xff900000)
7549 //Bit 28:16 region3 startp
7550 //Bit 12:0 region4 startp
7551 #define VPP2_VSC_REGION34_STARTP (0x1906)
7552 #define P_VPP2_VSC_REGION34_STARTP (volatile uint32_t *)((0x1906 << 2) + 0xff900000)
7553 #define VPP2_VSC_REGION4_ENDP (0x1907)
7554 #define P_VPP2_VSC_REGION4_ENDP (volatile uint32_t *)((0x1907 << 2) + 0xff900000)
7555 //vertical start phase step, (source/dest)*(2^24)
7556 //Bit 27:24 integer part
7557 //Bit 23:0 fraction part
7558 #define VPP2_VSC_START_PHASE_STEP (0x1908)
7559 #define P_VPP2_VSC_START_PHASE_STEP (volatile uint32_t *)((0x1908 << 2) + 0xff900000)
7560 //vertical scaler region0 phase slope, Bit24 signed bit
7561 #define VPP2_VSC_REGION0_PHASE_SLOPE (0x1909)
7562 #define P_VPP2_VSC_REGION0_PHASE_SLOPE (volatile uint32_t *)((0x1909 << 2) + 0xff900000)
7563 //vertical scaler region1 phase slope, Bit24 signed bit
7564 #define VPP2_VSC_REGION1_PHASE_SLOPE (0x190a)
7565 #define P_VPP2_VSC_REGION1_PHASE_SLOPE (volatile uint32_t *)((0x190a << 2) + 0xff900000)
7566 //vertical scaler region3 phase slope, Bit24 signed bit
7567 #define VPP2_VSC_REGION3_PHASE_SLOPE (0x190b)
7568 #define P_VPP2_VSC_REGION3_PHASE_SLOPE (volatile uint32_t *)((0x190b << 2) + 0xff900000)
7569 //vertical scaler region4 phase slope, Bit24 signed bit
7570 #define VPP2_VSC_REGION4_PHASE_SLOPE (0x190c)
7571 #define P_VPP2_VSC_REGION4_PHASE_SLOPE (volatile uint32_t *)((0x190c << 2) + 0xff900000)
7572 //Bit 18:17 double line mode, input/output line width of vscaler becomes 2X,
7573 // so only 2 line buffer in this case, use for 3D line by line interleave scaling
7574 // bit1 true, double the input width and half input height, bit0 true, change line buffer 2 lines instead of 4 lines
7575 //Bit 16 0: progressive output, 1: interlace output
7576 //Bit 15 vertical scaler output line0 in advance or not for bottom field
7577 //Bit 14:13 vertical scaler initial repeat line0 number for bottom field
7578 //Bit 11:8 vertical scaler initial receiving number for bottom field
7579 //Bit 7 vertical scaler output line0 in advance or not for top field
7580 //Bit 6:5 vertical scaler initial repeat line0 number for top field
7581 //Bit 3:0 vertical scaler initial receiving number for top field
7582 #define VPP2_VSC_PHASE_CTRL (0x190d)
7583 #define P_VPP2_VSC_PHASE_CTRL (volatile uint32_t *)((0x190d << 2) + 0xff900000)
7584 //Bit 31:16 vertical scaler field initial phase for bottom field
7585 //Bit 15:0 vertical scaler field initial phase for top field
7586 #define VPP2_VSC_INI_PHASE (0x190e)
7587 #define P_VPP2_VSC_INI_PHASE (volatile uint32_t *)((0x190e << 2) + 0xff900000)
7588 //Bit 28:16 region1 startp
7589 //Bit 12:0 region2 startp
7590 #define VPP2_HSC_REGION12_STARTP (0x1910)
7591 #define P_VPP2_HSC_REGION12_STARTP (volatile uint32_t *)((0x1910 << 2) + 0xff900000)
7592 //Bit 28:16 region3 startp
7593 //Bit 12:0 region4 startp
7594 #define VPP2_HSC_REGION34_STARTP (0x1911)
7595 #define P_VPP2_HSC_REGION34_STARTP (volatile uint32_t *)((0x1911 << 2) + 0xff900000)
7596 #define VPP2_HSC_REGION4_ENDP (0x1912)
7597 #define P_VPP2_HSC_REGION4_ENDP (volatile uint32_t *)((0x1912 << 2) + 0xff900000)
7598 //horizontal start phase step, (source/dest)*(2^24)
7599 //Bit 27:24 integer part
7600 //Bit 23:0 fraction part
7601 #define VPP2_HSC_START_PHASE_STEP (0x1913)
7602 #define P_VPP2_HSC_START_PHASE_STEP (volatile uint32_t *)((0x1913 << 2) + 0xff900000)
7603 //horizontal scaler region0 phase slope, Bit24 signed bit
7604 #define VPP2_HSC_REGION0_PHASE_SLOPE (0x1914)
7605 #define P_VPP2_HSC_REGION0_PHASE_SLOPE (volatile uint32_t *)((0x1914 << 2) + 0xff900000)
7606 //horizontal scaler region1 phase slope, Bit24 signed bit
7607 #define VPP2_HSC_REGION1_PHASE_SLOPE (0x1915)
7608 #define P_VPP2_HSC_REGION1_PHASE_SLOPE (volatile uint32_t *)((0x1915 << 2) + 0xff900000)
7609 //horizontal scaler region3 phase slope, Bit24 signed bit
7610 #define VPP2_HSC_REGION3_PHASE_SLOPE (0x1916)
7611 #define P_VPP2_HSC_REGION3_PHASE_SLOPE (volatile uint32_t *)((0x1916 << 2) + 0xff900000)
7612 //horizontal scaler region4 phase slope, Bit24 signed bit
7613 #define VPP2_HSC_REGION4_PHASE_SLOPE (0x1917)
7614 #define P_VPP2_HSC_REGION4_PHASE_SLOPE (volatile uint32_t *)((0x1917 << 2) + 0xff900000)
7615 //Bit 22:21 horizontal scaler initial repeat pixel0 number
7616 //Bit 19:16 horizontal scaler initial receiving number
7617 //Bit 15:0 horizontal scaler top field initial phase
7618 #define VPP2_HSC_PHASE_CTRL (0x1918)
7619 #define P_VPP2_HSC_PHASE_CTRL (volatile uint32_t *)((0x1918 << 2) + 0xff900000)
7620 // Bit 22 if true, divide VSC line length 2 as the HSC input length, othwise VSC length length is the same as the VSC line length,
7621 // just for special usage, more flexibility
7622 // Bit 21 if true, prevsc uses lin buffer, otherwise prevsc does not use line buffer, it should be same as prevsc_en
7623 // Bit 20 prehsc_en
7624 // Bit 19 prevsc_en
7625 // Bit 18 vsc_en
7626 // Bit 17 hsc_en
7627 // Bit 16 scale_top_en
7628 // Bit 15 video1 scale out enable
7629 // Bit 12 if true, region0,region4 are nonlinear regions, otherwise they are not scaling regions, for horizontal scaler
7630 // Bit 10:8 horizontal scaler bank length
7631 // Bit 5, vertical scaler phase field mode, if true, disable the opposite parity line output, more bandwith needed if output 1080i
7632 // Bit 4 if true, region0,region4 are nonlinear regions, otherwise they are not scaling regions, for vertical scaler
7633 // Bit 2:0 vertical scaler bank length
7634 #define VPP2_SC_MISC (0x1919)
7635 #define P_VPP2_SC_MISC (volatile uint32_t *)((0x1919 << 2) + 0xff900000)
7636 // preblend video1 horizontal start and end
7637 //Bit 28:16 start
7638 //Bit 12:0 end
7639 #define VPP2_PREBLEND_VD1_H_START_END (0x191a)
7640 #define P_VPP2_PREBLEND_VD1_H_START_END (volatile uint32_t *)((0x191a << 2) + 0xff900000)
7641 // preblend video1 vertical start and end
7642 //Bit 28:16 start
7643 //Bit 12:0 end
7644 #define VPP2_PREBLEND_VD1_V_START_END (0x191b)
7645 #define P_VPP2_PREBLEND_VD1_V_START_END (volatile uint32_t *)((0x191b << 2) + 0xff900000)
7646 // postblend video1 horizontal start and end
7647 //Bit 28:16 start
7648 //Bit 12:0 end
7649 #define VPP2_POSTBLEND_VD1_H_START_END (0x191c)
7650 #define P_VPP2_POSTBLEND_VD1_H_START_END (volatile uint32_t *)((0x191c << 2) + 0xff900000)
7651 // postblend video1 vertical start and end
7652 //Bit 28:16 start
7653 //Bit 12:0 end
7654 #define VPP2_POSTBLEND_VD1_V_START_END (0x191d)
7655 #define P_VPP2_POSTBLEND_VD1_V_START_END (volatile uint32_t *)((0x191d << 2) + 0xff900000)
7656 // preblend horizontal size
7657 #define VPP2_PREBLEND_H_SIZE (0x1920)
7658 #define P_VPP2_PREBLEND_H_SIZE (volatile uint32_t *)((0x1920 << 2) + 0xff900000)
7659 // postblend horizontal size
7660 #define VPP2_POSTBLEND_H_SIZE (0x1921)
7661 #define P_VPP2_POSTBLEND_H_SIZE (volatile uint32_t *)((0x1921 << 2) + 0xff900000)
7662 //VPP hold lines
7663 //Bit 29:24
7664 //Bit 21:16
7665 //Bit 15:8 preblend hold lines
7666 //Bit 7:0 postblend hold lines
7667 #define VPP2_HOLD_LINES (0x1922)
7668 #define P_VPP2_HOLD_LINES (volatile uint32_t *)((0x1922 << 2) + 0xff900000)
7669 //Bit 25 if true, change screen to one color value for preblender
7670 //Bit 24 if true, change screen to one color value for postblender
7671 // Bit 23:16 one color Y
7672 // Bit 15:8 one color Cb
7673 // Bit 7:0 one color Cr
7674 #define VPP2_BLEND_ONECOLOR_CTRL (0x1923)
7675 #define P_VPP2_BLEND_ONECOLOR_CTRL (volatile uint32_t *)((0x1923 << 2) + 0xff900000)
7676 //Read Only, VPP preblend current_x, current_y
7677 //Bit 28:16 current_x
7678 //Bit 12:0 current_y
7679 #define VPP2_PREBLEND_CURRENT_XY (0x1924)
7680 #define P_VPP2_PREBLEND_CURRENT_XY (volatile uint32_t *)((0x1924 << 2) + 0xff900000)
7681 //Read Only, VPP postblend current_x, current_y
7682 //Bit 28:16 current_x
7683 //Bit 12:0 current_y
7684 #define VPP2_POSTBLEND_CURRENT_XY (0x1925)
7685 #define P_VPP2_POSTBLEND_CURRENT_XY (volatile uint32_t *)((0x1925 << 2) + 0xff900000)
7686 // Bit 31 vd1_bgosd_exchange_en for preblend
7687 // Bit 30 vd1_bgosd_exchange_en for postblend
7688 // bit 28 color management enable
7689 // Bit 27, reserved
7690 // Bit 26:18, reserved
7691 // Bit 17, osd2 enable for preblend
7692 // Bit 16, osd1 enable for preblend
7693 // Bit 15, reserved
7694 // Bit 14, vd1 enable for preblend
7695 // Bit 13, osd2 enable for postblend
7696 // Bit 12, osd1 enable for postblend
7697 // Bit 11, reserved
7698 // Bit 10, vd1 enable for postblend
7699 // Bit 9, if true, osd1 is alpha premultipiled
7700 // Bit 8, if true, osd2 is alpha premultipiled
7701 // Bit 7, postblend module enable
7702 // Bit 6, preblend module enable
7703 // Bit 5, if true, osd2 foreground compared with osd1 in preblend
7704 // Bit 4, if true, osd2 foreground compared with osd1 in postblend
7705 // Bit 3,
7706 // Bit 2, if true, disable resetting async fifo every vsync, otherwise every vsync
7707 // the aync fifo will be reseted.
7708 // Bit 1,
7709 // Bit 0 if true, the output result of VPP is saturated
7710 #define VPP2_MISC (0x1926)
7711 #define P_VPP2_MISC (volatile uint32_t *)((0x1926 << 2) + 0xff900000)
7712 //Bit 31:20 ofifo line length minus 1
7713 //Bit 19 if true invert input vs
7714 //Bit 18 if true invert input hs
7715 //Bit 17 force top/bottom field, enable
7716 //Bit 16 force top/bottom field, 0: top, 1: bottom
7717 //Bit 15 force one go_field, one pluse, write only
7718 //Bit 14 force one go_line, one pluse, write only
7719 //Bit 12:0 ofifo size (actually only bit 10:1 is valid), always even number
7720 #define VPP2_OFIFO_SIZE (0x1927)
7721 #define P_VPP2_OFIFO_SIZE (volatile uint32_t *)((0x1927 << 2) + 0xff900000)
7722 //Read only
7723 //Bit 28:17 current scale out fifo counter
7724 //Bit 16:12 current afifo counter
7725 //Bit 11:0 current ofifo counter
7726 #define VPP2_FIFO_STATUS (0x1928)
7727 #define P_VPP2_FIFO_STATUS (volatile uint32_t *)((0x1928 << 2) + 0xff900000)
7728 // Bit 3 SMOKE2 postblend enable only when postblend osd2 is not enable
7729 // Bit 2 SMOKE2 preblend enable only when preblend osd2 is not enable
7730 // Bit 1 SMOKE1 postblend enable only when postblend osd1 is not enable
7731 // Bit 0 SMOKE1 preblend enable only when preblend osd1 is not enable
7732 #define VPP2_SMOKE_CTRL (0x1929)
7733 #define P_VPP2_SMOKE_CTRL (volatile uint32_t *)((0x1929 << 2) + 0xff900000)
7734 //smoke can be used only when that blending is disable and then be used as smoke function
7735 //smoke1 for OSD1 chanel
7736 //smoke2 for OSD2 chanel
7737 //31:24 Y
7738 //23:16 Cb
7739 //15:8 Cr
7740 //7:0 Alpha
7741 #define VPP2_SMOKE1_VAL (0x192a)
7742 #define P_VPP2_SMOKE1_VAL (volatile uint32_t *)((0x192a << 2) + 0xff900000)
7743 #define VPP2_SMOKE2_VAL (0x192b)
7744 #define P_VPP2_SMOKE2_VAL (volatile uint32_t *)((0x192b << 2) + 0xff900000)
7745 //Bit 28:16 start
7746 //Bit 12:0 end
7747 #define VPP2_SMOKE1_H_START_END (0x192d)
7748 #define P_VPP2_SMOKE1_H_START_END (volatile uint32_t *)((0x192d << 2) + 0xff900000)
7749 //Bit 28:16 start
7750 //Bit 12:0 end
7751 #define VPP2_SMOKE1_V_START_END (0x192e)
7752 #define P_VPP2_SMOKE1_V_START_END (volatile uint32_t *)((0x192e << 2) + 0xff900000)
7753 //Bit 28:16 start
7754 //Bit 12:0 end
7755 #define VPP2_SMOKE2_H_START_END (0x192f)
7756 #define P_VPP2_SMOKE2_H_START_END (volatile uint32_t *)((0x192f << 2) + 0xff900000)
7757 //Bit 28:16 start
7758 //Bit 12:0 end
7759 #define VPP2_SMOKE2_V_START_END (0x1930)
7760 #define P_VPP2_SMOKE2_V_START_END (volatile uint32_t *)((0x1930 << 2) + 0xff900000)
7761 //Bit 27:16 scale out fifo line length minus 1
7762 //Bit 12:0 scale out fifo size (actually only bit 11:1 is valid, 11:1, max 1024), always even number
7763 #define VPP2_SCO_FIFO_CTRL (0x1933)
7764 #define P_VPP2_SCO_FIFO_CTRL (volatile uint32_t *)((0x1933 << 2) + 0xff900000)
7765 //for 3D quincunx sub-sampling and horizontal pixel by pixel 3D interleaving
7766 //Bit 27:24, prehsc_mode, bit 3:2, prehsc odd line interp mode, bit 1:0, prehsc even line interp mode,
7767 // each 2bit, 00: pix0+pix1/2, average, 01: pix1, 10: pix0
7768 //Bit 23 horizontal scaler double pixel mode
7769 //Bit 22:21 horizontal scaler initial repeat pixel0 number1
7770 //Bit 19:16 horizontal scaler initial receiving number1
7771 //Bit 15:0 horizontal scaler top field initial phase1
7772 #define VPP2_HSC_PHASE_CTRL1 (0x1934)
7773 #define P_VPP2_HSC_PHASE_CTRL1 (volatile uint32_t *)((0x1934 << 2) + 0xff900000)
7774 //for 3D quincunx sub-sampling
7775 //31:24 prehsc pattern, each patten 1 bit, from lsb -> msb
7776 //22:20 prehsc pattern start
7777 //18:16 prehsc pattern end
7778 //15:8 pattern, each patten 1 bit, from lsb -> msb
7779 //6:4 pattern start
7780 //2:0 pattern end
7781 #define VPP2_HSC_INI_PAT_CTRL (0x1935)
7782 #define P_VPP2_HSC_INI_PAT_CTRL (volatile uint32_t *)((0x1935 << 2) + 0xff900000)
7783 //Bit 3 minus black level enable for vadj2
7784 //Bit 2 Video adjustment enable for vadj2
7785 //Bit 1 minus black level enable for vadj1
7786 //Bit 0 Video adjustment enable for vadj1
7787 #define VPP2_VADJ_CTRL (0x1940)
7788 #define P_VPP2_VADJ_CTRL (volatile uint32_t *)((0x1940 << 2) + 0xff900000)
7789 //Bit 16:8 brightness, signed value
7790 //Bit 7:0 contrast, unsigned value, contrast from 0 <= contrast <2
7791 #define VPP2_VADJ1_Y (0x1941)
7792 #define P_VPP2_VADJ1_Y (volatile uint32_t *)((0x1941 << 2) + 0xff900000)
7793 //cb' = cb*ma + cr*mb
7794 //cr' = cb*mc + cr*md
7795 //all are bit 9:0, signed value, -2 < ma/mb/mc/md < 2
7796 #define VPP2_VADJ1_MA_MB (0x1942)
7797 #define P_VPP2_VADJ1_MA_MB (volatile uint32_t *)((0x1942 << 2) + 0xff900000)
7798 #define VPP2_VADJ1_MC_MD (0x1943)
7799 #define P_VPP2_VADJ1_MC_MD (volatile uint32_t *)((0x1943 << 2) + 0xff900000)
7800 //Bit 16:8 brightness, signed value
7801 //Bit 7:0 contrast, unsigned value, contrast from 0 <= contrast <2
7802 #define VPP2_VADJ2_Y (0x1944)
7803 #define P_VPP2_VADJ2_Y (volatile uint32_t *)((0x1944 << 2) + 0xff900000)
7804 //cb' = cb*ma + cr*mb
7805 //cr' = cb*mc + cr*md
7806 //all are bit 9:0, signed value, -2 < ma/mb/mc/md < 2
7807 #define VPP2_VADJ2_MA_MB (0x1945)
7808 #define P_VPP2_VADJ2_MA_MB (volatile uint32_t *)((0x1945 << 2) + 0xff900000)
7809 #define VPP2_VADJ2_MC_MD (0x1946)
7810 #define P_VPP2_VADJ2_MC_MD (volatile uint32_t *)((0x1946 << 2) + 0xff900000)
7811 //Read only
7812 //Bit 31, if it is true, it means this probe is valid in the last field/frame
7813 //Bit 29:20 component 0
7814 //Bit 19:10 component 1
7815 //Bit 9:0 component 2
7816 #define VPP2_MATRIX_PROBE_COLOR (0x195c)
7817 #define P_VPP2_MATRIX_PROBE_COLOR (volatile uint32_t *)((0x195c << 2) + 0xff900000)
7818 //Bit 23:16 component 0
7819 //Bit 15:8 component 1
7820 //Bit 7:0 component 2
7821 #define VPP2_MATRIX_HL_COLOR (0x195d)
7822 #define P_VPP2_MATRIX_HL_COLOR (volatile uint32_t *)((0x195d << 2) + 0xff900000)
7823 //28:16 probe x, postion
7824 //12:0 probe y, position
7825 #define VPP2_MATRIX_PROBE_POS (0x195e)
7826 #define P_VPP2_MATRIX_PROBE_POS (volatile uint32_t *)((0x195e << 2) + 0xff900000)
7827 //Bit 16, highlight_en
7828 //Bit 15 probe_post, if true, probe pixel data after matrix, otherwise probe pixel data before matrix
7829 //Bit 14:12 probe_sel, 000: select post matrix, 001: select vd1 matrix,
7830 //Bit 9:8 matrix coef idx selection, 00: select post matrix, 01: select vd1 matrix
7831 //Bit 5 vd1 conversion matrix enable
7832 //Bit 4 reserved
7833 //Bit 2 output y/cb/cr saturation enable, only for post matrix (y saturate to 16-235, cb/cr saturate to 16-240)
7834 //Bit 1 input y/cb/cr saturation enable, only for post matrix (y saturate to 16-235, cb/cr saturate to 16-240)
7835 //Bit 0 post conversion matrix enable
7836 #define VPP2_MATRIX_CTRL (0x195f)
7837 #define P_VPP2_MATRIX_CTRL (volatile uint32_t *)((0x195f << 2) + 0xff900000)
7838 //Bit 28:16 coef00
7839 //Bit 12:0 coef01
7840 #define VPP2_MATRIX_COEF00_01 (0x1960)
7841 #define P_VPP2_MATRIX_COEF00_01 (volatile uint32_t *)((0x1960 << 2) + 0xff900000)
7842 //Bit 28:16 coef02
7843 //Bit 12:0 coef10
7844 #define VPP2_MATRIX_COEF02_10 (0x1961)
7845 #define P_VPP2_MATRIX_COEF02_10 (volatile uint32_t *)((0x1961 << 2) + 0xff900000)
7846 //Bit 28:16 coef11
7847 //Bit 12:0 coef12
7848 #define VPP2_MATRIX_COEF11_12 (0x1962)
7849 #define P_VPP2_MATRIX_COEF11_12 (volatile uint32_t *)((0x1962 << 2) + 0xff900000)
7850 //Bit 28:16 coef20
7851 //Bit 12:0 coef21
7852 #define VPP2_MATRIX_COEF20_21 (0x1963)
7853 #define P_VPP2_MATRIX_COEF20_21 (volatile uint32_t *)((0x1963 << 2) + 0xff900000)
7854 #define VPP2_MATRIX_COEF22 (0x1964)
7855 #define P_VPP2_MATRIX_COEF22 (volatile uint32_t *)((0x1964 << 2) + 0xff900000)
7856 //Bit 26:16 offset0
7857 //Bit 10:0 offset1
7858 #define VPP2_MATRIX_OFFSET0_1 (0x1965)
7859 #define P_VPP2_MATRIX_OFFSET0_1 (volatile uint32_t *)((0x1965 << 2) + 0xff900000)
7860 //Bit 10:0 offset2
7861 #define VPP2_MATRIX_OFFSET2 (0x1966)
7862 #define P_VPP2_MATRIX_OFFSET2 (volatile uint32_t *)((0x1966 << 2) + 0xff900000)
7863 //Bit 26:16 pre_offset0
7864 //Bit 10:0 pre_offset1
7865 #define VPP2_MATRIX_PRE_OFFSET0_1 (0x1967)
7866 #define P_VPP2_MATRIX_PRE_OFFSET0_1 (volatile uint32_t *)((0x1967 << 2) + 0xff900000)
7867 //Bit 10:0 pre_offset2
7868 #define VPP2_MATRIX_PRE_OFFSET2 (0x1968)
7869 #define P_VPP2_MATRIX_PRE_OFFSET2 (volatile uint32_t *)((0x1968 << 2) + 0xff900000)
7870 // dummy data used in the VPP postblend
7871 // Bit 23:16 Y
7872 // Bit 15:8 CB
7873 // Bit 7:0 CR
7874 #define VPP2_DUMMY_DATA1 (0x1969)
7875 #define P_VPP2_DUMMY_DATA1 (volatile uint32_t *)((0x1969 << 2) + 0xff900000)
7876 //Bit 31 gainoff module enable
7877 //Bit 26:16 gain0, 1.10 unsigned data
7878 //Bit 10:0 gain1, 1.10 unsigned dat
7879 #define VPP2_GAINOFF_CTRL0 (0x196a)
7880 #define P_VPP2_GAINOFF_CTRL0 (volatile uint32_t *)((0x196a << 2) + 0xff900000)
7881 //Bit 26:16 gain2, 1.10 unsigned data
7882 //Bit 10:0, offset0, signed data
7883 #define VPP2_GAINOFF_CTRL1 (0x196b)
7884 #define P_VPP2_GAINOFF_CTRL1 (volatile uint32_t *)((0x196b << 2) + 0xff900000)
7885 //Bit 26:16, offset1, signed data
7886 //Bit 10:0, offset2, signed data
7887 #define VPP2_GAINOFF_CTRL2 (0x196c)
7888 #define P_VPP2_GAINOFF_CTRL2 (volatile uint32_t *)((0x196c << 2) + 0xff900000)
7889 //Bit 26:16, pre_offset0, signed data
7890 //Bit 10:0, pre_offset1, signed data
7891 #define VPP2_GAINOFF_CTRL3 (0x196d)
7892 #define P_VPP2_GAINOFF_CTRL3 (volatile uint32_t *)((0x196d << 2) + 0xff900000)
7893 //Bit 10:0, pre_offset2, signed data
7894 #define VPP2_GAINOFF_CTRL4 (0x196e)
7895 #define P_VPP2_GAINOFF_CTRL4 (volatile uint32_t *)((0x196e << 2) + 0xff900000)
7896 //only two registers used in the color management, which are defined in the chroma_reg.h
7897 #define VPP2_CHROMA_ADDR_PORT (0x1970)
7898 #define P_VPP2_CHROMA_ADDR_PORT (volatile uint32_t *)((0x1970 << 2) + 0xff900000)
7899 #define VPP2_CHROMA_DATA_PORT (0x1971)
7900 #define P_VPP2_CHROMA_DATA_PORT (volatile uint32_t *)((0x1971 << 2) + 0xff900000)
7901 //`include "chroma_reg.h" //defined inside is the indirect addressed registers
7902 //(hsvsharp), (blue), gainoff, mat_vd1,mat_vd2, mat_post, prebld, postbld,(hsharp),sco_ff, vadj1, vadj2, ofifo, (chroma1), clk0(free_clk) vpp_reg
7903 //each item 2bits, for each 2bits, if bit 2*i+1 == 1, free clk, else if bit 2*i == 1 no clk, else auto gated clock
7904 //bit1 is not used, because I can not turn off vpp_reg clk because I can not turn on again
7905 //because the register itself canot be set again without clk
7906 //Bit 31:0
7907 #define VPP2_GCLK_CTRL0 (0x1972)
7908 #define P_VPP2_GCLK_CTRL0 (volatile uint32_t *)((0x1972 << 2) + 0xff900000)
7909 //Chroma2_filter, Chroma2, (Ccoring), (blackext), dnlp
7910 //Bit 9:0
7911 #define VPP2_GCLK_CTRL1 (0x1973)
7912 #define P_VPP2_GCLK_CTRL1 (volatile uint32_t *)((0x1973 << 2) + 0xff900000)
7913 //prehsc_clk, line_buf, prevsc, vsc, hsc_clk, clk0(free_clk)
7914 //Bit 11:0
7915 #define VPP2_SC_GCLK_CTRL (0x1974)
7916 #define P_VPP2_SC_GCLK_CTRL (volatile uint32_t *)((0x1974 << 2) + 0xff900000)
7917 //Bit 17:9 VD1 alpha for preblend
7918 //Bit 8:0 VD1 alpha for postblend
7919 #define VPP2_MISC1 (0x1976)
7920 #define P_VPP2_MISC1 (volatile uint32_t *)((0x1976 << 2) + 0xff900000)
7921 //Bit 31:24 bottom of region03 output value
7922 //Bit 23:16 bottom of region02 output value
7923 //Bit 15:8 bottom of region01 output value
7924 //Bit 7:0 bottom of region00 output value
7925 #define VPP2_DNLP_CTRL_00 (0x1981)
7926 #define P_VPP2_DNLP_CTRL_00 (volatile uint32_t *)((0x1981 << 2) + 0xff900000)
7927 //Bit 31:24 bottom of region07 output value
7928 //Bit 23:16 bottom of region06 output value
7929 //Bit 15:8 bottom of region05 output value
7930 //Bit 7:0 bottom of region04 output value
7931 #define VPP2_DNLP_CTRL_01 (0x1982)
7932 #define P_VPP2_DNLP_CTRL_01 (volatile uint32_t *)((0x1982 << 2) + 0xff900000)
7933 //Bit 31:24 bottom of region11 output value
7934 //Bit 23:16 bottom of region10 output value
7935 //Bit 15:8 bottom of region09 output value
7936 //Bit 7:0 bottom of region08 output value
7937 #define VPP2_DNLP_CTRL_02 (0x1983)
7938 #define P_VPP2_DNLP_CTRL_02 (volatile uint32_t *)((0x1983 << 2) + 0xff900000)
7939 //Bit 31:24 bottom of region15 output value
7940 //Bit 23:16 bottom of region14 output value
7941 //Bit 15:8 bottom of region13 output value
7942 //Bit 7:0 bottom of region12 output value
7943 #define VPP2_DNLP_CTRL_03 (0x1984)
7944 #define P_VPP2_DNLP_CTRL_03 (volatile uint32_t *)((0x1984 << 2) + 0xff900000)
7945 //Bit 31:24 bottom of region19 output value
7946 //Bit 23:16 bottom of region18 output value
7947 //Bit 15:8 bottom of region17 output value
7948 //Bit 7:0 bottom of region16 output value
7949 #define VPP2_DNLP_CTRL_04 (0x1985)
7950 #define P_VPP2_DNLP_CTRL_04 (volatile uint32_t *)((0x1985 << 2) + 0xff900000)
7951 //Bit 31:24 bottom of region23 output value
7952 //Bit 23:16 bottom of region22 output value
7953 //Bit 15:8 bottom of region21 output value
7954 //Bit 7:0 bottom of region20 output value
7955 #define VPP2_DNLP_CTRL_05 (0x1986)
7956 #define P_VPP2_DNLP_CTRL_05 (volatile uint32_t *)((0x1986 << 2) + 0xff900000)
7957 //Bit 31:24 bottom of region27 output value
7958 //Bit 23:16 bottom of region26 output value
7959 //Bit 15:8 bottom of region25 output value
7960 //Bit 7:0 bottom of region24 output value
7961 #define VPP2_DNLP_CTRL_06 (0x1987)
7962 #define P_VPP2_DNLP_CTRL_06 (volatile uint32_t *)((0x1987 << 2) + 0xff900000)
7963 //Bit 31:24 bottom of region31 output value
7964 //Bit 23:16 bottom of region30 output value
7965 //Bit 15:8 bottom of region29 output value
7966 //Bit 7:0 bottom of region28 output value
7967 #define VPP2_DNLP_CTRL_07 (0x1988)
7968 #define P_VPP2_DNLP_CTRL_07 (volatile uint32_t *)((0x1988 << 2) + 0xff900000)
7969 //Bit 31:24 bottom of region35 output value
7970 //Bit 23:16 bottom of region34 output value
7971 //Bit 15:8 bottom of region33 output value
7972 //Bit 7:0 bottom of region32 output value
7973 #define VPP2_DNLP_CTRL_08 (0x1989)
7974 #define P_VPP2_DNLP_CTRL_08 (volatile uint32_t *)((0x1989 << 2) + 0xff900000)
7975 //Bit 31:24 bottom of region39 output value
7976 //Bit 23:16 bottom of region38 output value
7977 //Bit 15:8 bottom of region37 output value
7978 //Bit 7:0 bottom of region36 output value
7979 #define VPP2_DNLP_CTRL_09 (0x198a)
7980 #define P_VPP2_DNLP_CTRL_09 (volatile uint32_t *)((0x198a << 2) + 0xff900000)
7981 //Bit 31:24 bottom of region43 output value
7982 //Bit 23:16 bottom of region42 output value
7983 //Bit 15:8 bottom of region41 output value
7984 //Bit 7:0 bottom of region40 output value
7985 #define VPP2_DNLP_CTRL_10 (0x198b)
7986 #define P_VPP2_DNLP_CTRL_10 (volatile uint32_t *)((0x198b << 2) + 0xff900000)
7987 //Bit 31:24 bottom of region47 output value
7988 //Bit 23:16 bottom of region46 output value
7989 //Bit 15:8 bottom of region45 output value
7990 //Bit 7:0 bottom of region44 output value
7991 #define VPP2_DNLP_CTRL_11 (0x198c)
7992 #define P_VPP2_DNLP_CTRL_11 (volatile uint32_t *)((0x198c << 2) + 0xff900000)
7993 //Bit 31:24 bottom of region51 output value
7994 //Bit 23:16 bottom of region50 output value
7995 //Bit 15:8 bottom of region49 output value
7996 //Bit 7:0 bottom of region48 output value
7997 #define VPP2_DNLP_CTRL_12 (0x198d)
7998 #define P_VPP2_DNLP_CTRL_12 (volatile uint32_t *)((0x198d << 2) + 0xff900000)
7999 //Bit 31:24 bottom of region55 output value
8000 //Bit 23:16 bottom of region54 output value
8001 //Bit 15:8 bottom of region53 output value
8002 //Bit 7:0 bottom of region52 output value
8003 #define VPP2_DNLP_CTRL_13 (0x198e)
8004 #define P_VPP2_DNLP_CTRL_13 (volatile uint32_t *)((0x198e << 2) + 0xff900000)
8005 //Bit 31:24 bottom of region59 output value
8006 //Bit 23:16 bottom of region58 output value
8007 //Bit 15:8 bottom of region57 output value
8008 //Bit 7:0 bottom of region56 output value
8009 #define VPP2_DNLP_CTRL_14 (0x198f)
8010 #define P_VPP2_DNLP_CTRL_14 (volatile uint32_t *)((0x198f << 2) + 0xff900000)
8011 //Bit 31:24 bottom of region63 output value
8012 //Bit 23:16 bottom of region62 output value
8013 //Bit 15:8 bottom of region61 output value
8014 //Bit 7:0 bottom of region60 output value
8015 #define VPP2_DNLP_CTRL_15 (0x1990)
8016 #define P_VPP2_DNLP_CTRL_15 (volatile uint32_t *)((0x1990 << 2) + 0xff900000)
8017 //Bit 20 reserved
8018 //Bit 19 reserved
8019 //Bit 18 demo dynamic nonlinear luma processing enable
8020 //Bit 17 reserved
8021 //Bit 16 reserved
8022 //Bit 15:14, 2'b00: demo adjust on top, 2'b01: demo adjust on bottom, 2'b10: demo adjust on left, 2'b11: demo adjust on right
8023 //Bit 4 reserved
8024 //Bit 3 reserved
8025 //Bit 2 dynamic nonlinear luma processing enable
8026 //Bit 1 reserved
8027 //Bit 0 reserved
8028 #define VPP2_VE_ENABLE_CTRL (0x19a1)
8029 #define P_VPP2_VE_ENABLE_CTRL (volatile uint32_t *)((0x19a1 << 2) + 0xff900000)
8030 //Bit 12:0, demo left or top screen width
8031 #define VPP2_VE_DEMO_LEFT_TOP_SCREEN_WIDTH (0x19a2)
8032 #define P_VPP2_VE_DEMO_LEFT_TOP_SCREEN_WIDTH (volatile uint32_t *)((0x19a2 << 2) + 0xff900000)
8033 #define VPP2_VE_DEMO_CENTER_BAR (0x19a3)
8034 #define P_VPP2_VE_DEMO_CENTER_BAR (volatile uint32_t *)((0x19a3 << 2) + 0xff900000)
8035 //28:16 ve_line_length
8036 //12:0 ve_pic_height
8037 #define VPP2_VE_H_V_SIZE (0x19a4)
8038 #define P_VPP2_VE_H_V_SIZE (volatile uint32_t *)((0x19a4 << 2) + 0xff900000)
8039 //Bit 10 reset bit, high active
8040 //Bit 9 0: measuring rising edge, 1: measuring falling edge
8041 //Bit 8 if true, accumulate the counter number, otherwise not
8042 //Bit 7:0 vsync_span, define how many vsync span need to measure
8043 #define VPP2_VDO_MEAS_CTRL (0x19a8)
8044 #define P_VPP2_VDO_MEAS_CTRL (volatile uint32_t *)((0x19a8 << 2) + 0xff900000)
8045 //Read only
8046 //19:16 ind_meas_count_n, every number of sync_span vsyncs, this counter add 1
8047 //15:0, high bit portion of counter
8048 #define VPP2_VDO_MEAS_VS_COUNT_HI (0x19a9)
8049 #define P_VPP2_VDO_MEAS_VS_COUNT_HI (volatile uint32_t *)((0x19a9 << 2) + 0xff900000)
8050 //Read only
8051 //31:0, low bit portion of counter
8052 #define VPP2_VDO_MEAS_VS_COUNT_LO (0x19aa)
8053 #define P_VPP2_VDO_MEAS_VS_COUNT_LO (volatile uint32_t *)((0x19aa << 2) + 0xff900000)
8054 //vertical scaler phase step
8055 //Bit 27:0, 4.24 format
8056 #define VPP2_OSD_VSC_PHASE_STEP (0x19c0)
8057 #define P_VPP2_OSD_VSC_PHASE_STEP (volatile uint32_t *)((0x19c0 << 2) + 0xff900000)
8058 //Bit 31:16, botttom vertical scaler initial phase
8059 //Bit 15:0, top vertical scaler initial phase
8060 #define VPP2_OSD_VSC_INI_PHASE (0x19c1)
8061 #define P_VPP2_OSD_VSC_INI_PHASE (volatile uint32_t *)((0x19c1 << 2) + 0xff900000)
8062 //Bit 24 osd vertical Scaler enable
8063 //Bit 23 osd_prog_interlace 0: current field is progressive, 1: current field is interlace
8064 //Bit 22:21 osd_vsc_double_line_mode, bit1, double input width and half input height, bit0, change line buffer becomes 2 lines
8065 //Bit 20 osd_vsc_phase0_always_en
8066 //Bit 19 osd_vsc_nearest_en
8067 //Bit 17:16 osd_vsc_bot_rpt_l0_num
8068 //Bit 14:11 osd_vsc_bot_ini_rcv_num
8069 //Bit 9:8 osd_vsc_top_rpt_l0_num
8070 //Bit 6:3 osd_vsc_top_ini_rcv_num
8071 //Bit 2:0 osd_vsc_bank_length
8072 #define VPP2_OSD_VSC_CTRL0 (0x19c2)
8073 #define P_VPP2_OSD_VSC_CTRL0 (volatile uint32_t *)((0x19c2 << 2) + 0xff900000)
8074 //horizontal scaler phase step
8075 //Bit 27:0, 4.24 format
8076 #define VPP2_OSD_HSC_PHASE_STEP (0x19c3)
8077 #define P_VPP2_OSD_HSC_PHASE_STEP (volatile uint32_t *)((0x19c3 << 2) + 0xff900000)
8078 //Bit 31:16, horizontal scaler initial phase1
8079 //Bit 15:0, horizontal scaler initial phase0
8080 #define VPP2_OSD_HSC_INI_PHASE (0x19c4)
8081 #define P_VPP2_OSD_HSC_INI_PHASE (volatile uint32_t *)((0x19c4 << 2) + 0xff900000)
8082 //Bit 22 osd horizontal scaler enable
8083 //Bit 21 osd_hsc_double_pix_mode
8084 //Bit 20 osd_hsc_phase0_always_en
8085 //Bit 19 osd_hsc_nearest_en
8086 //Bit 17:16 osd_hsc_rpt_p0_num1
8087 //Bit 14:11 osd_hsc_ini_rcv_num1
8088 //Bit 9:8 osd_hsc_rpt_p0_num0
8089 //Bit 6:3 osd_hsc_ini_rcv_num0
8090 //Bit 2:0 osd_hsc_bank_length
8091 #define VPP2_OSD_HSC_CTRL0 (0x19c5)
8092 #define P_VPP2_OSD_HSC_CTRL0 (volatile uint32_t *)((0x19c5 << 2) + 0xff900000)
8093 //for 3D quincunx sub-sampling
8094 //bit 15:8 pattern, each patten 1 bit, from lsb -> msb
8095 //bit 6:4 pattern start
8096 //bit 2:0 pattern end
8097 #define VPP2_OSD_HSC_INI_PAT_CTRL (0x19c6)
8098 #define P_VPP2_OSD_HSC_INI_PAT_CTRL (volatile uint32_t *)((0x19c6 << 2) + 0xff900000)
8099 //bit 31:24, componet 0
8100 //bit 23:16, component 1
8101 //bit 15:8, component 2
8102 //bit 7:0 component 3, alpha
8103 #define VPP2_OSD_SC_DUMMY_DATA (0x19c7)
8104 #define P_VPP2_OSD_SC_DUMMY_DATA (volatile uint32_t *)((0x19c7 << 2) + 0xff900000)
8105 //Bit 14 osc_sc_din_osd1_alpha_mode, 1: (alpha >= 128) ? alpha -1: alpha, 0: (alpha >=1) ? alpha - 1: alpha.
8106 //Bit 13 osc_sc_din_osd2_alpha_mode, 1: (alpha >= 128) ? alpha -1: alpha, 0: (alpha >=1) ? alpha - 1: alpha.
8107 //Bit 12 osc_sc_dout_alpha_mode, 1: (alpha >= 128) ? alpha + 1: alpha, 0: (alpha >=1) ? alpha + 1: alpha.
8108 //Bit 12 osc_sc_alpha_mode, 1: (alpha >= 128) ? alpha + 1: alpha, 0: (alpha >=1) ? alpha + 1: alpha.
8109 //Bit 11:4 default alpha for vd1 or vd2 if they are selected as the source
8110 //Bit 3 osd scaler path enable
8111 //Bit 1:0 osd_sc_sel, 00: select osd1 input, 01: select osd2 input, 10: select vd1 input, 11: select vd2 input after matrix
8112 #define VPP2_OSD_SC_CTRL0 (0x19c8)
8113 #define P_VPP2_OSD_SC_CTRL0 (volatile uint32_t *)((0x19c8 << 2) + 0xff900000)
8114 //Bit 28:16 OSD scaler input width minus 1
8115 //Bit 12:0 OSD scaler input height minus 1
8116 #define VPP2_OSD_SCI_WH_M1 (0x19c9)
8117 #define P_VPP2_OSD_SCI_WH_M1 (volatile uint32_t *)((0x19c9 << 2) + 0xff900000)
8118 //Bit 28:16 OSD scaler output horizontal start
8119 //Bit 12:0 OSD scaler output horizontal end
8120 #define VPP2_OSD_SCO_H_START_END (0x19ca)
8121 #define P_VPP2_OSD_SCO_H_START_END (volatile uint32_t *)((0x19ca << 2) + 0xff900000)
8122 //Bit 28:16 OSD scaler output vertical start
8123 //Bit 12:0 OSD scaler output vertical end
8124 #define VPP2_OSD_SCO_V_START_END (0x19cb)
8125 #define P_VPP2_OSD_SCO_V_START_END (volatile uint32_t *)((0x19cb << 2) + 0xff900000)
8126 //Because there are many coefficients used in the vertical filter and horizontal filters,
8127 //indirect access the coefficients of vertical filter and horizontal filter is used.
8128 //For vertical filter, there are 33x4 coefficients
8129 //For horizontal filter, there are 33x4 coefficients
8130 //Bit 15 index increment, if bit9 == 1 then (0: index increase 1, 1: index increase 2) else (index increase 2)
8131 //Bit 14 1: read coef through cbus enable, just for debug purpose in case when we wanna check the coef in ram in correct or not
8132 //Bit 9 if true, use 9bit resolution coef, other use 8bit resolution coef
8133 //Bit 8 type of index, 0: vertical coef, 1: horizontal coef
8134 //Bit 6:0 coef index
8135 #define VPP2_OSD_SCALE_COEF_IDX (0x19cc)
8136 #define P_VPP2_OSD_SCALE_COEF_IDX (volatile uint32_t *)((0x19cc << 2) + 0xff900000)
8137 //coefficients for vertical filter and horizontal filter
8138 #define VPP2_OSD_SCALE_COEF (0x19cd)
8139 #define P_VPP2_OSD_SCALE_COEF (volatile uint32_t *)((0x19cd << 2) + 0xff900000)
8140 //Bit 12:0 line number use to generate interrupt when line == this number
8141 #define VPP2_INT_LINE_NUM (0x19ce)
8142 #define P_VPP2_INT_LINE_NUM (volatile uint32_t *)((0x19ce << 2) + 0xff900000)
8143 // synopsys translate_off
8144 // synopsys translate_on
8145 //
8146 // Closing file: vpp2_regs.h
8147 //
8148 //`define VIU_VCBUS_BASE 8'h1a
8149 //
8150 // Reading file: vregs_clk2.h
8151 //
8152 //===========================================================================
8153 // Video Interface Registers 0xa00 - 0xaff
8154 //===========================================================================
8155 // -----------------------------------------------
8156 // CBUS_BASE: VIU_VCBUS_BASE = 0x1a
8157 // -----------------------------------------------
8158 #define VIU_ADDR_START (0x1a00)
8159 #define P_VIU_ADDR_START (volatile uint32_t *)((0x1a00 << 2) + 0xff900000)
8160 #define VIU_ADDR_END (0x1aff)
8161 #define P_VIU_ADDR_END (volatile uint32_t *)((0x1aff << 2) + 0xff900000)
8162 //`define TRACE_REG 8'ff
8163 //------------------------------------------------------------------------------
8164 // VIU top-level registers
8165 //------------------------------------------------------------------------------
8166 // Bit 0 RW, osd1_reset
8167 // Bit 1 RW, osd2_reset
8168 // Bit 2 RW, vd1_reset
8169 // Bit 3 RW, vd1_fmt_reset
8170 // Bit 4 RW, vd2_reset
8171 // Bit 5 RW, vd2_fmt_reset
8172 // Bit 6 RW, di_dsr1to2_reset
8173 // Bit 7 RW, vpp_reset
8174 // Bit 8 RW, di_if1_reset
8175 // Bit 9 RW, di_if1_fmt_reset
8176 // Bit 10 RW, di_inp_reset
8177 // Bit 11 RW, di_inp_fmt_reset
8178 // Bit 12 RW, di_mem_reset
8179 // Bit 13 RW, di_mem_fmt_reset
8180 // Bit 14 RW, di_nr_wr_mif_reset
8181 // Bit 15 RW, dein_wr_mif_reset
8182 // Bit 16 RW, di_chan2_mif_reset
8183 // Bit 17 RW, di_mtn_wr_mif_reset
8184 // Bit 18 RW, di_mtn_rd_mif_reset
8185 // Bit 19 RW, di_mad_reset
8186 // Bit 20 RW, vdin0_reset
8187 // Bit 21 RW, vdin1_reset
8188 // Bit 22 RW, nrin_mux_reset
8189 // Bit 23 RW, vdin0_wr_reset
8190 // Bit 24 RW, vdin1_wr_reset
8191 // Bit 25 RW, reserved
8192 // Bit 26 RW, d2d3_reset
8193 // Bit 27 RW, di_cont_wr_mif_reset
8194 // Bit 28 RW, di_cont_rd_mif_reset
8195 #define VIU_SW_RESET (0x1a01)
8196 #define P_VIU_SW_RESET (volatile uint32_t *)((0x1a01 << 2) + 0xff900000)
8197 #define VIU_SW_RESET0 (0x1a02)
8198 #define P_VIU_SW_RESET0 (volatile uint32_t *)((0x1a02 << 2) + 0xff900000)
8199 // Bit 0 RW, software reset for mcvecrd_mif
8200 // Bit 1 RW, software reset for mcinfowr_mif
8201 // Bit 2 RW, software reset for mcinford_mif
8202 #define VIU_SECURE_REG (0x1a04)
8203 #define P_VIU_SECURE_REG (volatile uint32_t *)((0x1a04 << 2) + 0xff900000)
8204 // Bit 0 RW, dolby core1_tv secure w and r
8205 // Bit 1 RW, dolby core2 secure w and r
8206 // Bit 2 RW, dolby core3 secure w and r
8207 // Bit 3 RW, for osd1 secure read
8208 // Bit 4 RW, for osd2 secure read
8209 #define DOLBY_INT_STAT (0x1a05)
8210 #define P_DOLBY_INT_STAT (volatile uint32_t *)((0x1a05 << 2) + 0xff900000)
8211 // todo
8212 //bit 15:12 osdbld_gclk_ctrl 3:2 regclk ctrl 1:0 blending clk control
8213 //bit 8 if true, vsync interrup is generate only field == 0
8214 //bit 7:0 fix_disable
8215 #define VIU_MISC_CTRL0 (0x1a06)
8216 #define P_VIU_MISC_CTRL0 (volatile uint32_t *)((0x1a06 << 2) + 0xff900000)
8217 #define VIU_MISC_CTRL1 (0x1a07)
8218 #define P_VIU_MISC_CTRL1 (volatile uint32_t *)((0x1a07 << 2) + 0xff900000)
8219 // Bit 15:14 mali_afbcd_gclk_ctrl mali_afbcd clock gate control[5:4]
8220 // Bit 12 osd1_afbcd_axi_mux 0 : use the osd mif as input; 1 : use afbcd as input
8221 // Bit 11:8 mali_afbcd_gclk_ctrl mali_afbcd clock gate control[3:0]
8222 // Bit 7:2 vd2_afbcd_gclk_ctrl vd2_afbcd clock gate control
8223 // Bit 1 vpp_vd2_din_sel 0: vpp vd2 sel the mif input; 1: vpp vd2 sel the dos afbcd
8224 // Bit 0 vd2_afbcd_out_sel 0: vd2_afbcd output to vpp; 1 : vd2_afbcd output to di inp
8225 #define D2D3_INTF_LENGTH (0x1a08)
8226 #define P_D2D3_INTF_LENGTH (volatile uint32_t *)((0x1a08 << 2) + 0xff900000)
8227 // Bit 31:30 vdin0 dout splitter, bit 0 turns on vdin0 to old path, bit 1 turns on vdin0 to d2d3_intf vdin0 input path
8228 // Bit 29:28 vdin1 dout splitter, bit 0 turns on vdin1 to old path, bit 1 turns on vdin1 to d2d3_intf vdin1 input path
8229 // Bit 27:26 NR write dout splitter, bit 0 turns on NR write to old path, bit 1 turns on NR WR to d2d3_intf NR WR input path
8230 // Bit 23 if true, turn on clk_d2d3_reg (register clock)
8231 // Bit 22 if true, turn on clk_d2d3
8232 // Bit 21 reg_v1_go_line
8233 // Bit 20 reg_v1_go_field
8234 // Bit 19 reg_v0_go_field
8235 // Bit 18:16 v1_gofld_sel, 000: display go_field/go_line, 001: DI pre_frame_rst/go_line, 010: vdin0 go_field/go_line,
8236 //011: vdin1 go_field/go_line, otherwise: force go_field by reg_v1_go_field(bit20), force go_line by reg_v1_go_line(bit21)
8237 // Bit 15:13 v0_gofld_sel, 000: display go_field, 001: DI pre_frame_rst, 010: vdin0 go_field, 011: vdin1 go_field, otherwise: force go_field by
8238 // reg_v0_go_field(bit19)
8239 // Bit 12:6 hole_lines for d2d3 depth read interface
8240 // Bit 5:4 d2d3_v1_sel, 2'b01: video display read interface(DI or vd1 fomart output), 2'b10: scale output, otherwise nothing as v1
8241 // Bit 3 use_vdin_eol, if true, use vdin eol as the v0_eol, otherwise using length to get the v0_eol
8242 // Bit 2:0 d2d3_v0_sel 001: vdin0, 010: vdin1, 011: NRW, 100: video display read interface(DI or vd1 fomart output), 101: vpp scale output
8243 //
8244 #define D2D3_INTF_CTRL0 (0x1a09)
8245 #define P_D2D3_INTF_CTRL0 (volatile uint32_t *)((0x1a09 << 2) + 0xff900000)
8246 //------------------------------------------------------------------------------
8247 // OSD1 registers
8248 //------------------------------------------------------------------------------
8249 // Bit 31 Reserved
8250 // Bit 30 RW, enable_free_clk: 1=use free-running clock to drive logics;
8251 // 0=use gated clock for low power.
8252 // Bit 29 R, test_rd_dsr
8253 // Bit 28 R, osd_done
8254 // Bit 27:24 R, osd_blk_mode
8255 // Bit 23:22 R, osd_blk_ptr
8256 // Bit 21 R, osd_enable
8257 //
8258 // Bit 20:12 RW, global_alpha
8259 // Bit 11 RW, test_rd_en
8260 // Bit 10: 9 Reserved for control signals
8261 // Bit 8: 5 RW, ctrl_mtch_y
8262 // Bit 4 RW, ctrl_422to444
8263 // Bit 3: 0 RW, osd_blk_enable. Bit 0 to enable block 0: 1=enable, 0=disable;
8264 // Bit 1 to enable block 1, and so on.
8265 #define VIU_OSD1_CTRL_STAT (0x1a10)
8266 #define P_VIU_OSD1_CTRL_STAT (volatile uint32_t *)((0x1a10 << 2) + 0xff900000)
8267 // Bit 31:26 Reserved
8268 // Bit 25:16 R, fifo_count
8269 // Bit 15 RW, osd_dpath_sel 0-osd1 mif 1-vpu mali afbcd
8270 // Bit 14 RW, replaced_alpha_en
8271 // Bit 13: 6 RW, replaced_alpha
8272 // Bit 5: 4 RW, hold_fifo_lines[6:5]
8273 // Bit 3 RW, rgb2yuv_full_range
8274 // Bit 2 RW, alpha_9b_mode
8275 // Bit 1 RW, reserved
8276 // Bit 0 RW, color_expand_mode
8277 #define VIU_OSD1_CTRL_STAT2 (0x1a2d)
8278 #define P_VIU_OSD1_CTRL_STAT2 (volatile uint32_t *)((0x1a2d << 2) + 0xff900000)
8279 // Bit 31: 9 Reserved
8280 // Bit 8 RW, 0 = Write LUT, 1 = Read LUT
8281 // Bit 7: 0 RW, lut_addr
8282 #define VIU_OSD1_COLOR_ADDR (0x1a11)
8283 #define P_VIU_OSD1_COLOR_ADDR (volatile uint32_t *)((0x1a11 << 2) + 0xff900000)
8284 // Bit 31:24 RW, Y or R
8285 // Bit 23:16 RW, Cb or G
8286 // Bit 15: 8 RW, Cr or B
8287 // Bit 7: 0 RW, Alpha
8288 #define VIU_OSD1_COLOR (0x1a12)
8289 #define P_VIU_OSD1_COLOR (volatile uint32_t *)((0x1a12 << 2) + 0xff900000)
8290 // Bit 31:24 RW, Y or R
8291 // Bit 23:16 RW, Cb or G
8292 // Bit 15: 8 RW, Cr or B
8293 // Bit 7: 0 RW, Alpha
8294 #define VIU_OSD1_TCOLOR_AG0 (0x1a17)
8295 #define P_VIU_OSD1_TCOLOR_AG0 (volatile uint32_t *)((0x1a17 << 2) + 0xff900000)
8296 #define VIU_OSD1_TCOLOR_AG1 (0x1a18)
8297 #define P_VIU_OSD1_TCOLOR_AG1 (volatile uint32_t *)((0x1a18 << 2) + 0xff900000)
8298 #define VIU_OSD1_TCOLOR_AG2 (0x1a19)
8299 #define P_VIU_OSD1_TCOLOR_AG2 (volatile uint32_t *)((0x1a19 << 2) + 0xff900000)
8300 #define VIU_OSD1_TCOLOR_AG3 (0x1a1a)
8301 #define P_VIU_OSD1_TCOLOR_AG3 (volatile uint32_t *)((0x1a1a << 2) + 0xff900000)
8302 // Bit 31:30 Reserved
8303 // Bit 29 RW, y_rev: 0=normal read, 1=reverse read in Y direction
8304 // Bit 28 RW, x_rev: 0=normal read, 1=reverse read in X direction
8305 // Bit 27:24 Reserved
8306 // Bit 23:16 RW, tbl_addr
8307 // Bit 15 RW, little_endian: 0=big endian, 1=little endian
8308 // Bit 14 RW, rpt_y
8309 // Bit 13:12 RW, interp_ctrl. 0x=No interpolation; 10=Interpolate with previous
8310 // pixel; 11=Interpolate with the average value
8311 // between previous and next pixel.
8312 // Bit 11: 8 RW, osd_blk_mode
8313 // Bit 7 RW, rgb_en
8314 // Bit 6 RW, tc_alpha_en
8315 // Bit 5: 2 RW, color_matrix
8316 // Bit 1 RW, interlace_en
8317 // Bit 0 RW, interlace_sel_odd
8318 #define VIU_OSD1_BLK0_CFG_W0 (0x1a1b)
8319 #define P_VIU_OSD1_BLK0_CFG_W0 (volatile uint32_t *)((0x1a1b << 2) + 0xff900000)
8320 #define VIU_OSD1_BLK1_CFG_W0 (0x1a1f)
8321 #define P_VIU_OSD1_BLK1_CFG_W0 (volatile uint32_t *)((0x1a1f << 2) + 0xff900000)
8322 #define VIU_OSD1_BLK2_CFG_W0 (0x1a23)
8323 #define P_VIU_OSD1_BLK2_CFG_W0 (volatile uint32_t *)((0x1a23 << 2) + 0xff900000)
8324 #define VIU_OSD1_BLK3_CFG_W0 (0x1a27)
8325 #define P_VIU_OSD1_BLK3_CFG_W0 (volatile uint32_t *)((0x1a27 << 2) + 0xff900000)
8326 // Bit 31:29 Reserved
8327 // Bit 28:16 RW, x_end
8328 // Bit 15:13 Reserved
8329 // Bit 12: 0 RW, x_start
8330 #define VIU_OSD1_BLK0_CFG_W1 (0x1a1c)
8331 #define P_VIU_OSD1_BLK0_CFG_W1 (volatile uint32_t *)((0x1a1c << 2) + 0xff900000)
8332 #define VIU_OSD1_BLK1_CFG_W1 (0x1a20)
8333 #define P_VIU_OSD1_BLK1_CFG_W1 (volatile uint32_t *)((0x1a20 << 2) + 0xff900000)
8334 #define VIU_OSD1_BLK2_CFG_W1 (0x1a24)
8335 #define P_VIU_OSD1_BLK2_CFG_W1 (volatile uint32_t *)((0x1a24 << 2) + 0xff900000)
8336 #define VIU_OSD1_BLK3_CFG_W1 (0x1a28)
8337 #define P_VIU_OSD1_BLK3_CFG_W1 (volatile uint32_t *)((0x1a28 << 2) + 0xff900000)
8338 // Bit 31:29 Reserved
8339 // Bit 28:16 RW, y_end
8340 // Bit 15:13 Reserved
8341 // Bit 12: 0 RW, y_start
8342 #define VIU_OSD1_BLK0_CFG_W2 (0x1a1d)
8343 #define P_VIU_OSD1_BLK0_CFG_W2 (volatile uint32_t *)((0x1a1d << 2) + 0xff900000)
8344 #define VIU_OSD1_BLK1_CFG_W2 (0x1a21)
8345 #define P_VIU_OSD1_BLK1_CFG_W2 (volatile uint32_t *)((0x1a21 << 2) + 0xff900000)
8346 #define VIU_OSD1_BLK2_CFG_W2 (0x1a25)
8347 #define P_VIU_OSD1_BLK2_CFG_W2 (volatile uint32_t *)((0x1a25 << 2) + 0xff900000)
8348 #define VIU_OSD1_BLK3_CFG_W2 (0x1a29)
8349 #define P_VIU_OSD1_BLK3_CFG_W2 (volatile uint32_t *)((0x1a29 << 2) + 0xff900000)
8350 // Bit 31:28 Reserved
8351 // Bit 27:16 RW, h_end
8352 // Bit 15:12 Reserved
8353 // Bit 11: 0 RW, h_start
8354 #define VIU_OSD1_BLK0_CFG_W3 (0x1a1e)
8355 #define P_VIU_OSD1_BLK0_CFG_W3 (volatile uint32_t *)((0x1a1e << 2) + 0xff900000)
8356 #define VIU_OSD1_BLK1_CFG_W3 (0x1a22)
8357 #define P_VIU_OSD1_BLK1_CFG_W3 (volatile uint32_t *)((0x1a22 << 2) + 0xff900000)
8358 #define VIU_OSD1_BLK2_CFG_W3 (0x1a26)
8359 #define P_VIU_OSD1_BLK2_CFG_W3 (volatile uint32_t *)((0x1a26 << 2) + 0xff900000)
8360 #define VIU_OSD1_BLK3_CFG_W3 (0x1a2a)
8361 #define P_VIU_OSD1_BLK3_CFG_W3 (volatile uint32_t *)((0x1a2a << 2) + 0xff900000)
8362 // Bit 31:28 Reserved
8363 // Bit 27:16 RW, v_end
8364 // Bit 15:12 Reserved
8365 // Bit 11: 0 RW, v_start
8366 #define VIU_OSD1_BLK0_CFG_W4 (0x1a13)
8367 #define P_VIU_OSD1_BLK0_CFG_W4 (volatile uint32_t *)((0x1a13 << 2) + 0xff900000)
8368 #define VIU_OSD1_BLK1_CFG_W4 (0x1a14)
8369 #define P_VIU_OSD1_BLK1_CFG_W4 (volatile uint32_t *)((0x1a14 << 2) + 0xff900000)
8370 #define VIU_OSD1_BLK2_CFG_W4 (0x1a15)
8371 #define P_VIU_OSD1_BLK2_CFG_W4 (volatile uint32_t *)((0x1a15 << 2) + 0xff900000)
8372 #define VIU_OSD1_BLK3_CFG_W4 (0x1a16)
8373 #define P_VIU_OSD1_BLK3_CFG_W4 (volatile uint32_t *)((0x1a16 << 2) + 0xff900000)
8374 // Bit 31 RW, burst_len_sel[2] of [2:0]
8375 // Bit 30 RW, byte_swap: In addition to endian control, further define
8376 // whether to swap upper and lower byte within a 16-bit mem word.
8377 // 0=No swap; 1=Swap data[15:0] to be {data[7:0], data[15:8]}
8378 // Bit 29 RW, div_swap : swap the 2 64bits words in 128 bit word
8379 // Bit 28:24 RW, fifo_lim : when osd fifo is small than the fifo_lim*16, closed the rq port of osd_rd_mif
8380 // Bit 23:22 RW, fifo_ctrl: 00 : for 1 word in 1 burst , 01 : for 2words in 1burst, 10: for 4words in 1burst, 11: reserved
8381 // Bit 21:20 R, fifo_st. 0=IDLE, 1=FILL, 2=ABORT
8382 // Bit 19 R, fifo_overflow
8383 // Bit 18:12 RW, fifo_depth_val, max value=64: set actual fifo depth to fifo_depth_val*8.
8384 // Bit 11:10 RW, burst_len_sel[1:0] of [2:0]. 0=24(default), 1=32, 2=48, 3=64, 4=96, 5=128.
8385 // Bit 9: 5 RW, hold_fifo_lines[4:0]
8386 // Bit 4 RW, clear_err: one pulse to clear fifo_overflow
8387 // Bit 3 RW, fifo_sync_rst
8388 // Bit 2: 1 RW, endian
8389 // Bit 0 RW, urgent
8390 #define VIU_OSD1_FIFO_CTRL_STAT (0x1a2b)
8391 #define P_VIU_OSD1_FIFO_CTRL_STAT (volatile uint32_t *)((0x1a2b << 2) + 0xff900000)
8392 // Bit 31:24 R, Y or R
8393 // Bit 23:16 R, Cb or G
8394 // Bit 15: 8 R, Cr or B
8395 // Bit 7: 0 R, Output Alpha[8:1]
8396 #define VIU_OSD1_TEST_RDDATA (0x1a2c)
8397 #define P_VIU_OSD1_TEST_RDDATA (volatile uint32_t *)((0x1a2c << 2) + 0xff900000)
8398 // Bit 15 RW, prot_en: 1=Borrow PROT's FIFO storage, either for rotate or non-rotate.
8399 // Bit 12: 0 RW, effective FIFO size when prot_en=1.
8400 #define VIU_OSD1_PROT_CTRL (0x1a2e)
8401 #define P_VIU_OSD1_PROT_CTRL (volatile uint32_t *)((0x1a2e << 2) + 0xff900000)
8402 //Bit 7, highlight_en
8403 //Bit 6 probe_post, if true, probe pixel data after matrix, otherwise probe pixel data before matrix
8404 //Bit 5:4 probe_sel, 00: select matrix 0, 01: select matrix 1, otherwise select nothing
8405 //Bit 3:2, matrix coef idx selection, 00: select mat0, 01: select mat1, otherwise slect nothing
8406 //Bit 1 mat1 conversion matrix enable
8407 //Bit 0 mat0 conversion matrix enable
8408 #define VIU_OSD1_MATRIX_CTRL (0x1a90)
8409 #define P_VIU_OSD1_MATRIX_CTRL (volatile uint32_t *)((0x1a90 << 2) + 0xff900000)
8410 //Bit 28:16 coef00
8411 //Bit 12:0 coef01
8412 #define VIU_OSD1_MATRIX_COEF00_01 (0x1a91)
8413 #define P_VIU_OSD1_MATRIX_COEF00_01 (volatile uint32_t *)((0x1a91 << 2) + 0xff900000)
8414 //Bit 28:16 coef02
8415 //Bit 12:0 coef10
8416 #define VIU_OSD1_MATRIX_COEF02_10 (0x1a92)
8417 #define P_VIU_OSD1_MATRIX_COEF02_10 (volatile uint32_t *)((0x1a92 << 2) + 0xff900000)
8418 //Bit 28:16 coef11
8419 //Bit 12:0 coef12
8420 #define VIU_OSD1_MATRIX_COEF11_12 (0x1a93)
8421 #define P_VIU_OSD1_MATRIX_COEF11_12 (volatile uint32_t *)((0x1a93 << 2) + 0xff900000)
8422 //Bit 28:16 coef20
8423 //Bit 12:0 coef21
8424 #define VIU_OSD1_MATRIX_COEF20_21 (0x1a94)
8425 #define P_VIU_OSD1_MATRIX_COEF20_21 (volatile uint32_t *)((0x1a94 << 2) + 0xff900000)
8426 //Bit 31:30 mat_clmod
8427 //Bit 18:16 mat_convrs
8428 //Bit 12:0 mat_coef42
8429 #define VIU_OSD1_MATRIX_COLMOD_COEF42 (0x1a95)
8430 #define P_VIU_OSD1_MATRIX_COLMOD_COEF42 (volatile uint32_t *)((0x1a95 << 2) + 0xff900000)
8431 //Bit 26:16 offset0
8432 //Bit 10:0 offset1
8433 #define VIU_OSD1_MATRIX_OFFSET0_1 (0x1a96)
8434 #define P_VIU_OSD1_MATRIX_OFFSET0_1 (volatile uint32_t *)((0x1a96 << 2) + 0xff900000)
8435 //Bit 10:0 offset2
8436 #define VIU_OSD1_MATRIX_OFFSET2 (0x1a97)
8437 #define P_VIU_OSD1_MATRIX_OFFSET2 (volatile uint32_t *)((0x1a97 << 2) + 0xff900000)
8438 //Bit 26:16 pre_offset0
8439 //Bit 10:0 pre_offset1
8440 #define VIU_OSD1_MATRIX_PRE_OFFSET0_1 (0x1a98)
8441 #define P_VIU_OSD1_MATRIX_PRE_OFFSET0_1 (volatile uint32_t *)((0x1a98 << 2) + 0xff900000)
8442 //Bit 10:0 pre_offset2
8443 #define VIU_OSD1_MATRIX_PRE_OFFSET2 (0x1a99)
8444 #define P_VIU_OSD1_MATRIX_PRE_OFFSET2 (volatile uint32_t *)((0x1a99 << 2) + 0xff900000)
8445 //Read only
8446 //Bit 29:20 component 0
8447 //Bit 19:10 component 1
8448 //Bit 9:0 component 2
8449 #define VIU_OSD1_MATRIX_PROBE_COLOR (0x1a9a)
8450 #define P_VIU_OSD1_MATRIX_PROBE_COLOR (volatile uint32_t *)((0x1a9a << 2) + 0xff900000)
8451 //Bit 23:16 component 0
8452 //Bit 15:8 component 1
8453 //Bit 7:0 component 2
8454 #define VIU_OSD1_MATRIX_HL_COLOR (0x1a9b)
8455 #define P_VIU_OSD1_MATRIX_HL_COLOR (volatile uint32_t *)((0x1a9b << 2) + 0xff900000)
8456 //28:16 probe x, postion
8457 //12:0 probe y, position
8458 #define VIU_OSD1_MATRIX_PROBE_POS (0x1a9c)
8459 #define P_VIU_OSD1_MATRIX_PROBE_POS (volatile uint32_t *)((0x1a9c << 2) + 0xff900000)
8460 //Bit 28:16 coef22
8461 //Bit 12:0 coef30
8462 #define VIU_OSD1_MATRIX_COEF22_30 (0x1a9d)
8463 #define P_VIU_OSD1_MATRIX_COEF22_30 (volatile uint32_t *)((0x1a9d << 2) + 0xff900000)
8464 //Bit 28:16 coef31
8465 //Bit 12:0 coef32
8466 #define VIU_OSD1_MATRIX_COEF31_32 (0x1a9e)
8467 #define P_VIU_OSD1_MATRIX_COEF31_32 (volatile uint32_t *)((0x1a9e << 2) + 0xff900000)
8468 //Bit 28:16 coef40
8469 //Bit 12:0 coef41
8470 #define VIU_OSD1_MATRIX_COEF40_41 (0x1a9f)
8471 #define P_VIU_OSD1_MATRIX_COEF40_41 (volatile uint32_t *)((0x1a9f << 2) + 0xff900000)
8472 //Bit 31:27 for all [31] for all eotf enable,[30] for matrix3x3 enable, [29:27] for eotf_ch0~3
8473 //Bit 17:6 for clock gating
8474 //Bit 5:4 pscale_mode ch2
8475 //Bit 3:2 pscale_mode ch1
8476 //Bit 1:0 pscale_mode ch0
8477 #define VIU_OSD1_EOTF_CTL (0x1ad4)
8478 #define P_VIU_OSD1_EOTF_CTL (volatile uint32_t *)((0x1ad4 << 2) + 0xff900000)
8479 //Bit 28:16 coef00
8480 //Bit 12:0 coef01
8481 #define VIU_OSD1_EOTF_COEF00_01 (0x1ad5)
8482 #define P_VIU_OSD1_EOTF_COEF00_01 (volatile uint32_t *)((0x1ad5 << 2) + 0xff900000)
8483 //Bit 28:16 coef02
8484 //Bit 12:0 coef10
8485 #define VIU_OSD1_EOTF_COEF02_10 (0x1ad6)
8486 #define P_VIU_OSD1_EOTF_COEF02_10 (volatile uint32_t *)((0x1ad6 << 2) + 0xff900000)
8487 //Bit 28:16 coef11
8488 //Bit 12:0 coef12
8489 #define VIU_OSD1_EOTF_COEF11_12 (0x1ad7)
8490 #define P_VIU_OSD1_EOTF_COEF11_12 (volatile uint32_t *)((0x1ad7 << 2) + 0xff900000)
8491 //Bit 28:16 coef20
8492 //Bit 12:0 coef21
8493 #define VIU_OSD1_EOTF_COEF20_21 (0x1ad8)
8494 #define P_VIU_OSD1_EOTF_COEF20_21 (volatile uint32_t *)((0x1ad8 << 2) + 0xff900000)
8495 //Bit 28:16 coef22
8496 //Bit 2:0 coef_rs
8497 #define VIU_OSD1_EOTF_COEF22_RS (0x1ad9)
8498 #define P_VIU_OSD1_EOTF_COEF22_RS (volatile uint32_t *)((0x1ad9 << 2) + 0xff900000)
8499 #define VIU_OSD1_EOTF_LUT_ADDR_PORT (0x1ada)
8500 #define P_VIU_OSD1_EOTF_LUT_ADDR_PORT (volatile uint32_t *)((0x1ada << 2) + 0xff900000)
8501 #define VIU_OSD1_EOTF_LUT_DATA_PORT (0x1adb)
8502 #define P_VIU_OSD1_EOTF_LUT_DATA_PORT (volatile uint32_t *)((0x1adb << 2) + 0xff900000)
8503 //Bit 31:29 for OETF ch0~ch2
8504 //Bit 21:12 for clock gating
8505 //Bit 11:8 for oetf_scl_ch2
8506 //Bit 7:4 for oetf_scl_ch1
8507 //Bit 3:0 for oetf_scl_ch0
8508 #define VIU_OSD1_OETF_CTL (0x1adc)
8509 #define P_VIU_OSD1_OETF_CTL (volatile uint32_t *)((0x1adc << 2) + 0xff900000)
8510 #define VIU_OSD1_OETF_LUT_ADDR_PORT (0x1add)
8511 #define P_VIU_OSD1_OETF_LUT_ADDR_PORT (volatile uint32_t *)((0x1add << 2) + 0xff900000)
8512 #define VIU_OSD1_OETF_LUT_DATA_PORT (0x1ade)
8513 #define P_VIU_OSD1_OETF_LUT_DATA_PORT (volatile uint32_t *)((0x1ade << 2) + 0xff900000)
8514 #define VIU_OSD1_OETF_3X3_OFST_0 (0x1aa0)
8515 #define P_VIU_OSD1_OETF_3X3_OFST_0 (volatile uint32_t *)((0x1aa0 << 2) + 0xff900000)
8516 #define VIU_OSD1_OETF_3X3_OFST_1 (0x1aa1)
8517 #define P_VIU_OSD1_OETF_3X3_OFST_1 (volatile uint32_t *)((0x1aa1 << 2) + 0xff900000)
8518 //------------------------------------------------------------------------------
8519 // OSD2 registers
8520 //------------------------------------------------------------------------------
8521 // Bit 31 Reserved
8522 // Bit 30 RW, enable_free_clk: 1=use free-running clock to drive logics;
8523 // 0=use gated clock for low power.
8524 // Bit 29 R, test_rd_dsr
8525 // Bit 28 R, osd_done
8526 // Bit 27:24 R, osd_blk_mode
8527 // Bit 23:22 R, osd_blk_ptr
8528 // Bit 21 R, osd_enable
8529 //
8530 // Bit 20:12 RW, global_alpha
8531 // Bit 11 RW, test_rd_en
8532 // Bit 10 RW, hl2_en
8533 // Bit 9 RW, hl1_en
8534 // Bit 8: 5 RW, ctrl_mtch_y
8535 // Bit 4 RW, ctrl_422to444
8536 // Bit 3: 0 RW, osd_blk_enable. Bit 0 to enable block 0: 1=enable, 0=disable;
8537 // Bit 1 to enable block 1, and so on.
8538 #define VIU_OSD2_CTRL_STAT (0x1a30)
8539 #define P_VIU_OSD2_CTRL_STAT (volatile uint32_t *)((0x1a30 << 2) + 0xff900000)
8540 // Bit 31:26 Reserved
8541 // Bit 25:16 R, fifo_count
8542 // Bit 15 Reserved
8543 // Bit 14 RW, replaced_alpha_en
8544 // Bit 13: 6 RW, replaced_alpha
8545 // Bit 5: 4 RW, hold_fifo_lines[6:5]
8546 // Bit 3 RW, rgb2yuv_full_range
8547 // Bit 2 RW, alpha_9b_mode
8548 // Bit 1 RW, reserved
8549 // Bit 0 RW, color_expand_mode
8550 #define VIU_OSD2_CTRL_STAT2 (0x1a4d)
8551 #define P_VIU_OSD2_CTRL_STAT2 (volatile uint32_t *)((0x1a4d << 2) + 0xff900000)
8552 // Bit 31: 9 Reserved
8553 // Bit 8 RW, 0 = Write LUT, 1 = Read LUT
8554 // Bit 7: 0 RW, lut_addr
8555 #define VIU_OSD2_COLOR_ADDR (0x1a31)
8556 #define P_VIU_OSD2_COLOR_ADDR (volatile uint32_t *)((0x1a31 << 2) + 0xff900000)
8557 // Bit 31:24 RW, Y or R
8558 // Bit 23:16 RW, Cb or G
8559 // Bit 15: 8 RW, Cr or B
8560 // Bit 7: 0 RW, Alpha
8561 #define VIU_OSD2_COLOR (0x1a32)
8562 #define P_VIU_OSD2_COLOR (volatile uint32_t *)((0x1a32 << 2) + 0xff900000)
8563 // Bit 31:28 Reserved
8564 // Bit 27:16 RW, hl[1-2]_h/v_start
8565 // Bit 15:12 Reserved
8566 // Bit 11: 0 RW, hl[1-2]_h/v_end
8567 #define VIU_OSD2_HL1_H_START_END (0x1a33)
8568 #define P_VIU_OSD2_HL1_H_START_END (volatile uint32_t *)((0x1a33 << 2) + 0xff900000)
8569 #define VIU_OSD2_HL1_V_START_END (0x1a34)
8570 #define P_VIU_OSD2_HL1_V_START_END (volatile uint32_t *)((0x1a34 << 2) + 0xff900000)
8571 #define VIU_OSD2_HL2_H_START_END (0x1a35)
8572 #define P_VIU_OSD2_HL2_H_START_END (volatile uint32_t *)((0x1a35 << 2) + 0xff900000)
8573 #define VIU_OSD2_HL2_V_START_END (0x1a36)
8574 #define P_VIU_OSD2_HL2_V_START_END (volatile uint32_t *)((0x1a36 << 2) + 0xff900000)
8575 // Bit 31:24 RW, Y or R
8576 // Bit 23:16 RW, Cb or G
8577 // Bit 15: 8 RW, Cr or B
8578 // Bit 7: 0 RW, Alpha
8579 #define VIU_OSD2_TCOLOR_AG0 (0x1a37)
8580 #define P_VIU_OSD2_TCOLOR_AG0 (volatile uint32_t *)((0x1a37 << 2) + 0xff900000)
8581 #define VIU_OSD2_TCOLOR_AG1 (0x1a38)
8582 #define P_VIU_OSD2_TCOLOR_AG1 (volatile uint32_t *)((0x1a38 << 2) + 0xff900000)
8583 #define VIU_OSD2_TCOLOR_AG2 (0x1a39)
8584 #define P_VIU_OSD2_TCOLOR_AG2 (volatile uint32_t *)((0x1a39 << 2) + 0xff900000)
8585 #define VIU_OSD2_TCOLOR_AG3 (0x1a3a)
8586 #define P_VIU_OSD2_TCOLOR_AG3 (volatile uint32_t *)((0x1a3a << 2) + 0xff900000)
8587 // Bit 31:24 Reserved
8588 // Bit 23:16 RW, tbl_addr
8589 // Bit 15 RW, little_endian: 0=big endian, 1=little endian
8590 // Bit 14 RW, rpt_y
8591 // Bit 13:12 RW, interp_ctrl. 0x=No interpolation; 10=Interpolate with previous
8592 // pixel; 11=Interpolate with the average value
8593 // between previous and next pixel.
8594 // Bit 11: 8 RW, osd_blk_mode
8595 // Bit 7 RW, rgb_en
8596 // Bit 6 RW, tc_alpha_en
8597 // Bit 5: 2 RW, color_matrix
8598 // Bit 1 RW, interlace_en
8599 // Bit 0 RW, interlace_sel_odd
8600 #define VIU_OSD2_BLK0_CFG_W0 (0x1a3b)
8601 #define P_VIU_OSD2_BLK0_CFG_W0 (volatile uint32_t *)((0x1a3b << 2) + 0xff900000)
8602 #define VIU_OSD2_BLK1_CFG_W0 (0x1a3f)
8603 #define P_VIU_OSD2_BLK1_CFG_W0 (volatile uint32_t *)((0x1a3f << 2) + 0xff900000)
8604 #define VIU_OSD2_BLK2_CFG_W0 (0x1a43)
8605 #define P_VIU_OSD2_BLK2_CFG_W0 (volatile uint32_t *)((0x1a43 << 2) + 0xff900000)
8606 #define VIU_OSD2_BLK3_CFG_W0 (0x1a47)
8607 #define P_VIU_OSD2_BLK3_CFG_W0 (volatile uint32_t *)((0x1a47 << 2) + 0xff900000)
8608 // Bit 31:29 Reserved
8609 // Bit 28:16 RW, x_end
8610 // Bit 15:13 Reserved
8611 // Bit 12: 0 RW, x_start
8612 #define VIU_OSD2_BLK0_CFG_W1 (0x1a3c)
8613 #define P_VIU_OSD2_BLK0_CFG_W1 (volatile uint32_t *)((0x1a3c << 2) + 0xff900000)
8614 #define VIU_OSD2_BLK1_CFG_W1 (0x1a40)
8615 #define P_VIU_OSD2_BLK1_CFG_W1 (volatile uint32_t *)((0x1a40 << 2) + 0xff900000)
8616 #define VIU_OSD2_BLK2_CFG_W1 (0x1a44)
8617 #define P_VIU_OSD2_BLK2_CFG_W1 (volatile uint32_t *)((0x1a44 << 2) + 0xff900000)
8618 #define VIU_OSD2_BLK3_CFG_W1 (0x1a48)
8619 #define P_VIU_OSD2_BLK3_CFG_W1 (volatile uint32_t *)((0x1a48 << 2) + 0xff900000)
8620 // Bit 31:29 Reserved
8621 // Bit 28:16 RW, y_end
8622 // Bit 15:13 Reserved
8623 // Bit 12: 0 RW, y_start
8624 #define VIU_OSD2_BLK0_CFG_W2 (0x1a3d)
8625 #define P_VIU_OSD2_BLK0_CFG_W2 (volatile uint32_t *)((0x1a3d << 2) + 0xff900000)
8626 #define VIU_OSD2_BLK1_CFG_W2 (0x1a41)
8627 #define P_VIU_OSD2_BLK1_CFG_W2 (volatile uint32_t *)((0x1a41 << 2) + 0xff900000)
8628 #define VIU_OSD2_BLK2_CFG_W2 (0x1a45)
8629 #define P_VIU_OSD2_BLK2_CFG_W2 (volatile uint32_t *)((0x1a45 << 2) + 0xff900000)
8630 #define VIU_OSD2_BLK3_CFG_W2 (0x1a49)
8631 #define P_VIU_OSD2_BLK3_CFG_W2 (volatile uint32_t *)((0x1a49 << 2) + 0xff900000)
8632 // Bit 31:28 Reserved
8633 // Bit 27:16 RW, h_end
8634 // Bit 15:12 Reserved
8635 // Bit 11: 0 RW, h_start
8636 #define VIU_OSD2_BLK0_CFG_W3 (0x1a3e)
8637 #define P_VIU_OSD2_BLK0_CFG_W3 (volatile uint32_t *)((0x1a3e << 2) + 0xff900000)
8638 #define VIU_OSD2_BLK1_CFG_W3 (0x1a42)
8639 #define P_VIU_OSD2_BLK1_CFG_W3 (volatile uint32_t *)((0x1a42 << 2) + 0xff900000)
8640 #define VIU_OSD2_BLK2_CFG_W3 (0x1a46)
8641 #define P_VIU_OSD2_BLK2_CFG_W3 (volatile uint32_t *)((0x1a46 << 2) + 0xff900000)
8642 #define VIU_OSD2_BLK3_CFG_W3 (0x1a4a)
8643 #define P_VIU_OSD2_BLK3_CFG_W3 (volatile uint32_t *)((0x1a4a << 2) + 0xff900000)
8644 // Bit 31:28 Reserved
8645 // Bit 27:16 RW, v_end
8646 // Bit 15:12 Reserved
8647 // Bit 11: 0 RW, v_start
8648 #define VIU_OSD2_BLK0_CFG_W4 (0x1a64)
8649 #define P_VIU_OSD2_BLK0_CFG_W4 (volatile uint32_t *)((0x1a64 << 2) + 0xff900000)
8650 #define VIU_OSD2_BLK1_CFG_W4 (0x1a65)
8651 #define P_VIU_OSD2_BLK1_CFG_W4 (volatile uint32_t *)((0x1a65 << 2) + 0xff900000)
8652 #define VIU_OSD2_BLK2_CFG_W4 (0x1a66)
8653 #define P_VIU_OSD2_BLK2_CFG_W4 (volatile uint32_t *)((0x1a66 << 2) + 0xff900000)
8654 #define VIU_OSD2_BLK3_CFG_W4 (0x1a67)
8655 #define P_VIU_OSD2_BLK3_CFG_W4 (volatile uint32_t *)((0x1a67 << 2) + 0xff900000)
8656 // Bit 31 RW, burst_len_sel[2] of [2:0]
8657 // Bit 30 RW, byte_swap: In addition to endian control, further define
8658 // whether to swap upper and lower byte within a 16-bit mem word.
8659 // 0=No swap; 1=Swap data[15:0] to be {data[7:0], data[15:8]}
8660 // Bit 29 RW, div_swap : swap the 2 64bits words in 128 bit word
8661 // Bit 28:24 RW, fifo_lim : when osd fifo is small than the fifo_lim*16, closed the rq port of osd_rd_mif
8662 // Bit 23:22 RW, fifo_ctrl: 00 : for 1 word in 1 burst , 01 : for 2words in 1burst, 10: for 4words in 1burst, 11: reserved
8663 // Bit 21:20 R, fifo_st. 0=IDLE, 1=FILL, 2=ABORT
8664 // Bit 19 R, fifo_overflow
8665 //
8666 // Bit 18:12 RW, fifo_depth_val, max value=64: set actual fifo depth to fifo_depth_val*8.
8667 // Bit 11:10 RW, burst_len_sel[1:0] of [2:0]. 0=24(default), 1=32, 2=48, 3=64, 4=96, 5=128.
8668 // Bit 9: 5 RW, hold_fifo_lines[4:0]
8669 // Bit 4 RW, clear_err: one pulse to clear fifo_overflow
8670 // Bit 3 RW, fifo_sync_rst
8671 // Bit 2: 1 RW, endian
8672 // Bit 0 RW, urgent
8673 #define VIU_OSD2_FIFO_CTRL_STAT (0x1a4b)
8674 #define P_VIU_OSD2_FIFO_CTRL_STAT (volatile uint32_t *)((0x1a4b << 2) + 0xff900000)
8675 // Bit 31:24 R, Y or R
8676 // Bit 23:16 R, Cb or G
8677 // Bit 15: 8 R, Cr or B
8678 // Bit 7: 0 R, Output Alpha[8:1]
8679 #define VIU_OSD2_TEST_RDDATA (0x1a4c)
8680 #define P_VIU_OSD2_TEST_RDDATA (volatile uint32_t *)((0x1a4c << 2) + 0xff900000)
8681 // Bit 15 RW, prot_en: 1=Borrow PROT's FIFO storage, either for rotate or non-rotate.
8682 // Bit 12: 0 RW, effective FIFO size when prot_en=1.
8683 #define VIU_OSD2_PROT_CTRL (0x1a4e)
8684 #define P_VIU_OSD2_PROT_CTRL (volatile uint32_t *)((0x1a4e << 2) + 0xff900000)
8685 //------------------------------------------------------------------------------
8686 // VD1 path
8687 //------------------------------------------------------------------------------
8688 #define VD1_IF0_GEN_REG (0x1a50)
8689 #define P_VD1_IF0_GEN_REG (volatile uint32_t *)((0x1a50 << 2) + 0xff900000)
8690 #define VD1_IF0_CANVAS0 (0x1a51)
8691 #define P_VD1_IF0_CANVAS0 (volatile uint32_t *)((0x1a51 << 2) + 0xff900000)
8692 #define VD1_IF0_CANVAS1 (0x1a52)
8693 #define P_VD1_IF0_CANVAS1 (volatile uint32_t *)((0x1a52 << 2) + 0xff900000)
8694 #define VD1_IF0_LUMA_X0 (0x1a53)
8695 #define P_VD1_IF0_LUMA_X0 (volatile uint32_t *)((0x1a53 << 2) + 0xff900000)
8696 #define VD1_IF0_LUMA_Y0 (0x1a54)
8697 #define P_VD1_IF0_LUMA_Y0 (volatile uint32_t *)((0x1a54 << 2) + 0xff900000)
8698 #define VD1_IF0_CHROMA_X0 (0x1a55)
8699 #define P_VD1_IF0_CHROMA_X0 (volatile uint32_t *)((0x1a55 << 2) + 0xff900000)
8700 #define VD1_IF0_CHROMA_Y0 (0x1a56)
8701 #define P_VD1_IF0_CHROMA_Y0 (volatile uint32_t *)((0x1a56 << 2) + 0xff900000)
8702 #define VD1_IF0_LUMA_X1 (0x1a57)
8703 #define P_VD1_IF0_LUMA_X1 (volatile uint32_t *)((0x1a57 << 2) + 0xff900000)
8704 #define VD1_IF0_LUMA_Y1 (0x1a58)
8705 #define P_VD1_IF0_LUMA_Y1 (volatile uint32_t *)((0x1a58 << 2) + 0xff900000)
8706 #define VD1_IF0_CHROMA_X1 (0x1a59)
8707 #define P_VD1_IF0_CHROMA_X1 (volatile uint32_t *)((0x1a59 << 2) + 0xff900000)
8708 #define VD1_IF0_CHROMA_Y1 (0x1a5a)
8709 #define P_VD1_IF0_CHROMA_Y1 (volatile uint32_t *)((0x1a5a << 2) + 0xff900000)
8710 #define VD1_IF0_RPT_LOOP (0x1a5b)
8711 #define P_VD1_IF0_RPT_LOOP (volatile uint32_t *)((0x1a5b << 2) + 0xff900000)
8712 #define VD1_IF0_LUMA0_RPT_PAT (0x1a5c)
8713 #define P_VD1_IF0_LUMA0_RPT_PAT (volatile uint32_t *)((0x1a5c << 2) + 0xff900000)
8714 #define VD1_IF0_CHROMA0_RPT_PAT (0x1a5d)
8715 #define P_VD1_IF0_CHROMA0_RPT_PAT (volatile uint32_t *)((0x1a5d << 2) + 0xff900000)
8716 #define VD1_IF0_LUMA1_RPT_PAT (0x1a5e)
8717 #define P_VD1_IF0_LUMA1_RPT_PAT (volatile uint32_t *)((0x1a5e << 2) + 0xff900000)
8718 #define VD1_IF0_CHROMA1_RPT_PAT (0x1a5f)
8719 #define P_VD1_IF0_CHROMA1_RPT_PAT (volatile uint32_t *)((0x1a5f << 2) + 0xff900000)
8720 #define VD1_IF0_LUMA_PSEL (0x1a60)
8721 #define P_VD1_IF0_LUMA_PSEL (volatile uint32_t *)((0x1a60 << 2) + 0xff900000)
8722 #define VD1_IF0_CHROMA_PSEL (0x1a61)
8723 #define P_VD1_IF0_CHROMA_PSEL (volatile uint32_t *)((0x1a61 << 2) + 0xff900000)
8724 #define VD1_IF0_DUMMY_PIXEL (0x1a62)
8725 #define P_VD1_IF0_DUMMY_PIXEL (volatile uint32_t *)((0x1a62 << 2) + 0xff900000)
8726 #define VD1_IF0_LUMA_FIFO_SIZE (0x1a63)
8727 #define P_VD1_IF0_LUMA_FIFO_SIZE (volatile uint32_t *)((0x1a63 << 2) + 0xff900000)
8728 #define VD1_IF0_RANGE_MAP_Y (0x1a6a)
8729 #define P_VD1_IF0_RANGE_MAP_Y (volatile uint32_t *)((0x1a6a << 2) + 0xff900000)
8730 #define VD1_IF0_RANGE_MAP_CB (0x1a6b)
8731 #define P_VD1_IF0_RANGE_MAP_CB (volatile uint32_t *)((0x1a6b << 2) + 0xff900000)
8732 #define VD1_IF0_RANGE_MAP_CR (0x1a6c)
8733 #define P_VD1_IF0_RANGE_MAP_CR (volatile uint32_t *)((0x1a6c << 2) + 0xff900000)
8734 #define VD1_IF0_GEN_REG2 (0x1a6d)
8735 #define P_VD1_IF0_GEN_REG2 (volatile uint32_t *)((0x1a6d << 2) + 0xff900000)
8736 #define VD1_IF0_PROT_CNTL (0x1a6e)
8737 #define P_VD1_IF0_PROT_CNTL (volatile uint32_t *)((0x1a6e << 2) + 0xff900000)
8738 #define VD1_IF0_URGENT_CTRL (0x1a6f)
8739 #define P_VD1_IF0_URGENT_CTRL (volatile uint32_t *)((0x1a6f << 2) + 0xff900000)
8740 //Bit 31 it true, disable clock, otherwise enable clock
8741 //Bit 30 soft rst bit
8742 //Bit 28 if true, horizontal formatter use repeating to generete pixel, otherwise use bilinear interpolation
8743 //Bit 27:24 horizontal formatter initial phase
8744 //Bit 23 horizontal formatter repeat pixel 0 enable
8745 //Bit 22:21 horizontal Y/C ratio, 00: 1:1, 01: 2:1, 10: 4:1
8746 //Bit 20 horizontal formatter enable
8747 //Bit 19 if true, always use phase0 while vertical formater, meaning always
8748 // repeat data, no interpolation
8749 //Bit 18 if true, disable vertical formatter chroma repeat last line
8750 //Bit 17 veritcal formatter dont need repeat line on phase0, 1: enable, 0: disable
8751 //Bit 16 veritcal formatter repeat line 0 enable
8752 //Bit 15:12 vertical formatter skip line num at the beginning
8753 //Bit 11:8 vertical formatter initial phase
8754 //Bit 7:1 vertical formatter phase step (3.4)
8755 //Bit 0 vertical formatter enable
8756 #define VIU_VD1_FMT_CTRL (0x1a68)
8757 #define P_VIU_VD1_FMT_CTRL (volatile uint32_t *)((0x1a68 << 2) + 0xff900000)
8758 //Bit 27:16 horizontal formatter width
8759 //Bit 11:0 vertical formatter width
8760 #define VIU_VD1_FMT_W (0x1a69)
8761 #define P_VIU_VD1_FMT_W (volatile uint32_t *)((0x1a69 << 2) + 0xff900000)
8762 //------------------------------------------------------------------------------
8763 // VD2 path
8764 //------------------------------------------------------------------------------
8765 #define VD2_IF0_GEN_REG (0x1a70)
8766 #define P_VD2_IF0_GEN_REG (volatile uint32_t *)((0x1a70 << 2) + 0xff900000)
8767 #define VD2_IF0_CANVAS0 (0x1a71)
8768 #define P_VD2_IF0_CANVAS0 (volatile uint32_t *)((0x1a71 << 2) + 0xff900000)
8769 #define VD2_IF0_CANVAS1 (0x1a72)
8770 #define P_VD2_IF0_CANVAS1 (volatile uint32_t *)((0x1a72 << 2) + 0xff900000)
8771 #define VD2_IF0_LUMA_X0 (0x1a73)
8772 #define P_VD2_IF0_LUMA_X0 (volatile uint32_t *)((0x1a73 << 2) + 0xff900000)
8773 #define VD2_IF0_LUMA_Y0 (0x1a74)
8774 #define P_VD2_IF0_LUMA_Y0 (volatile uint32_t *)((0x1a74 << 2) + 0xff900000)
8775 #define VD2_IF0_CHROMA_X0 (0x1a75)
8776 #define P_VD2_IF0_CHROMA_X0 (volatile uint32_t *)((0x1a75 << 2) + 0xff900000)
8777 #define VD2_IF0_CHROMA_Y0 (0x1a76)
8778 #define P_VD2_IF0_CHROMA_Y0 (volatile uint32_t *)((0x1a76 << 2) + 0xff900000)
8779 #define VD2_IF0_LUMA_X1 (0x1a77)
8780 #define P_VD2_IF0_LUMA_X1 (volatile uint32_t *)((0x1a77 << 2) + 0xff900000)
8781 #define VD2_IF0_LUMA_Y1 (0x1a78)
8782 #define P_VD2_IF0_LUMA_Y1 (volatile uint32_t *)((0x1a78 << 2) + 0xff900000)
8783 #define VD2_IF0_CHROMA_X1 (0x1a79)
8784 #define P_VD2_IF0_CHROMA_X1 (volatile uint32_t *)((0x1a79 << 2) + 0xff900000)
8785 #define VD2_IF0_CHROMA_Y1 (0x1a7a)
8786 #define P_VD2_IF0_CHROMA_Y1 (volatile uint32_t *)((0x1a7a << 2) + 0xff900000)
8787 #define VD2_IF0_RPT_LOOP (0x1a7b)
8788 #define P_VD2_IF0_RPT_LOOP (volatile uint32_t *)((0x1a7b << 2) + 0xff900000)
8789 #define VD2_IF0_LUMA0_RPT_PAT (0x1a7c)
8790 #define P_VD2_IF0_LUMA0_RPT_PAT (volatile uint32_t *)((0x1a7c << 2) + 0xff900000)
8791 #define VD2_IF0_CHROMA0_RPT_PAT (0x1a7d)
8792 #define P_VD2_IF0_CHROMA0_RPT_PAT (volatile uint32_t *)((0x1a7d << 2) + 0xff900000)
8793 #define VD2_IF0_LUMA1_RPT_PAT (0x1a7e)
8794 #define P_VD2_IF0_LUMA1_RPT_PAT (volatile uint32_t *)((0x1a7e << 2) + 0xff900000)
8795 #define VD2_IF0_CHROMA1_RPT_PAT (0x1a7f)
8796 #define P_VD2_IF0_CHROMA1_RPT_PAT (volatile uint32_t *)((0x1a7f << 2) + 0xff900000)
8797 #define VD2_IF0_LUMA_PSEL (0x1a80)
8798 #define P_VD2_IF0_LUMA_PSEL (volatile uint32_t *)((0x1a80 << 2) + 0xff900000)
8799 #define VD2_IF0_CHROMA_PSEL (0x1a81)
8800 #define P_VD2_IF0_CHROMA_PSEL (volatile uint32_t *)((0x1a81 << 2) + 0xff900000)
8801 #define VD2_IF0_DUMMY_PIXEL (0x1a82)
8802 #define P_VD2_IF0_DUMMY_PIXEL (volatile uint32_t *)((0x1a82 << 2) + 0xff900000)
8803 #define VD2_IF0_LUMA_FIFO_SIZE (0x1a83)
8804 #define P_VD2_IF0_LUMA_FIFO_SIZE (volatile uint32_t *)((0x1a83 << 2) + 0xff900000)
8805 #define VD2_IF0_RANGE_MAP_Y (0x1a8a)
8806 #define P_VD2_IF0_RANGE_MAP_Y (volatile uint32_t *)((0x1a8a << 2) + 0xff900000)
8807 #define VD2_IF0_RANGE_MAP_CB (0x1a8b)
8808 #define P_VD2_IF0_RANGE_MAP_CB (volatile uint32_t *)((0x1a8b << 2) + 0xff900000)
8809 #define VD2_IF0_RANGE_MAP_CR (0x1a8c)
8810 #define P_VD2_IF0_RANGE_MAP_CR (volatile uint32_t *)((0x1a8c << 2) + 0xff900000)
8811 #define VD2_IF0_GEN_REG2 (0x1a8d)
8812 #define P_VD2_IF0_GEN_REG2 (volatile uint32_t *)((0x1a8d << 2) + 0xff900000)
8813 #define VD2_IF0_PROT_CNTL (0x1a8e)
8814 #define P_VD2_IF0_PROT_CNTL (volatile uint32_t *)((0x1a8e << 2) + 0xff900000)
8815 #define VD2_IF0_URGENT_CTRL (0x1a8f)
8816 #define P_VD2_IF0_URGENT_CTRL (volatile uint32_t *)((0x1a8f << 2) + 0xff900000)
8817 //Bit 31 it true, disable clock, otherwise enable clock
8818 //Bit 30 soft rst bit
8819 //Bit 28 if true, horizontal formatter use repeating to generete pixel, otherwise use bilinear interpolation
8820 //Bit 27:24 horizontal formatter initial phase
8821 //Bit 23 horizontal formatter repeat pixel 0 enable
8822 //Bit 22:21 horizontal Y/C ratio, 00: 1:1, 01: 2:1, 10: 4:1
8823 //Bit 20 horizontal formatter enable
8824 //Bit 17 veritcal formatter dont need repeat line on phase0, 1: enable, 0: disable
8825 //Bit 16 veritcal formatter repeat line 0 enable
8826 //Bit 15:12 vertical formatter skip line num at the beginning
8827 //Bit 11:8 vertical formatter initial phase
8828 //Bit 7:1 vertical formatter phase step (3.4)
8829 //Bit 0 vertical formatter enable
8830 #define VIU_VD2_FMT_CTRL (0x1a88)
8831 #define P_VIU_VD2_FMT_CTRL (volatile uint32_t *)((0x1a88 << 2) + 0xff900000)
8832 //Bit 27:16 horizontal formatter width
8833 //Bit 11:0 vertical formatter width
8834 #define VIU_VD2_FMT_W (0x1a89)
8835 #define P_VIU_VD2_FMT_W (volatile uint32_t *)((0x1a89 << 2) + 0xff900000)
8836 // //todo add comment
8837 #define LDIM_STTS_GCLK_CTRL0 (0x1ac0)
8838 #define P_LDIM_STTS_GCLK_CTRL0 (volatile uint32_t *)((0x1ac0 << 2) + 0xff900000)
8839 #define LDIM_STTS_CTRL0 (0x1ac1)
8840 #define P_LDIM_STTS_CTRL0 (volatile uint32_t *)((0x1ac1 << 2) + 0xff900000)
8841 #define LDIM_STTS_WIDTHM1_HEIGHTM1 (0x1ac2)
8842 #define P_LDIM_STTS_WIDTHM1_HEIGHTM1 (volatile uint32_t *)((0x1ac2 << 2) + 0xff900000)
8843 #define LDIM_STTS_MATRIX_COEF00_01 (0x1ac3)
8844 #define P_LDIM_STTS_MATRIX_COEF00_01 (volatile uint32_t *)((0x1ac3 << 2) + 0xff900000)
8845 #define LDIM_STTS_MATRIX_COEF02_10 (0x1ac4)
8846 #define P_LDIM_STTS_MATRIX_COEF02_10 (volatile uint32_t *)((0x1ac4 << 2) + 0xff900000)
8847 #define LDIM_STTS_MATRIX_COEF11_12 (0x1ac5)
8848 #define P_LDIM_STTS_MATRIX_COEF11_12 (volatile uint32_t *)((0x1ac5 << 2) + 0xff900000)
8849 #define LDIM_STTS_MATRIX_COEF20_21 (0x1ac6)
8850 #define P_LDIM_STTS_MATRIX_COEF20_21 (volatile uint32_t *)((0x1ac6 << 2) + 0xff900000)
8851 #define LDIM_STTS_MATRIX_COEF22 (0x1ac7)
8852 #define P_LDIM_STTS_MATRIX_COEF22 (volatile uint32_t *)((0x1ac7 << 2) + 0xff900000)
8853 #define LDIM_STTS_MATRIX_OFFSET0_1 (0x1ac8)
8854 #define P_LDIM_STTS_MATRIX_OFFSET0_1 (volatile uint32_t *)((0x1ac8 << 2) + 0xff900000)
8855 #define LDIM_STTS_MATRIX_OFFSET2 (0x1ac9)
8856 #define P_LDIM_STTS_MATRIX_OFFSET2 (volatile uint32_t *)((0x1ac9 << 2) + 0xff900000)
8857 #define LDIM_STTS_MATRIX_PRE_OFFSET0_1 (0x1aca)
8858 #define P_LDIM_STTS_MATRIX_PRE_OFFSET0_1 (volatile uint32_t *)((0x1aca << 2) + 0xff900000)
8859 #define LDIM_STTS_MATRIX_PRE_OFFSET2 (0x1acb)
8860 #define P_LDIM_STTS_MATRIX_PRE_OFFSET2 (volatile uint32_t *)((0x1acb << 2) + 0xff900000)
8861 #define LDIM_STTS_MATRIX_HL_COLOR (0x1acc)
8862 #define P_LDIM_STTS_MATRIX_HL_COLOR (volatile uint32_t *)((0x1acc << 2) + 0xff900000)
8863 #define LDIM_STTS_MATRIX_PROBE_POS (0x1acd)
8864 #define P_LDIM_STTS_MATRIX_PROBE_POS (volatile uint32_t *)((0x1acd << 2) + 0xff900000)
8865 //
8866 // //read only
8867 #define LDIM_STTS_MATRIX_PROBE_COLOR (0x1ace)
8868 #define P_LDIM_STTS_MATRIX_PROBE_COLOR (volatile uint32_t *)((0x1ace << 2) + 0xff900000)
8869 //
8870 // //Bit 31, local dimming statistic enable
8871 // //Bit 29, 1: output region histogram 16bit 0:output region histogram 20bit
8872 // //Bit 28, eol enable
8873 // //Bit 27:25, vertical line overlap number for max finding
8874 // //Bit 24:22, horizontal pixel overlap number, 0: 17 pix, 1: 9 pix, 2: 5 pix, 3: 3 pix, 4: 0 pix
8875 // //Bit 20, 1,2,1 low pass filter enable before max/hist statistic
8876 // //Bit 19:16, region H/V position index, refer to VDIN_LDIM_STTS_HIST_SET_REGION
8877 // //Bit 15:14, 1: region read index auto increase per block read finished to VDIN_LDIM_STTS_HIST_READ_REGION
8878 // // 2: region read index auto increase per read finished to VDIN_LDIM_STTS_HIST_READ_REGION
8879 // // 0/3: disable read index self increase
8880 // //Bit 13:8, region read sub index, which mux the hist & max-finding result to cbus port, refer to LDIM_STTS_HIST_READ_REGION
8881 // //Bit 6:0, region read index
8882 #define LDIM_STTS_HIST_REGION_IDX (0x1ad0)
8883 #define P_LDIM_STTS_HIST_REGION_IDX (volatile uint32_t *)((0x1ad0 << 2) + 0xff900000)
8884 //Bit 28:0, if VDIN_LDIM_STTS_HIST_REGION_IDX[19:16] == 5'h0: read/write hvstart0
8885 // if VDIN_LDIM_STTS_HIST_REGION_IDX[19:16] == 5'h1: read/write hend01
8886 // if VDIN_LDIM_STTS_HIST_REGION_IDX[19:16] == 5'h2: read/write vend01
8887 // if VDIN_LDIM_STTS_HIST_REGION_IDX[19:16] == 5'h3: read/write hend23
8888 // if VDIN_LDIM_STTS_HIST_REGION_IDX[19:16] == 5'h4: read/write vend23
8889 // if VDIN_LDIM_STTS_HIST_REGION_IDX[19:16] == 5'h5: read/write hend45
8890 // if VDIN_LDIM_STTS_HIST_REGION_IDX[19:16] == 5'h6: read/write vend45
8891 // if VDIN_LDIM_STTS_HIST_REGION_IDX[19:16] == 5'd7: read/write hend67
8892 // if VDIN_LDIM_STTS_HIST_REGION_IDX[19:16] == 5'h8: read/write vend67
8893 // if VDIN_LDIM_STTS_HIST_REGION_IDX[19:16] == 5'h9: read/write hend89
8894 // if VDIN_LDIM_STTS_HIST_REGION_IDX[19:16] == 5'ha: read/write vend89
8895 // //hvstart0, Bit 28:16 row0 vstart, Bit 12:0 col0 hstart
8896 // //hend01, Bit 28:16 col1 hend, Bit 12:0 col0 hend
8897 // //vend01, Bit 28:16 row1 vend, Bit 12:0 row0 vend
8898 // //hend23, Bit 28:16 col3 hend, Bit 12:0 col2 hend
8899 // //vend23, Bit 28:16 row3 vend, Bit 12:0 row2 vend
8900 // //hend45, Bit 28:16 col5 hend, Bit 12:0 col4 hend
8901 // //vend45, Bit 28:16 row5 vend, Bit 12:0 row4 vend
8902 // //hend67, Bit 28:16 col7 hend, Bit 12:0 col6 hend
8903 // //vend67, Bit 28:16 row7 vend, Bit 12:0 row6 vend
8904 // //hend89, Bit 28:16 col9 hend, Bit 12:0 col8 hend
8905 // //vend89, Bit 28:16 row9 vend, Bit 12:0 row8 vend
8906 #define LDIM_STTS_HIST_SET_REGION (0x1ad1)
8907 #define P_LDIM_STTS_HIST_SET_REGION (volatile uint32_t *)((0x1ad1 << 2) + 0xff900000)
8908 //
8909 // //if LDIM_STTS_HIST_REGION_IDX[29] == 0, that is output hist with 20bit data.
8910 // //if LDIM_STTS_HIST_REGION_IDX[21] == 0, that is output 16hist bins in comp 0.
8911 // //output sequence as rd_sub_idx from 0~47: {max_comp2, comp0_hist0}, {max_comp1, comp0_hist1}, {max_comp0, comp0_hist2},
8912 // // comp0_hist3 ... comp2_hist16
8913 // //if LDIM_STTS_HIST_REGION_IDX[29] == 1, that is output hist with 16bit data.
8914 // //if LDIM_STTS_HIST_REGION_IDX[21] == 0, that is output 16hist bins in comp 0.
8915 // //output sequence as rd_sub_idx from 0~47: {max_comp2, max_comp1, max_comp0}, comp0_hist0, comp0_hist1, comp0_hist2
8916 // // comp0_hist3 ... comp2_hist16
8917 // //if LDIM_STTS_HIST_REGION_IDX[29] == 0, that is output hist with 20bit data.
8918 // //if LDIM_STTS_HIST_REGION_IDX[21] == 1, that is output 32hist bins in comp 0.
8919 // //output sequence as rd_sub_idx from 0~47: {max_comp2, max_comp1, max_comp0}, comp0_hist0, comp0_hist1, comp0_hist2
8920 // // comp0_hist3 ...comp0_hist31 ... comp1_hist16
8921 //
8922 #define LDIM_STTS_HIST_READ_REGION (0x1ad2)
8923 #define P_LDIM_STTS_HIST_READ_REGION (volatile uint32_t *)((0x1ad2 << 2) + 0xff900000)
8924 #define LDIM_STTS_HIST_START_RD_REGION (0x1ad3)
8925 #define P_LDIM_STTS_HIST_START_RD_REGION (volatile uint32_t *)((0x1ad3 << 2) + 0xff900000)
8926 // //bit15, auto enable; bit14, canvas write mode ;7:4, high threshold ;3:0 , low threshold for di if1 chroma path
8927 // //bit31, auto enable; bit30, canvas write mode ;23:20, high threshold ;19:16 , low threshold for di if1 luma path
8928 // `define DI_IF1_URGENT_CTRL 8'ha3
8929 // //bit15, auto enable; bit14, canvas write mode ;7:4, high threshold ;3:0 , low threshold for di inp chroma path
8930 // //bit31, auto enable; bit30, canvas write mode ;23:20, high threshold ;19:16 , low threshold for di inp luma path
8931 // `define DI_INP_URGENT_CTRL 8'ha4
8932 // //bit15, auto enable; bit14, canvas write mode ;7:4, high threshold ;3:0 , low threshold for di mem chroma path
8933 // //bit31, auto enable; bit30, canvas write mode ;23:20, high threshold ;19:16 , low threshold for di mem luma path
8934 // `define DI_MEM_URGENT_CTRL 8'ha5
8935 // //bit15, auto enable; bit14, canvas write mode ;7:4, high threshold ;3:0 , low threshold for di chan2 chroma path
8936 // //bit31, auto enable; bit30, canvas write mode ;23:20, high threshold ;19:16 , low threshold for di chan2 luma path
8937 // `define DI_CHAN2_URGENT_CTRL 8'ha6
8938 #define VD1_IF0_GEN_REG3 (0x1aa7)
8939 #define P_VD1_IF0_GEN_REG3 (volatile uint32_t *)((0x1aa7 << 2) + 0xff900000)
8940 //bit 31:1, reversed
8941 //bit 0, cntl_64bit_rev
8942 #define VD2_IF0_GEN_REG3 (0x1aa8)
8943 #define P_VD2_IF0_GEN_REG3 (volatile uint32_t *)((0x1aa8 << 2) + 0xff900000)
8944 //bit 31:1, reversed
8945 //bit 0, cntl_64bit_rev
8946 #define OSD_BLENDO_H_START_END (0x1aa9)
8947 #define P_OSD_BLENDO_H_START_END (volatile uint32_t *)((0x1aa9 << 2) + 0xff900000)
8948 //OSD blending output horizontal start and end
8949 //Bit 28:16 start
8950 //Bit 12:0 end
8951 #define OSD_BLENDO_V_START_END (0x1aaa)
8952 #define P_OSD_BLENDO_V_START_END (volatile uint32_t *)((0x1aaa << 2) + 0xff900000)
8953 //OSD blending output vertical start and end
8954 //Bit 28:16 start
8955 //Bit 12:0 end
8956 #define OSD_BLEND_GEN_CTRL0 (0x1aab)
8957 #define P_OSD_BLEND_GEN_CTRL0 (volatile uint32_t *)((0x1aab << 2) + 0xff900000)
8958 //Bit 31:23 const_out_alpha
8959 //Bit 22:14 const_op_alpha
8960 //Bit 13 if true, OSD2 foreground otherwise OSD1 foreground
8961 //Bit 12 OSD BLENDing enable
8962 //Bit 9:8 alpha_op_sel 00: output alpha use osd1_alpha, 01: use osd2_alpha, else use const_out_alpha
8963 //Bit 5:4 color_op_sel 00: use osd1_alpha, 01: use osd2_alpha, else use const_op_alpha
8964 //Bit 1 OSD2 enable
8965 //Bit 0 OSD1 enable
8966 #define OSD_BLEND_GEN_CTRL1 (0x1aac)
8967 #define P_OSD_BLEND_GEN_CTRL1 (volatile uint32_t *)((0x1aac << 2) + 0xff900000)
8968 //Bit 31 osd1_alpha_premult, if true, osd1 alpha is premultipiled
8969 //Bit 30 osd2_alpha_premult, if true, osd2 alpha is premultipiled
8970 //Bit 23:16 osd blending hold lines
8971 //Bit 13:0 osd blending h_size
8972 #define OSD_BLEND_DUMMY_DATA (0x1aad)
8973 #define P_OSD_BLEND_DUMMY_DATA (volatile uint32_t *)((0x1aad << 2) + 0xff900000)
8974 //Bit 29:20 Y/R
8975 //Bit 19:10 CB/G
8976 //Bit 9:0 Cr/B
8977 #define OSD_BLEND_CURRENT_XY (0x1aae)
8978 #define P_OSD_BLEND_CURRENT_XY (volatile uint32_t *)((0x1aae << 2) + 0xff900000)
8979 //Bit 28:16 current_x
8980 //Bit 12:0 current_y
8981 //Bit 7, highlight_en
8982 //Bit 6 probe_post, if true, probe pixel data after matrix, otherwise probe pixel data before matrix
8983 //Bit 5:4 probe_sel, 00: select matrix 0, 01: select matrix 1, otherwise select nothing
8984 //Bit 3:2, matrix coef idx selection, 00: select mat0, 01: select mat1, otherwise slect nothing
8985 //Bit 1 mat1 conversion matrix enable
8986 //Bit 0 mat0 conversion matrix enable
8987 #define VIU_OSD2_MATRIX_CTRL (0x1ab0)
8988 #define P_VIU_OSD2_MATRIX_CTRL (volatile uint32_t *)((0x1ab0 << 2) + 0xff900000)
8989 //Bit 28:16 coef00
8990 //Bit 12:0 coef01
8991 #define VIU_OSD2_MATRIX_COEF00_01 (0x1ab1)
8992 #define P_VIU_OSD2_MATRIX_COEF00_01 (volatile uint32_t *)((0x1ab1 << 2) + 0xff900000)
8993 //Bit 28:16 coef02
8994 //Bit 12:0 coef10
8995 #define VIU_OSD2_MATRIX_COEF02_10 (0x1ab2)
8996 #define P_VIU_OSD2_MATRIX_COEF02_10 (volatile uint32_t *)((0x1ab2 << 2) + 0xff900000)
8997 //Bit 28:16 coef11
8998 //Bit 12:0 coef12
8999 #define VIU_OSD2_MATRIX_COEF11_12 (0x1ab3)
9000 #define P_VIU_OSD2_MATRIX_COEF11_12 (volatile uint32_t *)((0x1ab3 << 2) + 0xff900000)
9001 //Bit 28:16 coef20
9002 //Bit 12:0 coef21
9003 #define VIU_OSD2_MATRIX_COEF20_21 (0x1ab4)
9004 #define P_VIU_OSD2_MATRIX_COEF20_21 (volatile uint32_t *)((0x1ab4 << 2) + 0xff900000)
9005 #define VIU_OSD2_MATRIX_COEF22 (0x1ab5)
9006 #define P_VIU_OSD2_MATRIX_COEF22 (volatile uint32_t *)((0x1ab5 << 2) + 0xff900000)
9007 //Bit 26:16 offset0
9008 //Bit 10:0 offset1
9009 #define VIU_OSD2_MATRIX_OFFSET0_1 (0x1ab6)
9010 #define P_VIU_OSD2_MATRIX_OFFSET0_1 (volatile uint32_t *)((0x1ab6 << 2) + 0xff900000)
9011 //Bit 10:0 offset2
9012 #define VIU_OSD2_MATRIX_OFFSET2 (0x1ab7)
9013 #define P_VIU_OSD2_MATRIX_OFFSET2 (volatile uint32_t *)((0x1ab7 << 2) + 0xff900000)
9014 //Bit 26:16 pre_offset0
9015 //Bit 10:0 pre_offset1
9016 #define VIU_OSD2_MATRIX_PRE_OFFSET0_1 (0x1ab8)
9017 #define P_VIU_OSD2_MATRIX_PRE_OFFSET0_1 (volatile uint32_t *)((0x1ab8 << 2) + 0xff900000)
9018 //Bit 10:0 pre_offset2
9019 #define VIU_OSD2_MATRIX_PRE_OFFSET2 (0x1ab9)
9020 #define P_VIU_OSD2_MATRIX_PRE_OFFSET2 (volatile uint32_t *)((0x1ab9 << 2) + 0xff900000)
9021 //Read only
9022 //Bit 29:20 component 0
9023 //Bit 19:10 component 1
9024 //Bit 9:0 component 2
9025 #define VIU_OSD2_MATRIX_PROBE_COLOR (0x1aba)
9026 #define P_VIU_OSD2_MATRIX_PROBE_COLOR (volatile uint32_t *)((0x1aba << 2) + 0xff900000)
9027 //Bit 23:16 component 0
9028 //Bit 15:8 component 1
9029 //Bit 7:0 component 2
9030 #define VIU_OSD2_MATRIX_HL_COLOR (0x1abb)
9031 #define P_VIU_OSD2_MATRIX_HL_COLOR (volatile uint32_t *)((0x1abb << 2) + 0xff900000)
9032 //28:16 probe x, postion
9033 //12:0 probe y, position
9034 #define VIU_OSD2_MATRIX_PROBE_POS (0x1abc)
9035 #define P_VIU_OSD2_MATRIX_PROBE_POS (volatile uint32_t *)((0x1abc << 2) + 0xff900000)
9036 //the segment of afbc dec is 8'he0-8'hfe
9037 //`define AFBC_DEC_OFFSET 8'he0
9038 //
9039 // Reading file: afbc_dec_regs.h
9040 //
9041 // synopsys translate_off
9042 // synopsys translate_on
9043 ////===============================////
9044 //// reg
9045 ////===============================////
9046 #define AFBC_ENABLE (0x1ae0)
9047 #define P_AFBC_ENABLE (volatile uint32_t *)((0x1ae0 << 2) + 0xff900000)
9048 //Bit 31:1, reserved
9049 //Bit 8, dec_enable unsigned , default = 0
9050 //Bit 7:1, reserved
9051 //Bit 0, frm_start unsigned , default = 0
9052 #define AFBC_MODE (0x1ae1)
9053 #define P_AFBC_MODE (volatile uint32_t *)((0x1ae1 << 2) + 0xff900000)
9054 //Bit 31, soft_reset the use as go_field
9055 //Bit 30, reserved
9056 //Bit 29, ddr_sz_mode uns, default = 0 , 0: fixed block ddr size 1 : unfixed block ddr size;
9057 //Bit 28, blk_mem_mode uns, default = 0 , 0: fixed 16x128 size; 1 : fixed 12x128 size
9058 //Bit 27:26, rev_mode uns, default = 0 , reverse mode
9059 //Bit 25:24, mif_urgent uns, default = 3 , info mif and data mif urgent
9060 //Bit 22:16, hold_line_num
9061 //Bit 15:14, burst_len uns, default = 1, 0: burst1 1:burst2 2:burst4
9062 //Bit 13:8, compbits_yuv uns, default = 0 ,
9063 // bit 1:0,: y component bitwidth : 00-8bit 01-9bit 10-10bit
9064 // bit 3:2,: u component bitwidth : 00-8bit 01-9bit 10-10bit
9065 // bit 5:4,: v component bitwidth : 00-8bit 01-9bit 10-10bit
9066 //Bit 7:6, vert_skip_y uns, default = 0 , luma vert skip mode : 00-y0y1, 01-y0, 10-y1, 11-(y0+y1)/2
9067 //Bit 5:4, horz_skip_y uns, default = 0 , luma horz skip mode : 00-y0y1, 01-y0, 10-y1, 11-(y0+y1)/2
9068 //Bit 3:2, vert_skip_uv uns, default = 0 , chroma vert skip mode : 00-y0y1, 01-y0, 10-y1, 11-(y0+y1)/2
9069 //Bit 1:0, horz_skip_uv uns, default = 0 , chroma horz skip mode : 00-y0y1, 01-y0, 10-y1, 11-(y0+y1)/2
9070 #define AFBC_SIZE_IN (0x1ae2)
9071 #define P_AFBC_SIZE_IN (volatile uint32_t *)((0x1ae2 << 2) + 0xff900000)
9072 //Bit 31:29, reserved
9073 //Bit 28:16 hsize_in uns, default = 1920 , pic horz size in unit: pixel
9074 //Bit 15:13, reserved
9075 //Bit 12:0, vsize_in uns, default = 1080 , pic vert size in unit: pixel
9076 #define AFBC_DEC_DEF_COLOR (0x1ae3)
9077 #define P_AFBC_DEC_DEF_COLOR (volatile uint32_t *)((0x1ae3 << 2) + 0xff900000)
9078 //Bit 31:29, reserved
9079 //Bit 29:20, def_color_y uns, default = 0, afbc dec y default setting value
9080 //Bit 19:10, def_color_u uns, default = 0, afbc dec u default setting value
9081 //Bit 9: 0, def_color_v uns, default = 0, afbc dec v default setting value
9082 #define AFBC_CONV_CTRL (0x1ae4)
9083 #define P_AFBC_CONV_CTRL (volatile uint32_t *)((0x1ae4 << 2) + 0xff900000)
9084 //Bit 31:12, reserved
9085 //Bit 11: 0, conv_lbuf_len uns, default = 256, unit=16 pixel need to set = 2^n
9086 #define AFBC_LBUF_DEPTH (0x1ae5)
9087 #define P_AFBC_LBUF_DEPTH (volatile uint32_t *)((0x1ae5 << 2) + 0xff900000)
9088 //Bit 31:28, reserved
9089 //Bit 27:16, dec_lbuf_depth uns, default = 128; // unit= 8 pixel
9090 //Bit 15:12, reserved
9091 //Bit 11:0, mif_lbuf_depth uns, default = 128;
9092 #define AFBC_HEAD_BADDR (0x1ae6)
9093 #define P_AFBC_HEAD_BADDR (volatile uint32_t *)((0x1ae6 << 2) + 0xff900000)
9094 //Bit 31:0, mif_info_baddr uns, default = 32'h0;
9095 #define AFBC_BODY_BADDR (0x1ae7)
9096 #define P_AFBC_BODY_BADDR (volatile uint32_t *)((0x1ae7 << 2) + 0xff900000)
9097 //Bit 31:0, mif_data_baddr uns, default = 32'h0001_0000;
9098 #define AFBC_SIZE_OUT (0x1ae8)
9099 #define P_AFBC_SIZE_OUT (volatile uint32_t *)((0x1ae8 << 2) + 0xff900000)
9100 //Bit 31:29, reserved
9101 //Bit 28:16, hsize_out uns, default = 1920 ; // unit: 1 pixel
9102 //Bit 15:13, reserved
9103 //Bit 12:0, vsize_out uns, default = 1080 ; // unit: 1 pixel
9104 #define AFBC_OUT_YSCOPE (0x1ae9)
9105 #define P_AFBC_OUT_YSCOPE (volatile uint32_t *)((0x1ae9 << 2) + 0xff900000)
9106 //Bit 31:29, reserved
9107 //Bit 28:16, out_vert_bgn uns, default = 0 ; // unit: 1 pixel
9108 //Bit 15:13, reserved
9109 //Bit 12:0, out_vert_end uns, default = 1079 ; // unit: 1 pixel
9110 #define AFBC_STAT (0x1aea)
9111 #define P_AFBC_STAT (volatile uint32_t *)((0x1aea << 2) + 0xff900000)
9112 //Bit 31:1, reserved
9113 //Bit 0, frm_end_stat uns, frame end status
9114 #define AFBC_VD_CFMT_CTRL (0x1aeb)
9115 #define P_AFBC_VD_CFMT_CTRL (volatile uint32_t *)((0x1aeb << 2) + 0xff900000)
9116 //Bit 31 it true, disable clock, otherwise enable clock
9117 //Bit 30 soft rst bit
9118 //Bit 28 if true, horizontal formatter use repeating to generete pixel, otherwise use bilinear interpolation
9119 //Bit 27:24 horizontal formatter initial phase
9120 //Bit 23 horizontal formatter repeat pixel 0 enable
9121 //Bit 22:21 horizontal Y/C ratio, 00: 1:1, 01: 2:1, 10: 4:1
9122 //Bit 20 horizontal formatter enable
9123 //Bit 19 if true, always use phase0 while vertical formater, meaning always
9124 // repeat data, no interpolation
9125 //Bit 18 if true, disable vertical formatter chroma repeat last line
9126 //Bit 17 veritcal formatter dont need repeat line on phase0, 1: enable, 0: disable
9127 //Bit 16 veritcal formatter repeat line 0 enable
9128 //Bit 15:12 vertical formatter skip line num at the beginning
9129 //Bit 11:8 vertical formatter initial phase
9130 //Bit 7:1 vertical formatter phase step (3.4)
9131 //Bit 0 vertical formatter enable
9132 #define AFBC_VD_CFMT_W (0x1aec)
9133 #define P_AFBC_VD_CFMT_W (volatile uint32_t *)((0x1aec << 2) + 0xff900000)
9134 //Bit 27:16 horizontal formatter width
9135 //Bit 11:0 vertical formatter width
9136 #define AFBC_MIF_HOR_SCOPE (0x1aed)
9137 #define P_AFBC_MIF_HOR_SCOPE (volatile uint32_t *)((0x1aed << 2) + 0xff900000)
9138 //Bit 31:26, reserved
9139 //Bit 25:16, mif_blk_bgn_h uns, default = 0 ; // unit: 32 pixel/block hor
9140 //Bit 15:10, reserved
9141 //Bit 9: 0, mif_blk_end_h uns, default = 59 ; // unit: 32 pixel/block hor
9142 #define AFBC_MIF_VER_SCOPE (0x1aee)
9143 #define P_AFBC_MIF_VER_SCOPE (volatile uint32_t *)((0x1aee << 2) + 0xff900000)
9144 //Bit 31:28, reserved
9145 //Bit 27:16, mif_blk_bgn_v uns, default = 0 ; // unit: 32 pixel/block ver
9146 //Bit 15:12, reserved
9147 //Bit 11: 0, mif_blk_end_v uns, default = 269; // unit: 32 pixel/block ver
9148 #define AFBC_PIXEL_HOR_SCOPE (0x1aef)
9149 #define P_AFBC_PIXEL_HOR_SCOPE (volatile uint32_t *)((0x1aef << 2) + 0xff900000)
9150 //Bit 31:29, reserved
9151 //Bit 28:16, dec_pixel_bgn_h uns, default = 0 ; // unit: pixel
9152 //Bit 15:13, reserved
9153 //Bit 12: 0, dec_pixel_end_h uns, default = 1919 ; // unit: pixel
9154 #define AFBC_PIXEL_VER_SCOPE (0x1af0)
9155 #define P_AFBC_PIXEL_VER_SCOPE (volatile uint32_t *)((0x1af0 << 2) + 0xff900000)
9156 //Bit 31:29, reserved
9157 //Bit 28:16, dec_pixel_bgn_v uns, default = 0 ; // unit: pixel
9158 //Bit 15:13, reserved
9159 //Bit 12: 0, dec_pixel_end_v uns, default = 1079 ; // unit: pixel
9160 #define AFBC_VD_CFMT_H (0x1af1)
9161 #define P_AFBC_VD_CFMT_H (volatile uint32_t *)((0x1af1 << 2) + 0xff900000)
9162 //Bit 12:0 vertical formatter height
9163 // synopsys translate_off
9164 // synopsys translate_on
9165 //
9166 // Closing file: afbc_dec_regs.h
9167 //
9168 //
9169 // Closing file: vregs_clk2.h
9170 //
9171 //`define VENC_VCBUS_BASE 8'h1b
9172 //
9173 // Reading file: venc_regs.h
9174 //
9175 //===========================================================================
9176 // Video Interface Registers 0xa00 - 0xbff
9177 //===========================================================================
9178 // -----------------------------------------------
9179 // CBUS_BASE: VENC_VCBUS_BASE = 0x1b
9180 // -----------------------------------------------
9181 // bit 15:8 -- vfifo2vd_vd_sel
9182 // bit 0 -- vfifo2vd_en
9183 #define ENCP_VFIFO2VD_CTL (0x1b58)
9184 #define P_ENCP_VFIFO2VD_CTL (volatile uint32_t *)((0x1b58 << 2) + 0xff900000)
9185 // bit 12:0 -- vfifo2vd_pixel_start
9186 #define ENCP_VFIFO2VD_PIXEL_START (0x1b59)
9187 #define P_ENCP_VFIFO2VD_PIXEL_START (volatile uint32_t *)((0x1b59 << 2) + 0xff900000)
9188 // bit 12:00 -- vfifo2vd_pixel_end
9189 #define ENCP_VFIFO2VD_PIXEL_END (0x1b5a)
9190 #define P_ENCP_VFIFO2VD_PIXEL_END (volatile uint32_t *)((0x1b5a << 2) + 0xff900000)
9191 // bit 10:0 -- vfifo2vd_line_top_start
9192 #define ENCP_VFIFO2VD_LINE_TOP_START (0x1b5b)
9193 #define P_ENCP_VFIFO2VD_LINE_TOP_START (volatile uint32_t *)((0x1b5b << 2) + 0xff900000)
9194 // bit 10:00 -- vfifo2vd_line_top_end
9195 #define ENCP_VFIFO2VD_LINE_TOP_END (0x1b5c)
9196 #define P_ENCP_VFIFO2VD_LINE_TOP_END (volatile uint32_t *)((0x1b5c << 2) + 0xff900000)
9197 // bit 10:00 -- vfifo2vd_line_bot_start
9198 #define ENCP_VFIFO2VD_LINE_BOT_START (0x1b5d)
9199 #define P_ENCP_VFIFO2VD_LINE_BOT_START (volatile uint32_t *)((0x1b5d << 2) + 0xff900000)
9200 // bit 10:00 -- vfifo2vd_line_bot_end
9201 #define ENCP_VFIFO2VD_LINE_BOT_END (0x1b5e)
9202 #define P_ENCP_VFIFO2VD_LINE_BOT_END (volatile uint32_t *)((0x1b5e << 2) + 0xff900000)
9203 // Route the hsync and vsync signals round the chip. There are three
9204 // sources and users of these signals: VIU, internal video encoder, and
9205 // the pins on the chip. Some muxing is still being done in the VIU. It
9206 // was not moved to the venc module so that the same exact VIU code could
9207 // be used both in Twister and Twister2000.
9208 // Bit 2: venc_sync_source (1=>pins, 0=>viu)
9209 // Bit 1: viu_sync_source (1=>pins, 0=>venc)
9210 // Bit 0: vpins_sync_source (1=>venc, 0=>viu)
9211 #define VENC_SYNC_ROUTE (0x1b60)
9212 #define P_VENC_SYNC_ROUTE (volatile uint32_t *)((0x1b60 << 2) + 0xff900000)
9213 #define VENC_VIDEO_EXSRC (0x1b61)
9214 #define P_VENC_VIDEO_EXSRC (volatile uint32_t *)((0x1b61 << 2) + 0xff900000)
9215 #define VENC_DVI_SETTING (0x1b62)
9216 #define P_VENC_DVI_SETTING (volatile uint32_t *)((0x1b62 << 2) + 0xff900000)
9217 #define VENC_C656_CTRL (0x1b63)
9218 #define P_VENC_C656_CTRL (volatile uint32_t *)((0x1b63 << 2) + 0xff900000)
9219 #define VENC_UPSAMPLE_CTRL0 (0x1b64)
9220 #define P_VENC_UPSAMPLE_CTRL0 (volatile uint32_t *)((0x1b64 << 2) + 0xff900000)
9221 #define VENC_UPSAMPLE_CTRL1 (0x1b65)
9222 #define P_VENC_UPSAMPLE_CTRL1 (volatile uint32_t *)((0x1b65 << 2) + 0xff900000)
9223 #define VENC_UPSAMPLE_CTRL2 (0x1b66)
9224 #define P_VENC_UPSAMPLE_CTRL2 (volatile uint32_t *)((0x1b66 << 2) + 0xff900000)
9225 // Invert control for tcon output
9226 // bit[15:14] -- vsync, hsync,
9227 // bit[13:0] -- oev3, oev2, cpv2, cph3, cph2, cph1, oeh, vcom, stv2, stv1, cpv1, oev1, sth1, sth2
9228 #define TCON_INVERT_CTL (0x1b67)
9229 #define P_TCON_INVERT_CTL (volatile uint32_t *)((0x1b67 << 2) + 0xff900000)
9230 #define VENC_VIDEO_PROG_MODE (0x1b68)
9231 #define P_VENC_VIDEO_PROG_MODE (volatile uint32_t *)((0x1b68 << 2) + 0xff900000)
9232 //---- Venc pixel/line info
9233 #define VENC_ENCI_LINE (0x1b69)
9234 #define P_VENC_ENCI_LINE (volatile uint32_t *)((0x1b69 << 2) + 0xff900000)
9235 #define VENC_ENCI_PIXEL (0x1b6a)
9236 #define P_VENC_ENCI_PIXEL (volatile uint32_t *)((0x1b6a << 2) + 0xff900000)
9237 #define VENC_ENCP_LINE (0x1b6b)
9238 #define P_VENC_ENCP_LINE (volatile uint32_t *)((0x1b6b << 2) + 0xff900000)
9239 #define VENC_ENCP_PIXEL (0x1b6c)
9240 #define P_VENC_ENCP_PIXEL (volatile uint32_t *)((0x1b6c << 2) + 0xff900000)
9241 //---- Status
9242 #define VENC_STATA (0x1b6d)
9243 #define P_VENC_STATA (volatile uint32_t *)((0x1b6d << 2) + 0xff900000)
9244 //---- Interrupt setting
9245 #define VENC_INTCTRL (0x1b6e)
9246 #define P_VENC_INTCTRL (volatile uint32_t *)((0x1b6e << 2) + 0xff900000)
9247 #define VENC_INTFLAG (0x1b6f)
9248 #define P_VENC_INTFLAG (volatile uint32_t *)((0x1b6f << 2) + 0xff900000)
9249 //--------- Video test configuration
9250 #define VENC_VIDEO_TST_EN (0x1b70)
9251 #define P_VENC_VIDEO_TST_EN (volatile uint32_t *)((0x1b70 << 2) + 0xff900000)
9252 #define VENC_VIDEO_TST_MDSEL (0x1b71)
9253 #define P_VENC_VIDEO_TST_MDSEL (volatile uint32_t *)((0x1b71 << 2) + 0xff900000)
9254 #define VENC_VIDEO_TST_Y (0x1b72)
9255 #define P_VENC_VIDEO_TST_Y (volatile uint32_t *)((0x1b72 << 2) + 0xff900000)
9256 #define VENC_VIDEO_TST_CB (0x1b73)
9257 #define P_VENC_VIDEO_TST_CB (volatile uint32_t *)((0x1b73 << 2) + 0xff900000)
9258 #define VENC_VIDEO_TST_CR (0x1b74)
9259 #define P_VENC_VIDEO_TST_CR (volatile uint32_t *)((0x1b74 << 2) + 0xff900000)
9260 #define VENC_VIDEO_TST_CLRBAR_STRT (0x1b75)
9261 #define P_VENC_VIDEO_TST_CLRBAR_STRT (volatile uint32_t *)((0x1b75 << 2) + 0xff900000)
9262 #define VENC_VIDEO_TST_CLRBAR_WIDTH (0x1b76)
9263 #define P_VENC_VIDEO_TST_CLRBAR_WIDTH (volatile uint32_t *)((0x1b76 << 2) + 0xff900000)
9264 #define VENC_VIDEO_TST_VDCNT_STSET (0x1b77)
9265 #define P_VENC_VIDEO_TST_VDCNT_STSET (volatile uint32_t *)((0x1b77 << 2) + 0xff900000)
9266 //----- Video dac setting
9267 #define VENC_VDAC_DACSEL0 (0x1b78)
9268 #define P_VENC_VDAC_DACSEL0 (volatile uint32_t *)((0x1b78 << 2) + 0xff900000)
9269 #define VENC_VDAC_DACSEL1 (0x1b79)
9270 #define P_VENC_VDAC_DACSEL1 (volatile uint32_t *)((0x1b79 << 2) + 0xff900000)
9271 #define VENC_VDAC_DACSEL2 (0x1b7a)
9272 #define P_VENC_VDAC_DACSEL2 (volatile uint32_t *)((0x1b7a << 2) + 0xff900000)
9273 #define VENC_VDAC_DACSEL3 (0x1b7b)
9274 #define P_VENC_VDAC_DACSEL3 (volatile uint32_t *)((0x1b7b << 2) + 0xff900000)
9275 #define VENC_VDAC_DACSEL4 (0x1b7c)
9276 #define P_VENC_VDAC_DACSEL4 (volatile uint32_t *)((0x1b7c << 2) + 0xff900000)
9277 #define VENC_VDAC_DACSEL5 (0x1b7d)
9278 #define P_VENC_VDAC_DACSEL5 (volatile uint32_t *)((0x1b7d << 2) + 0xff900000)
9279 #define VENC_VDAC_SETTING (0x1b7e)
9280 #define P_VENC_VDAC_SETTING (volatile uint32_t *)((0x1b7e << 2) + 0xff900000)
9281 #define VENC_VDAC_TST_VAL (0x1b7f)
9282 #define P_VENC_VDAC_TST_VAL (volatile uint32_t *)((0x1b7f << 2) + 0xff900000)
9283 #define VENC_VDAC_DAC0_GAINCTRL (0x1bf0)
9284 #define P_VENC_VDAC_DAC0_GAINCTRL (volatile uint32_t *)((0x1bf0 << 2) + 0xff900000)
9285 #define VENC_VDAC_DAC0_OFFSET (0x1bf1)
9286 #define P_VENC_VDAC_DAC0_OFFSET (volatile uint32_t *)((0x1bf1 << 2) + 0xff900000)
9287 #define VENC_VDAC_DAC1_GAINCTRL (0x1bf2)
9288 #define P_VENC_VDAC_DAC1_GAINCTRL (volatile uint32_t *)((0x1bf2 << 2) + 0xff900000)
9289 #define VENC_VDAC_DAC1_OFFSET (0x1bf3)
9290 #define P_VENC_VDAC_DAC1_OFFSET (volatile uint32_t *)((0x1bf3 << 2) + 0xff900000)
9291 #define VENC_VDAC_DAC2_GAINCTRL (0x1bf4)
9292 #define P_VENC_VDAC_DAC2_GAINCTRL (volatile uint32_t *)((0x1bf4 << 2) + 0xff900000)
9293 #define VENC_VDAC_DAC2_OFFSET (0x1bf5)
9294 #define P_VENC_VDAC_DAC2_OFFSET (volatile uint32_t *)((0x1bf5 << 2) + 0xff900000)
9295 #define VENC_VDAC_DAC3_GAINCTRL (0x1bf6)
9296 #define P_VENC_VDAC_DAC3_GAINCTRL (volatile uint32_t *)((0x1bf6 << 2) + 0xff900000)
9297 #define VENC_VDAC_DAC3_OFFSET (0x1bf7)
9298 #define P_VENC_VDAC_DAC3_OFFSET (volatile uint32_t *)((0x1bf7 << 2) + 0xff900000)
9299 #define VENC_VDAC_DAC4_GAINCTRL (0x1bf8)
9300 #define P_VENC_VDAC_DAC4_GAINCTRL (volatile uint32_t *)((0x1bf8 << 2) + 0xff900000)
9301 #define VENC_VDAC_DAC4_OFFSET (0x1bf9)
9302 #define P_VENC_VDAC_DAC4_OFFSET (volatile uint32_t *)((0x1bf9 << 2) + 0xff900000)
9303 #define VENC_VDAC_DAC5_GAINCTRL (0x1bfa)
9304 #define P_VENC_VDAC_DAC5_GAINCTRL (volatile uint32_t *)((0x1bfa << 2) + 0xff900000)
9305 #define VENC_VDAC_DAC5_OFFSET (0x1bfb)
9306 #define P_VENC_VDAC_DAC5_OFFSET (volatile uint32_t *)((0x1bfb << 2) + 0xff900000)
9307 #define VENC_VDAC_FIFO_CTRL (0x1bfc)
9308 #define P_VENC_VDAC_FIFO_CTRL (volatile uint32_t *)((0x1bfc << 2) + 0xff900000)
9309 #define ENCL_TCON_INVERT_CTL (0x1bfd)
9310 #define P_ENCL_TCON_INVERT_CTL (volatile uint32_t *)((0x1bfd << 2) + 0xff900000)
9311 //
9312 // Closing file: venc_regs.h
9313 //
9314 //
9315 // Reading file: enc480p_regs.h
9316 //
9317 // synopsys translate_off
9318 // synopsys translate_on
9319 //===========================================================================
9320 // Video Encoder 480p Registers 0xb80 - 0xbef
9321 //===========================================================================
9322 //-------- Video basic setting
9323 #define ENCP_VIDEO_EN (0x1b80)
9324 #define P_ENCP_VIDEO_EN (volatile uint32_t *)((0x1b80 << 2) + 0xff900000)
9325 #define ENCP_VIDEO_SYNC_MODE (0x1b81)
9326 #define P_ENCP_VIDEO_SYNC_MODE (volatile uint32_t *)((0x1b81 << 2) + 0xff900000)
9327 #define ENCP_MACV_EN (0x1b82)
9328 #define P_ENCP_MACV_EN (volatile uint32_t *)((0x1b82 << 2) + 0xff900000)
9329 #define ENCP_VIDEO_Y_SCL (0x1b83)
9330 #define P_ENCP_VIDEO_Y_SCL (volatile uint32_t *)((0x1b83 << 2) + 0xff900000)
9331 #define ENCP_VIDEO_PB_SCL (0x1b84)
9332 #define P_ENCP_VIDEO_PB_SCL (volatile uint32_t *)((0x1b84 << 2) + 0xff900000)
9333 #define ENCP_VIDEO_PR_SCL (0x1b85)
9334 #define P_ENCP_VIDEO_PR_SCL (volatile uint32_t *)((0x1b85 << 2) + 0xff900000)
9335 #define ENCP_VIDEO_SYNC_SCL (0x1b86)
9336 #define P_ENCP_VIDEO_SYNC_SCL (volatile uint32_t *)((0x1b86 << 2) + 0xff900000)
9337 #define ENCP_VIDEO_MACV_SCL (0x1b87)
9338 #define P_ENCP_VIDEO_MACV_SCL (volatile uint32_t *)((0x1b87 << 2) + 0xff900000)
9339 #define ENCP_VIDEO_Y_OFFST (0x1b88)
9340 #define P_ENCP_VIDEO_Y_OFFST (volatile uint32_t *)((0x1b88 << 2) + 0xff900000)
9341 #define ENCP_VIDEO_PB_OFFST (0x1b89)
9342 #define P_ENCP_VIDEO_PB_OFFST (volatile uint32_t *)((0x1b89 << 2) + 0xff900000)
9343 #define ENCP_VIDEO_PR_OFFST (0x1b8a)
9344 #define P_ENCP_VIDEO_PR_OFFST (volatile uint32_t *)((0x1b8a << 2) + 0xff900000)
9345 #define ENCP_VIDEO_SYNC_OFFST (0x1b8b)
9346 #define P_ENCP_VIDEO_SYNC_OFFST (volatile uint32_t *)((0x1b8b << 2) + 0xff900000)
9347 #define ENCP_VIDEO_MACV_OFFST (0x1b8c)
9348 #define P_ENCP_VIDEO_MACV_OFFST (volatile uint32_t *)((0x1b8c << 2) + 0xff900000)
9349 //----- Video mode
9350 #define ENCP_VIDEO_MODE (0x1b8d)
9351 #define P_ENCP_VIDEO_MODE (volatile uint32_t *)((0x1b8d << 2) + 0xff900000)
9352 #define ENCP_VIDEO_MODE_ADV (0x1b8e)
9353 #define P_ENCP_VIDEO_MODE_ADV (volatile uint32_t *)((0x1b8e << 2) + 0xff900000)
9354 //--------------- Debug pins
9355 #define ENCP_DBG_PX_RST (0x1b90)
9356 #define P_ENCP_DBG_PX_RST (volatile uint32_t *)((0x1b90 << 2) + 0xff900000)
9357 #define ENCP_DBG_LN_RST (0x1b91)
9358 #define P_ENCP_DBG_LN_RST (volatile uint32_t *)((0x1b91 << 2) + 0xff900000)
9359 #define ENCP_DBG_PX_INT (0x1b92)
9360 #define P_ENCP_DBG_PX_INT (volatile uint32_t *)((0x1b92 << 2) + 0xff900000)
9361 #define ENCP_DBG_LN_INT (0x1b93)
9362 #define P_ENCP_DBG_LN_INT (volatile uint32_t *)((0x1b93 << 2) + 0xff900000)
9363 //----------- Video Advanced setting
9364 #define ENCP_VIDEO_YFP1_HTIME (0x1b94)
9365 #define P_ENCP_VIDEO_YFP1_HTIME (volatile uint32_t *)((0x1b94 << 2) + 0xff900000)
9366 #define ENCP_VIDEO_YFP2_HTIME (0x1b95)
9367 #define P_ENCP_VIDEO_YFP2_HTIME (volatile uint32_t *)((0x1b95 << 2) + 0xff900000)
9368 #define ENCP_VIDEO_YC_DLY (0x1b96)
9369 #define P_ENCP_VIDEO_YC_DLY (volatile uint32_t *)((0x1b96 << 2) + 0xff900000)
9370 #define ENCP_VIDEO_MAX_PXCNT (0x1b97)
9371 #define P_ENCP_VIDEO_MAX_PXCNT (volatile uint32_t *)((0x1b97 << 2) + 0xff900000)
9372 #define ENCP_VIDEO_HSPULS_BEGIN (0x1b98)
9373 #define P_ENCP_VIDEO_HSPULS_BEGIN (volatile uint32_t *)((0x1b98 << 2) + 0xff900000)
9374 #define ENCP_VIDEO_HSPULS_END (0x1b99)
9375 #define P_ENCP_VIDEO_HSPULS_END (volatile uint32_t *)((0x1b99 << 2) + 0xff900000)
9376 #define ENCP_VIDEO_HSPULS_SWITCH (0x1b9a)
9377 #define P_ENCP_VIDEO_HSPULS_SWITCH (volatile uint32_t *)((0x1b9a << 2) + 0xff900000)
9378 #define ENCP_VIDEO_VSPULS_BEGIN (0x1b9b)
9379 #define P_ENCP_VIDEO_VSPULS_BEGIN (volatile uint32_t *)((0x1b9b << 2) + 0xff900000)
9380 #define ENCP_VIDEO_VSPULS_END (0x1b9c)
9381 #define P_ENCP_VIDEO_VSPULS_END (volatile uint32_t *)((0x1b9c << 2) + 0xff900000)
9382 #define ENCP_VIDEO_VSPULS_BLINE (0x1b9d)
9383 #define P_ENCP_VIDEO_VSPULS_BLINE (volatile uint32_t *)((0x1b9d << 2) + 0xff900000)
9384 #define ENCP_VIDEO_VSPULS_ELINE (0x1b9e)
9385 #define P_ENCP_VIDEO_VSPULS_ELINE (volatile uint32_t *)((0x1b9e << 2) + 0xff900000)
9386 #define ENCP_VIDEO_EQPULS_BEGIN (0x1b9f)
9387 #define P_ENCP_VIDEO_EQPULS_BEGIN (volatile uint32_t *)((0x1b9f << 2) + 0xff900000)
9388 #define ENCP_VIDEO_EQPULS_END (0x1ba0)
9389 #define P_ENCP_VIDEO_EQPULS_END (volatile uint32_t *)((0x1ba0 << 2) + 0xff900000)
9390 #define ENCP_VIDEO_EQPULS_BLINE (0x1ba1)
9391 #define P_ENCP_VIDEO_EQPULS_BLINE (volatile uint32_t *)((0x1ba1 << 2) + 0xff900000)
9392 #define ENCP_VIDEO_EQPULS_ELINE (0x1ba2)
9393 #define P_ENCP_VIDEO_EQPULS_ELINE (volatile uint32_t *)((0x1ba2 << 2) + 0xff900000)
9394 #define ENCP_VIDEO_HAVON_END (0x1ba3)
9395 #define P_ENCP_VIDEO_HAVON_END (volatile uint32_t *)((0x1ba3 << 2) + 0xff900000)
9396 #define ENCP_VIDEO_HAVON_BEGIN (0x1ba4)
9397 #define P_ENCP_VIDEO_HAVON_BEGIN (volatile uint32_t *)((0x1ba4 << 2) + 0xff900000)
9398 #define ENCP_VIDEO_VAVON_ELINE (0x1baf)
9399 #define P_ENCP_VIDEO_VAVON_ELINE (volatile uint32_t *)((0x1baf << 2) + 0xff900000)
9400 #define ENCP_VIDEO_VAVON_BLINE (0x1ba6)
9401 #define P_ENCP_VIDEO_VAVON_BLINE (volatile uint32_t *)((0x1ba6 << 2) + 0xff900000)
9402 #define ENCP_VIDEO_HSO_BEGIN (0x1ba7)
9403 #define P_ENCP_VIDEO_HSO_BEGIN (volatile uint32_t *)((0x1ba7 << 2) + 0xff900000)
9404 #define ENCP_VIDEO_HSO_END (0x1ba8)
9405 #define P_ENCP_VIDEO_HSO_END (volatile uint32_t *)((0x1ba8 << 2) + 0xff900000)
9406 #define ENCP_VIDEO_VSO_BEGIN (0x1ba9)
9407 #define P_ENCP_VIDEO_VSO_BEGIN (volatile uint32_t *)((0x1ba9 << 2) + 0xff900000)
9408 #define ENCP_VIDEO_VSO_END (0x1baa)
9409 #define P_ENCP_VIDEO_VSO_END (volatile uint32_t *)((0x1baa << 2) + 0xff900000)
9410 #define ENCP_VIDEO_VSO_BLINE (0x1bab)
9411 #define P_ENCP_VIDEO_VSO_BLINE (volatile uint32_t *)((0x1bab << 2) + 0xff900000)
9412 #define ENCP_VIDEO_VSO_ELINE (0x1bac)
9413 #define P_ENCP_VIDEO_VSO_ELINE (volatile uint32_t *)((0x1bac << 2) + 0xff900000)
9414 #define ENCP_VIDEO_SYNC_WAVE_CURVE (0x1bad)
9415 #define P_ENCP_VIDEO_SYNC_WAVE_CURVE (volatile uint32_t *)((0x1bad << 2) + 0xff900000)
9416 #define ENCP_VIDEO_MAX_LNCNT (0x1bae)
9417 #define P_ENCP_VIDEO_MAX_LNCNT (volatile uint32_t *)((0x1bae << 2) + 0xff900000)
9418 #define ENCP_VIDEO_SY_VAL (0x1bb0)
9419 #define P_ENCP_VIDEO_SY_VAL (volatile uint32_t *)((0x1bb0 << 2) + 0xff900000)
9420 #define ENCP_VIDEO_SY2_VAL (0x1bb1)
9421 #define P_ENCP_VIDEO_SY2_VAL (volatile uint32_t *)((0x1bb1 << 2) + 0xff900000)
9422 #define ENCP_VIDEO_BLANKY_VAL (0x1bb2)
9423 #define P_ENCP_VIDEO_BLANKY_VAL (volatile uint32_t *)((0x1bb2 << 2) + 0xff900000)
9424 #define ENCP_VIDEO_BLANKPB_VAL (0x1bb3)
9425 #define P_ENCP_VIDEO_BLANKPB_VAL (volatile uint32_t *)((0x1bb3 << 2) + 0xff900000)
9426 #define ENCP_VIDEO_BLANKPR_VAL (0x1bb4)
9427 #define P_ENCP_VIDEO_BLANKPR_VAL (volatile uint32_t *)((0x1bb4 << 2) + 0xff900000)
9428 #define ENCP_VIDEO_HOFFST (0x1bb5)
9429 #define P_ENCP_VIDEO_HOFFST (volatile uint32_t *)((0x1bb5 << 2) + 0xff900000)
9430 #define ENCP_VIDEO_VOFFST (0x1bb6)
9431 #define P_ENCP_VIDEO_VOFFST (volatile uint32_t *)((0x1bb6 << 2) + 0xff900000)
9432 #define ENCP_VIDEO_RGB_CTRL (0x1bb7)
9433 #define P_ENCP_VIDEO_RGB_CTRL (volatile uint32_t *)((0x1bb7 << 2) + 0xff900000)
9434 #define ENCP_VIDEO_FILT_CTRL (0x1bb8)
9435 #define P_ENCP_VIDEO_FILT_CTRL (volatile uint32_t *)((0x1bb8 << 2) + 0xff900000)
9436 #define ENCP_VIDEO_OFLD_VPEQ_OFST (0x1bb9)
9437 #define P_ENCP_VIDEO_OFLD_VPEQ_OFST (volatile uint32_t *)((0x1bb9 << 2) + 0xff900000)
9438 #define ENCP_VIDEO_OFLD_VOAV_OFST (0x1bba)
9439 #define P_ENCP_VIDEO_OFLD_VOAV_OFST (volatile uint32_t *)((0x1bba << 2) + 0xff900000)
9440 #define ENCP_VIDEO_MATRIX_CB (0x1bbb)
9441 #define P_ENCP_VIDEO_MATRIX_CB (volatile uint32_t *)((0x1bbb << 2) + 0xff900000)
9442 #define ENCP_VIDEO_MATRIX_CR (0x1bbc)
9443 #define P_ENCP_VIDEO_MATRIX_CR (volatile uint32_t *)((0x1bbc << 2) + 0xff900000)
9444 #define ENCP_VIDEO_RGBIN_CTRL (0x1bbd)
9445 #define P_ENCP_VIDEO_RGBIN_CTRL (volatile uint32_t *)((0x1bbd << 2) + 0xff900000)
9446 //------------------Macrovision advanced setting
9447 #define ENCP_MACV_BLANKY_VAL (0x1bc0)
9448 #define P_ENCP_MACV_BLANKY_VAL (volatile uint32_t *)((0x1bc0 << 2) + 0xff900000)
9449 #define ENCP_MACV_MAXY_VAL (0x1bc1)
9450 #define P_ENCP_MACV_MAXY_VAL (volatile uint32_t *)((0x1bc1 << 2) + 0xff900000)
9451 #define ENCP_MACV_1ST_PSSYNC_STRT (0x1bc2)
9452 #define P_ENCP_MACV_1ST_PSSYNC_STRT (volatile uint32_t *)((0x1bc2 << 2) + 0xff900000)
9453 #define ENCP_MACV_PSSYNC_STRT (0x1bc3)
9454 #define P_ENCP_MACV_PSSYNC_STRT (volatile uint32_t *)((0x1bc3 << 2) + 0xff900000)
9455 #define ENCP_MACV_AGC_STRT (0x1bc4)
9456 #define P_ENCP_MACV_AGC_STRT (volatile uint32_t *)((0x1bc4 << 2) + 0xff900000)
9457 #define ENCP_MACV_AGC_END (0x1bc5)
9458 #define P_ENCP_MACV_AGC_END (volatile uint32_t *)((0x1bc5 << 2) + 0xff900000)
9459 #define ENCP_MACV_WAVE_END (0x1bc6)
9460 #define P_ENCP_MACV_WAVE_END (volatile uint32_t *)((0x1bc6 << 2) + 0xff900000)
9461 #define ENCP_MACV_STRTLINE (0x1bc7)
9462 #define P_ENCP_MACV_STRTLINE (volatile uint32_t *)((0x1bc7 << 2) + 0xff900000)
9463 #define ENCP_MACV_ENDLINE (0x1bc8)
9464 #define P_ENCP_MACV_ENDLINE (volatile uint32_t *)((0x1bc8 << 2) + 0xff900000)
9465 #define ENCP_MACV_TS_CNT_MAX_L (0x1bc9)
9466 #define P_ENCP_MACV_TS_CNT_MAX_L (volatile uint32_t *)((0x1bc9 << 2) + 0xff900000)
9467 #define ENCP_MACV_TS_CNT_MAX_H (0x1bca)
9468 #define P_ENCP_MACV_TS_CNT_MAX_H (volatile uint32_t *)((0x1bca << 2) + 0xff900000)
9469 #define ENCP_MACV_TIME_DOWN (0x1bcb)
9470 #define P_ENCP_MACV_TIME_DOWN (volatile uint32_t *)((0x1bcb << 2) + 0xff900000)
9471 #define ENCP_MACV_TIME_LO (0x1bcc)
9472 #define P_ENCP_MACV_TIME_LO (volatile uint32_t *)((0x1bcc << 2) + 0xff900000)
9473 #define ENCP_MACV_TIME_UP (0x1bcd)
9474 #define P_ENCP_MACV_TIME_UP (volatile uint32_t *)((0x1bcd << 2) + 0xff900000)
9475 #define ENCP_MACV_TIME_RST (0x1bce)
9476 #define P_ENCP_MACV_TIME_RST (volatile uint32_t *)((0x1bce << 2) + 0xff900000)
9477 //---------------- VBI control -------------------
9478 #define ENCP_VBI_CTRL (0x1bd0)
9479 #define P_ENCP_VBI_CTRL (volatile uint32_t *)((0x1bd0 << 2) + 0xff900000)
9480 #define ENCP_VBI_SETTING (0x1bd1)
9481 #define P_ENCP_VBI_SETTING (volatile uint32_t *)((0x1bd1 << 2) + 0xff900000)
9482 #define ENCP_VBI_BEGIN (0x1bd2)
9483 #define P_ENCP_VBI_BEGIN (volatile uint32_t *)((0x1bd2 << 2) + 0xff900000)
9484 #define ENCP_VBI_WIDTH (0x1bd3)
9485 #define P_ENCP_VBI_WIDTH (volatile uint32_t *)((0x1bd3 << 2) + 0xff900000)
9486 #define ENCP_VBI_HVAL (0x1bd4)
9487 #define P_ENCP_VBI_HVAL (volatile uint32_t *)((0x1bd4 << 2) + 0xff900000)
9488 #define ENCP_VBI_DATA0 (0x1bd5)
9489 #define P_ENCP_VBI_DATA0 (volatile uint32_t *)((0x1bd5 << 2) + 0xff900000)
9490 #define ENCP_VBI_DATA1 (0x1bd6)
9491 #define P_ENCP_VBI_DATA1 (volatile uint32_t *)((0x1bd6 << 2) + 0xff900000)
9492 //----------------C656 OUT Control------------- Grant
9493 #define C656_HS_ST (0x1be0)
9494 #define P_C656_HS_ST (volatile uint32_t *)((0x1be0 << 2) + 0xff900000)
9495 #define C656_HS_ED (0x1be1)
9496 #define P_C656_HS_ED (volatile uint32_t *)((0x1be1 << 2) + 0xff900000)
9497 #define C656_VS_LNST_E (0x1be2)
9498 #define P_C656_VS_LNST_E (volatile uint32_t *)((0x1be2 << 2) + 0xff900000)
9499 #define C656_VS_LNST_O (0x1be3)
9500 #define P_C656_VS_LNST_O (volatile uint32_t *)((0x1be3 << 2) + 0xff900000)
9501 #define C656_VS_LNED_E (0x1be4)
9502 #define P_C656_VS_LNED_E (volatile uint32_t *)((0x1be4 << 2) + 0xff900000)
9503 #define C656_VS_LNED_O (0x1be5)
9504 #define P_C656_VS_LNED_O (volatile uint32_t *)((0x1be5 << 2) + 0xff900000)
9505 #define C656_FS_LNST (0x1be6)
9506 #define P_C656_FS_LNST (volatile uint32_t *)((0x1be6 << 2) + 0xff900000)
9507 #define C656_FS_LNED (0x1be7)
9508 #define P_C656_FS_LNED (volatile uint32_t *)((0x1be7 << 2) + 0xff900000)
9509 // synopsys translate_off
9510 // synopsys translate_on
9511 //
9512 // Closing file: enc480p_regs.h
9513 //
9514 //
9515 // Reading file: enci_regs.h
9516 //
9517 //===========================================================================
9518 // Video Interface Registers 0xb00 - 0xb57
9519 //===========================================================================
9520 #define ENCI_VIDEO_MODE (0x1b00)
9521 #define P_ENCI_VIDEO_MODE (volatile uint32_t *)((0x1b00 << 2) + 0xff900000)
9522 #define ENCI_VIDEO_MODE_ADV (0x1b01)
9523 #define P_ENCI_VIDEO_MODE_ADV (volatile uint32_t *)((0x1b01 << 2) + 0xff900000)
9524 #define ENCI_VIDEO_FSC_ADJ (0x1b02)
9525 #define P_ENCI_VIDEO_FSC_ADJ (volatile uint32_t *)((0x1b02 << 2) + 0xff900000)
9526 #define ENCI_VIDEO_BRIGHT (0x1b03)
9527 #define P_ENCI_VIDEO_BRIGHT (volatile uint32_t *)((0x1b03 << 2) + 0xff900000)
9528 #define ENCI_VIDEO_CONT (0x1b04)
9529 #define P_ENCI_VIDEO_CONT (volatile uint32_t *)((0x1b04 << 2) + 0xff900000)
9530 #define ENCI_VIDEO_SAT (0x1b05)
9531 #define P_ENCI_VIDEO_SAT (volatile uint32_t *)((0x1b05 << 2) + 0xff900000)
9532 #define ENCI_VIDEO_HUE (0x1b06)
9533 #define P_ENCI_VIDEO_HUE (volatile uint32_t *)((0x1b06 << 2) + 0xff900000)
9534 #define ENCI_VIDEO_SCH (0x1b07)
9535 #define P_ENCI_VIDEO_SCH (volatile uint32_t *)((0x1b07 << 2) + 0xff900000)
9536 #define ENCI_SYNC_MODE (0x1b08)
9537 #define P_ENCI_SYNC_MODE (volatile uint32_t *)((0x1b08 << 2) + 0xff900000)
9538 #define ENCI_SYNC_CTRL (0x1b09)
9539 #define P_ENCI_SYNC_CTRL (volatile uint32_t *)((0x1b09 << 2) + 0xff900000)
9540 #define ENCI_SYNC_HSO_BEGIN (0x1b0a)
9541 #define P_ENCI_SYNC_HSO_BEGIN (volatile uint32_t *)((0x1b0a << 2) + 0xff900000)
9542 #define ENCI_SYNC_HSO_END (0x1b0b)
9543 #define P_ENCI_SYNC_HSO_END (volatile uint32_t *)((0x1b0b << 2) + 0xff900000)
9544 #define ENCI_SYNC_VSO_EVN (0x1b0c)
9545 #define P_ENCI_SYNC_VSO_EVN (volatile uint32_t *)((0x1b0c << 2) + 0xff900000)
9546 #define ENCI_SYNC_VSO_ODD (0x1b0d)
9547 #define P_ENCI_SYNC_VSO_ODD (volatile uint32_t *)((0x1b0d << 2) + 0xff900000)
9548 #define ENCI_SYNC_VSO_EVNLN (0x1b0e)
9549 #define P_ENCI_SYNC_VSO_EVNLN (volatile uint32_t *)((0x1b0e << 2) + 0xff900000)
9550 #define ENCI_SYNC_VSO_ODDLN (0x1b0f)
9551 #define P_ENCI_SYNC_VSO_ODDLN (volatile uint32_t *)((0x1b0f << 2) + 0xff900000)
9552 #define ENCI_SYNC_HOFFST (0x1b10)
9553 #define P_ENCI_SYNC_HOFFST (volatile uint32_t *)((0x1b10 << 2) + 0xff900000)
9554 #define ENCI_SYNC_VOFFST (0x1b11)
9555 #define P_ENCI_SYNC_VOFFST (volatile uint32_t *)((0x1b11 << 2) + 0xff900000)
9556 #define ENCI_SYNC_ADJ (0x1b12)
9557 #define P_ENCI_SYNC_ADJ (volatile uint32_t *)((0x1b12 << 2) + 0xff900000)
9558 #define ENCI_RGB_SETTING (0x1b13)
9559 #define P_ENCI_RGB_SETTING (volatile uint32_t *)((0x1b13 << 2) + 0xff900000)
9560 //`define ENCI_CMPN_MATRIX_CB 8'h14
9561 //`define ENCI_CMPN_MATRIX_CR 8'h15
9562 #define ENCI_DE_H_BEGIN (0x1b16)
9563 #define P_ENCI_DE_H_BEGIN (volatile uint32_t *)((0x1b16 << 2) + 0xff900000)
9564 #define ENCI_DE_H_END (0x1b17)
9565 #define P_ENCI_DE_H_END (volatile uint32_t *)((0x1b17 << 2) + 0xff900000)
9566 #define ENCI_DE_V_BEGIN_EVEN (0x1b18)
9567 #define P_ENCI_DE_V_BEGIN_EVEN (volatile uint32_t *)((0x1b18 << 2) + 0xff900000)
9568 #define ENCI_DE_V_END_EVEN (0x1b19)
9569 #define P_ENCI_DE_V_END_EVEN (volatile uint32_t *)((0x1b19 << 2) + 0xff900000)
9570 #define ENCI_DE_V_BEGIN_ODD (0x1b1a)
9571 #define P_ENCI_DE_V_BEGIN_ODD (volatile uint32_t *)((0x1b1a << 2) + 0xff900000)
9572 #define ENCI_DE_V_END_ODD (0x1b1b)
9573 #define P_ENCI_DE_V_END_ODD (volatile uint32_t *)((0x1b1b << 2) + 0xff900000)
9574 #define ENCI_VBI_SETTING (0x1b20)
9575 #define P_ENCI_VBI_SETTING (volatile uint32_t *)((0x1b20 << 2) + 0xff900000)
9576 #define ENCI_VBI_CCDT_EVN (0x1b21)
9577 #define P_ENCI_VBI_CCDT_EVN (volatile uint32_t *)((0x1b21 << 2) + 0xff900000)
9578 #define ENCI_VBI_CCDT_ODD (0x1b22)
9579 #define P_ENCI_VBI_CCDT_ODD (volatile uint32_t *)((0x1b22 << 2) + 0xff900000)
9580 #define ENCI_VBI_CC525_LN (0x1b23)
9581 #define P_ENCI_VBI_CC525_LN (volatile uint32_t *)((0x1b23 << 2) + 0xff900000)
9582 #define ENCI_VBI_CC625_LN (0x1b24)
9583 #define P_ENCI_VBI_CC625_LN (volatile uint32_t *)((0x1b24 << 2) + 0xff900000)
9584 #define ENCI_VBI_WSSDT (0x1b25)
9585 #define P_ENCI_VBI_WSSDT (volatile uint32_t *)((0x1b25 << 2) + 0xff900000)
9586 #define ENCI_VBI_WSS_LN (0x1b26)
9587 #define P_ENCI_VBI_WSS_LN (volatile uint32_t *)((0x1b26 << 2) + 0xff900000)
9588 #define ENCI_VBI_CGMSDT_L (0x1b27)
9589 #define P_ENCI_VBI_CGMSDT_L (volatile uint32_t *)((0x1b27 << 2) + 0xff900000)
9590 #define ENCI_VBI_CGMSDT_H (0x1b28)
9591 #define P_ENCI_VBI_CGMSDT_H (volatile uint32_t *)((0x1b28 << 2) + 0xff900000)
9592 #define ENCI_VBI_CGMS_LN (0x1b29)
9593 #define P_ENCI_VBI_CGMS_LN (volatile uint32_t *)((0x1b29 << 2) + 0xff900000)
9594 #define ENCI_VBI_TTX_HTIME (0x1b2a)
9595 #define P_ENCI_VBI_TTX_HTIME (volatile uint32_t *)((0x1b2a << 2) + 0xff900000)
9596 #define ENCI_VBI_TTX_LN (0x1b2b)
9597 #define P_ENCI_VBI_TTX_LN (volatile uint32_t *)((0x1b2b << 2) + 0xff900000)
9598 #define ENCI_VBI_TTXDT0 (0x1b2c)
9599 #define P_ENCI_VBI_TTXDT0 (volatile uint32_t *)((0x1b2c << 2) + 0xff900000)
9600 #define ENCI_VBI_TTXDT1 (0x1b2d)
9601 #define P_ENCI_VBI_TTXDT1 (volatile uint32_t *)((0x1b2d << 2) + 0xff900000)
9602 #define ENCI_VBI_TTXDT2 (0x1b2e)
9603 #define P_ENCI_VBI_TTXDT2 (volatile uint32_t *)((0x1b2e << 2) + 0xff900000)
9604 #define ENCI_VBI_TTXDT3 (0x1b2f)
9605 #define P_ENCI_VBI_TTXDT3 (volatile uint32_t *)((0x1b2f << 2) + 0xff900000)
9606 #define ENCI_MACV_N0 (0x1b30)
9607 #define P_ENCI_MACV_N0 (volatile uint32_t *)((0x1b30 << 2) + 0xff900000)
9608 #define ENCI_MACV_N1 (0x1b31)
9609 #define P_ENCI_MACV_N1 (volatile uint32_t *)((0x1b31 << 2) + 0xff900000)
9610 #define ENCI_MACV_N2 (0x1b32)
9611 #define P_ENCI_MACV_N2 (volatile uint32_t *)((0x1b32 << 2) + 0xff900000)
9612 #define ENCI_MACV_N3 (0x1b33)
9613 #define P_ENCI_MACV_N3 (volatile uint32_t *)((0x1b33 << 2) + 0xff900000)
9614 #define ENCI_MACV_N4 (0x1b34)
9615 #define P_ENCI_MACV_N4 (volatile uint32_t *)((0x1b34 << 2) + 0xff900000)
9616 #define ENCI_MACV_N5 (0x1b35)
9617 #define P_ENCI_MACV_N5 (volatile uint32_t *)((0x1b35 << 2) + 0xff900000)
9618 #define ENCI_MACV_N6 (0x1b36)
9619 #define P_ENCI_MACV_N6 (volatile uint32_t *)((0x1b36 << 2) + 0xff900000)
9620 #define ENCI_MACV_N7 (0x1b37)
9621 #define P_ENCI_MACV_N7 (volatile uint32_t *)((0x1b37 << 2) + 0xff900000)
9622 #define ENCI_MACV_N8 (0x1b38)
9623 #define P_ENCI_MACV_N8 (volatile uint32_t *)((0x1b38 << 2) + 0xff900000)
9624 #define ENCI_MACV_N9 (0x1b39)
9625 #define P_ENCI_MACV_N9 (volatile uint32_t *)((0x1b39 << 2) + 0xff900000)
9626 #define ENCI_MACV_N10 (0x1b3a)
9627 #define P_ENCI_MACV_N10 (volatile uint32_t *)((0x1b3a << 2) + 0xff900000)
9628 #define ENCI_MACV_N11 (0x1b3b)
9629 #define P_ENCI_MACV_N11 (volatile uint32_t *)((0x1b3b << 2) + 0xff900000)
9630 #define ENCI_MACV_N12 (0x1b3c)
9631 #define P_ENCI_MACV_N12 (volatile uint32_t *)((0x1b3c << 2) + 0xff900000)
9632 #define ENCI_MACV_N13 (0x1b3d)
9633 #define P_ENCI_MACV_N13 (volatile uint32_t *)((0x1b3d << 2) + 0xff900000)
9634 #define ENCI_MACV_N14 (0x1b3e)
9635 #define P_ENCI_MACV_N14 (volatile uint32_t *)((0x1b3e << 2) + 0xff900000)
9636 #define ENCI_MACV_N15 (0x1b3f)
9637 #define P_ENCI_MACV_N15 (volatile uint32_t *)((0x1b3f << 2) + 0xff900000)
9638 #define ENCI_MACV_N16 (0x1b40)
9639 #define P_ENCI_MACV_N16 (volatile uint32_t *)((0x1b40 << 2) + 0xff900000)
9640 #define ENCI_MACV_N17 (0x1b41)
9641 #define P_ENCI_MACV_N17 (volatile uint32_t *)((0x1b41 << 2) + 0xff900000)
9642 #define ENCI_MACV_N18 (0x1b42)
9643 #define P_ENCI_MACV_N18 (volatile uint32_t *)((0x1b42 << 2) + 0xff900000)
9644 #define ENCI_MACV_N19 (0x1b43)
9645 #define P_ENCI_MACV_N19 (volatile uint32_t *)((0x1b43 << 2) + 0xff900000)
9646 #define ENCI_MACV_N20 (0x1b44)
9647 #define P_ENCI_MACV_N20 (volatile uint32_t *)((0x1b44 << 2) + 0xff900000)
9648 #define ENCI_MACV_N21 (0x1b45)
9649 #define P_ENCI_MACV_N21 (volatile uint32_t *)((0x1b45 << 2) + 0xff900000)
9650 #define ENCI_MACV_N22 (0x1b46)
9651 #define P_ENCI_MACV_N22 (volatile uint32_t *)((0x1b46 << 2) + 0xff900000)
9652 //`define ENCI_MACV_P_AGC 8'h47
9653 #define ENCI_DBG_PX_RST (0x1b48)
9654 #define P_ENCI_DBG_PX_RST (volatile uint32_t *)((0x1b48 << 2) + 0xff900000)
9655 #define ENCI_DBG_FLDLN_RST (0x1b49)
9656 #define P_ENCI_DBG_FLDLN_RST (volatile uint32_t *)((0x1b49 << 2) + 0xff900000)
9657 #define ENCI_DBG_PX_INT (0x1b4a)
9658 #define P_ENCI_DBG_PX_INT (volatile uint32_t *)((0x1b4a << 2) + 0xff900000)
9659 #define ENCI_DBG_FLDLN_INT (0x1b4b)
9660 #define P_ENCI_DBG_FLDLN_INT (volatile uint32_t *)((0x1b4b << 2) + 0xff900000)
9661 #define ENCI_DBG_MAXPX (0x1b4c)
9662 #define P_ENCI_DBG_MAXPX (volatile uint32_t *)((0x1b4c << 2) + 0xff900000)
9663 #define ENCI_DBG_MAXLN (0x1b4d)
9664 #define P_ENCI_DBG_MAXLN (volatile uint32_t *)((0x1b4d << 2) + 0xff900000)
9665 #define ENCI_MACV_MAX_AMP (0x1b50)
9666 #define P_ENCI_MACV_MAX_AMP (volatile uint32_t *)((0x1b50 << 2) + 0xff900000)
9667 #define ENCI_MACV_PULSE_LO (0x1b51)
9668 #define P_ENCI_MACV_PULSE_LO (volatile uint32_t *)((0x1b51 << 2) + 0xff900000)
9669 #define ENCI_MACV_PULSE_HI (0x1b52)
9670 #define P_ENCI_MACV_PULSE_HI (volatile uint32_t *)((0x1b52 << 2) + 0xff900000)
9671 #define ENCI_MACV_BKP_MAX (0x1b53)
9672 #define P_ENCI_MACV_BKP_MAX (volatile uint32_t *)((0x1b53 << 2) + 0xff900000)
9673 #define ENCI_CFILT_CTRL (0x1b54)
9674 #define P_ENCI_CFILT_CTRL (volatile uint32_t *)((0x1b54 << 2) + 0xff900000)
9675 #define ENCI_CFILT7 (0x1b55)
9676 #define P_ENCI_CFILT7 (volatile uint32_t *)((0x1b55 << 2) + 0xff900000)
9677 #define ENCI_YC_DELAY (0x1b56)
9678 #define P_ENCI_YC_DELAY (volatile uint32_t *)((0x1b56 << 2) + 0xff900000)
9679 #define ENCI_VIDEO_EN (0x1b57)
9680 #define P_ENCI_VIDEO_EN (volatile uint32_t *)((0x1b57 << 2) + 0xff900000)
9681 //
9682 // Closing file: enci_regs.h
9683 //
9684 //`define VENC2_VCBUS_BASE 8'h1c
9685 //
9686 // Reading file: venc2_regs.h
9687 //
9688 //===========================================================================
9689 // Venc Registers (Cont.) 0xc00 - 0xcff (VENC registers 0xc00 - 0xcef)
9690 //===========================================================================
9691 // -----------------------------------------------
9692 // CBUS_BASE: VENC2_VCBUS_BASE = 0x1c
9693 // -----------------------------------------------
9694 // Program video control signals from ENCI core to DVI/HDMI interface
9695 #define ENCI_DVI_HSO_BEGIN (0x1c00)
9696 #define P_ENCI_DVI_HSO_BEGIN (volatile uint32_t *)((0x1c00 << 2) + 0xff900000)
9697 #define ENCI_DVI_HSO_END (0x1c01)
9698 #define P_ENCI_DVI_HSO_END (volatile uint32_t *)((0x1c01 << 2) + 0xff900000)
9699 #define ENCI_DVI_VSO_BLINE_EVN (0x1c02)
9700 #define P_ENCI_DVI_VSO_BLINE_EVN (volatile uint32_t *)((0x1c02 << 2) + 0xff900000)
9701 #define ENCI_DVI_VSO_BLINE_ODD (0x1c03)
9702 #define P_ENCI_DVI_VSO_BLINE_ODD (volatile uint32_t *)((0x1c03 << 2) + 0xff900000)
9703 #define ENCI_DVI_VSO_ELINE_EVN (0x1c04)
9704 #define P_ENCI_DVI_VSO_ELINE_EVN (volatile uint32_t *)((0x1c04 << 2) + 0xff900000)
9705 #define ENCI_DVI_VSO_ELINE_ODD (0x1c05)
9706 #define P_ENCI_DVI_VSO_ELINE_ODD (volatile uint32_t *)((0x1c05 << 2) + 0xff900000)
9707 #define ENCI_DVI_VSO_BEGIN_EVN (0x1c06)
9708 #define P_ENCI_DVI_VSO_BEGIN_EVN (volatile uint32_t *)((0x1c06 << 2) + 0xff900000)
9709 #define ENCI_DVI_VSO_BEGIN_ODD (0x1c07)
9710 #define P_ENCI_DVI_VSO_BEGIN_ODD (volatile uint32_t *)((0x1c07 << 2) + 0xff900000)
9711 #define ENCI_DVI_VSO_END_EVN (0x1c08)
9712 #define P_ENCI_DVI_VSO_END_EVN (volatile uint32_t *)((0x1c08 << 2) + 0xff900000)
9713 #define ENCI_DVI_VSO_END_ODD (0x1c09)
9714 #define P_ENCI_DVI_VSO_END_ODD (volatile uint32_t *)((0x1c09 << 2) + 0xff900000)
9715 // Define cmpt and cvbs cb/cr delay after ENCI chroma filters
9716 // Bit 15:12 RW, enci_cb_cvbs_dly_sel. 0=no delay; 1~6=delay by 1~6 clk; 7~15 reserved.
9717 // Bit 11: 8 RW, enci_cr_cvbs_dly_sel. 0=no delay; 1~6=delay by 1~6 clk; 7~15 reserved.
9718 // Bit 7: 4 RW, enci_cb_cmpt_dly_sel. 0=no delay; 1~6=delay by 1~6 clk; 7~15 reserved.
9719 // Bit 3: 0 RW, enci_cr_cmpt_dly_sel. 0=no delay; 1~6=delay by 1~6 clk; 7~15 reserved.
9720 #define ENCI_CFILT_CTRL2 (0x1c0a)
9721 #define P_ENCI_CFILT_CTRL2 (volatile uint32_t *)((0x1c0a << 2) + 0xff900000)
9722 #define ENCI_DACSEL_0 (0x1c0b)
9723 #define P_ENCI_DACSEL_0 (volatile uint32_t *)((0x1c0b << 2) + 0xff900000)
9724 #define ENCI_DACSEL_1 (0x1c0c)
9725 #define P_ENCI_DACSEL_1 (volatile uint32_t *)((0x1c0c << 2) + 0xff900000)
9726 #define ENCP_DACSEL_0 (0x1c0d)
9727 #define P_ENCP_DACSEL_0 (volatile uint32_t *)((0x1c0d << 2) + 0xff900000)
9728 #define ENCP_DACSEL_1 (0x1c0e)
9729 #define P_ENCP_DACSEL_1 (volatile uint32_t *)((0x1c0e << 2) + 0xff900000)
9730 #define ENCP_MAX_LINE_SWITCH_POINT (0x1c0f)
9731 #define P_ENCP_MAX_LINE_SWITCH_POINT (volatile uint32_t *)((0x1c0f << 2) + 0xff900000)
9732 #define ENCI_TST_EN (0x1c10)
9733 #define P_ENCI_TST_EN (volatile uint32_t *)((0x1c10 << 2) + 0xff900000)
9734 #define ENCI_TST_MDSEL (0x1c11)
9735 #define P_ENCI_TST_MDSEL (volatile uint32_t *)((0x1c11 << 2) + 0xff900000)
9736 #define ENCI_TST_Y (0x1c12)
9737 #define P_ENCI_TST_Y (volatile uint32_t *)((0x1c12 << 2) + 0xff900000)
9738 #define ENCI_TST_CB (0x1c13)
9739 #define P_ENCI_TST_CB (volatile uint32_t *)((0x1c13 << 2) + 0xff900000)
9740 #define ENCI_TST_CR (0x1c14)
9741 #define P_ENCI_TST_CR (volatile uint32_t *)((0x1c14 << 2) + 0xff900000)
9742 #define ENCI_TST_CLRBAR_STRT (0x1c15)
9743 #define P_ENCI_TST_CLRBAR_STRT (volatile uint32_t *)((0x1c15 << 2) + 0xff900000)
9744 #define ENCI_TST_CLRBAR_WIDTH (0x1c16)
9745 #define P_ENCI_TST_CLRBAR_WIDTH (volatile uint32_t *)((0x1c16 << 2) + 0xff900000)
9746 #define ENCI_TST_VDCNT_STSET (0x1c17)
9747 #define P_ENCI_TST_VDCNT_STSET (volatile uint32_t *)((0x1c17 << 2) + 0xff900000)
9748 // bit 15:8 -- vfifo2vd_vd_sel
9749 // bit 7 -- vfifo2vd_drop
9750 // bit 6:1 -- vfifo2vd_delay
9751 // bit 0 -- vfifo2vd_en
9752 #define ENCI_VFIFO2VD_CTL (0x1c18)
9753 #define P_ENCI_VFIFO2VD_CTL (volatile uint32_t *)((0x1c18 << 2) + 0xff900000)
9754 // bit 12:0 -- vfifo2vd_pixel_start
9755 #define ENCI_VFIFO2VD_PIXEL_START (0x1c19)
9756 #define P_ENCI_VFIFO2VD_PIXEL_START (volatile uint32_t *)((0x1c19 << 2) + 0xff900000)
9757 // bit 12:00 -- vfifo2vd_pixel_end
9758 #define ENCI_VFIFO2VD_PIXEL_END (0x1c1a)
9759 #define P_ENCI_VFIFO2VD_PIXEL_END (volatile uint32_t *)((0x1c1a << 2) + 0xff900000)
9760 // bit 10:0 -- vfifo2vd_line_top_start
9761 #define ENCI_VFIFO2VD_LINE_TOP_START (0x1c1b)
9762 #define P_ENCI_VFIFO2VD_LINE_TOP_START (volatile uint32_t *)((0x1c1b << 2) + 0xff900000)
9763 // bit 10:00 -- vfifo2vd_line_top_end
9764 #define ENCI_VFIFO2VD_LINE_TOP_END (0x1c1c)
9765 #define P_ENCI_VFIFO2VD_LINE_TOP_END (volatile uint32_t *)((0x1c1c << 2) + 0xff900000)
9766 // bit 10:00 -- vfifo2vd_line_bot_start
9767 #define ENCI_VFIFO2VD_LINE_BOT_START (0x1c1d)
9768 #define P_ENCI_VFIFO2VD_LINE_BOT_START (volatile uint32_t *)((0x1c1d << 2) + 0xff900000)
9769 // bit 10:00 -- vfifo2vd_line_bot_end
9770 #define ENCI_VFIFO2VD_LINE_BOT_END (0x1c1e)
9771 #define P_ENCI_VFIFO2VD_LINE_BOT_END (volatile uint32_t *)((0x1c1e << 2) + 0xff900000)
9772 #define ENCI_VFIFO2VD_CTL2 (0x1c1f)
9773 #define P_ENCI_VFIFO2VD_CTL2 (volatile uint32_t *)((0x1c1f << 2) + 0xff900000)
9774 // bit 15:8 -- vfifo2vd_vd_sel
9775 // bit 7 -- vfifo2vd_drop
9776 // bit 6:1 -- vfifo2vd_delay
9777 // bit 0 -- vfifo2vd_en
9778 #define ENCT_VFIFO2VD_CTL (0x1c20)
9779 #define P_ENCT_VFIFO2VD_CTL (volatile uint32_t *)((0x1c20 << 2) + 0xff900000)
9780 // bit 12:0 -- vfifo2vd_pixel_start
9781 #define ENCT_VFIFO2VD_PIXEL_START (0x1c21)
9782 #define P_ENCT_VFIFO2VD_PIXEL_START (volatile uint32_t *)((0x1c21 << 2) + 0xff900000)
9783 // bit 12:00 -- vfifo2vd_pixel_end
9784 #define ENCT_VFIFO2VD_PIXEL_END (0x1c22)
9785 #define P_ENCT_VFIFO2VD_PIXEL_END (volatile uint32_t *)((0x1c22 << 2) + 0xff900000)
9786 // bit 10:0 -- vfifo2vd_line_top_start
9787 #define ENCT_VFIFO2VD_LINE_TOP_START (0x1c23)
9788 #define P_ENCT_VFIFO2VD_LINE_TOP_START (volatile uint32_t *)((0x1c23 << 2) + 0xff900000)
9789 // bit 10:00 -- vfifo2vd_line_top_end
9790 #define ENCT_VFIFO2VD_LINE_TOP_END (0x1c24)
9791 #define P_ENCT_VFIFO2VD_LINE_TOP_END (volatile uint32_t *)((0x1c24 << 2) + 0xff900000)
9792 // bit 10:00 -- vfifo2vd_line_bot_start
9793 #define ENCT_VFIFO2VD_LINE_BOT_START (0x1c25)
9794 #define P_ENCT_VFIFO2VD_LINE_BOT_START (volatile uint32_t *)((0x1c25 << 2) + 0xff900000)
9795 // bit 10:00 -- vfifo2vd_line_bot_end
9796 #define ENCT_VFIFO2VD_LINE_BOT_END (0x1c26)
9797 #define P_ENCT_VFIFO2VD_LINE_BOT_END (volatile uint32_t *)((0x1c26 << 2) + 0xff900000)
9798 #define ENCT_VFIFO2VD_CTL2 (0x1c27)
9799 #define P_ENCT_VFIFO2VD_CTL2 (volatile uint32_t *)((0x1c27 << 2) + 0xff900000)
9800 #define ENCT_TST_EN (0x1c28)
9801 #define P_ENCT_TST_EN (volatile uint32_t *)((0x1c28 << 2) + 0xff900000)
9802 #define ENCT_TST_MDSEL (0x1c29)
9803 #define P_ENCT_TST_MDSEL (volatile uint32_t *)((0x1c29 << 2) + 0xff900000)
9804 #define ENCT_TST_Y (0x1c2a)
9805 #define P_ENCT_TST_Y (volatile uint32_t *)((0x1c2a << 2) + 0xff900000)
9806 #define ENCT_TST_CB (0x1c2b)
9807 #define P_ENCT_TST_CB (volatile uint32_t *)((0x1c2b << 2) + 0xff900000)
9808 #define ENCT_TST_CR (0x1c2c)
9809 #define P_ENCT_TST_CR (volatile uint32_t *)((0x1c2c << 2) + 0xff900000)
9810 #define ENCT_TST_CLRBAR_STRT (0x1c2d)
9811 #define P_ENCT_TST_CLRBAR_STRT (volatile uint32_t *)((0x1c2d << 2) + 0xff900000)
9812 #define ENCT_TST_CLRBAR_WIDTH (0x1c2e)
9813 #define P_ENCT_TST_CLRBAR_WIDTH (volatile uint32_t *)((0x1c2e << 2) + 0xff900000)
9814 #define ENCT_TST_VDCNT_STSET (0x1c2f)
9815 #define P_ENCT_TST_VDCNT_STSET (volatile uint32_t *)((0x1c2f << 2) + 0xff900000)
9816 // Program video control signals from ENCP core to DVI/HDMI interface
9817 #define ENCP_DVI_HSO_BEGIN (0x1c30)
9818 #define P_ENCP_DVI_HSO_BEGIN (volatile uint32_t *)((0x1c30 << 2) + 0xff900000)
9819 #define ENCP_DVI_HSO_END (0x1c31)
9820 #define P_ENCP_DVI_HSO_END (volatile uint32_t *)((0x1c31 << 2) + 0xff900000)
9821 #define ENCP_DVI_VSO_BLINE_EVN (0x1c32)
9822 #define P_ENCP_DVI_VSO_BLINE_EVN (volatile uint32_t *)((0x1c32 << 2) + 0xff900000)
9823 #define ENCP_DVI_VSO_BLINE_ODD (0x1c33)
9824 #define P_ENCP_DVI_VSO_BLINE_ODD (volatile uint32_t *)((0x1c33 << 2) + 0xff900000)
9825 #define ENCP_DVI_VSO_ELINE_EVN (0x1c34)
9826 #define P_ENCP_DVI_VSO_ELINE_EVN (volatile uint32_t *)((0x1c34 << 2) + 0xff900000)
9827 #define ENCP_DVI_VSO_ELINE_ODD (0x1c35)
9828 #define P_ENCP_DVI_VSO_ELINE_ODD (volatile uint32_t *)((0x1c35 << 2) + 0xff900000)
9829 #define ENCP_DVI_VSO_BEGIN_EVN (0x1c36)
9830 #define P_ENCP_DVI_VSO_BEGIN_EVN (volatile uint32_t *)((0x1c36 << 2) + 0xff900000)
9831 #define ENCP_DVI_VSO_BEGIN_ODD (0x1c37)
9832 #define P_ENCP_DVI_VSO_BEGIN_ODD (volatile uint32_t *)((0x1c37 << 2) + 0xff900000)
9833 #define ENCP_DVI_VSO_END_EVN (0x1c38)
9834 #define P_ENCP_DVI_VSO_END_EVN (volatile uint32_t *)((0x1c38 << 2) + 0xff900000)
9835 #define ENCP_DVI_VSO_END_ODD (0x1c39)
9836 #define P_ENCP_DVI_VSO_END_ODD (volatile uint32_t *)((0x1c39 << 2) + 0xff900000)
9837 #define ENCP_DE_H_BEGIN (0x1c3a)
9838 #define P_ENCP_DE_H_BEGIN (volatile uint32_t *)((0x1c3a << 2) + 0xff900000)
9839 #define ENCP_DE_H_END (0x1c3b)
9840 #define P_ENCP_DE_H_END (volatile uint32_t *)((0x1c3b << 2) + 0xff900000)
9841 #define ENCP_DE_V_BEGIN_EVEN (0x1c3c)
9842 #define P_ENCP_DE_V_BEGIN_EVEN (volatile uint32_t *)((0x1c3c << 2) + 0xff900000)
9843 #define ENCP_DE_V_END_EVEN (0x1c3d)
9844 #define P_ENCP_DE_V_END_EVEN (volatile uint32_t *)((0x1c3d << 2) + 0xff900000)
9845 #define ENCP_DE_V_BEGIN_ODD (0x1c3e)
9846 #define P_ENCP_DE_V_BEGIN_ODD (volatile uint32_t *)((0x1c3e << 2) + 0xff900000)
9847 #define ENCP_DE_V_END_ODD (0x1c3f)
9848 #define P_ENCP_DE_V_END_ODD (volatile uint32_t *)((0x1c3f << 2) + 0xff900000)
9849 // Bit 15:11 - sync length
9850 // Bit 10:0 - sync start line
9851 #define ENCI_SYNC_LINE_LENGTH (0x1c40)
9852 #define P_ENCI_SYNC_LINE_LENGTH (volatile uint32_t *)((0x1c40 << 2) + 0xff900000)
9853 // Bit 15 - sync_pulse_enable
9854 // Bit 12:0 - sync start pixel
9855 #define ENCI_SYNC_PIXEL_EN (0x1c41)
9856 #define P_ENCI_SYNC_PIXEL_EN (volatile uint32_t *)((0x1c41 << 2) + 0xff900000)
9857 // Bit 15 - enci_sync_enable
9858 // Bit 14 - encp_sync_enable
9859 // Bit 13 - enct_sync_enable
9860 // Bit 12 - short_fussy_sync
9861 // Bit 11 - fussy_sync_enable
9862 // Bit 10:0 - sync target line
9863 #define ENCI_SYNC_TO_LINE_EN (0x1c42)
9864 #define P_ENCI_SYNC_TO_LINE_EN (volatile uint32_t *)((0x1c42 << 2) + 0xff900000)
9865 // Bit 12:0 - sync target pixel
9866 #define ENCI_SYNC_TO_PIXEL (0x1c43)
9867 #define P_ENCI_SYNC_TO_PIXEL (volatile uint32_t *)((0x1c43 << 2) + 0xff900000)
9868 // Bit 15:11 - sync length
9869 // Bit 10:0 - sync start line
9870 #define ENCP_SYNC_LINE_LENGTH (0x1c44)
9871 #define P_ENCP_SYNC_LINE_LENGTH (volatile uint32_t *)((0x1c44 << 2) + 0xff900000)
9872 // Bit 15 - sync_pulse_enable
9873 // Bit 12:0 - sync start pixel
9874 #define ENCP_SYNC_PIXEL_EN (0x1c45)
9875 #define P_ENCP_SYNC_PIXEL_EN (volatile uint32_t *)((0x1c45 << 2) + 0xff900000)
9876 // Bit 15 - enci_sync_enable
9877 // Bit 14 - encp_sync_enable
9878 // Bit 13 - enct_sync_enable
9879 // Bit 12 - short_fussy_sync
9880 // Bit 11 - fussy_sync_enable
9881 // Bit 10:0 - sync target line
9882 #define ENCP_SYNC_TO_LINE_EN (0x1c46)
9883 #define P_ENCP_SYNC_TO_LINE_EN (volatile uint32_t *)((0x1c46 << 2) + 0xff900000)
9884 // Bit 12:0 - sync target pixel
9885 #define ENCP_SYNC_TO_PIXEL (0x1c47)
9886 #define P_ENCP_SYNC_TO_PIXEL (volatile uint32_t *)((0x1c47 << 2) + 0xff900000)
9887 // Bit 15:11 - sync length
9888 // Bit 10:0 - sync start line
9889 #define ENCT_SYNC_LINE_LENGTH (0x1c48)
9890 #define P_ENCT_SYNC_LINE_LENGTH (volatile uint32_t *)((0x1c48 << 2) + 0xff900000)
9891 // Bit 15 - sync_pulse_enable
9892 // Bit 12:0 - sync start pixel
9893 #define ENCT_SYNC_PIXEL_EN (0x1c49)
9894 #define P_ENCT_SYNC_PIXEL_EN (volatile uint32_t *)((0x1c49 << 2) + 0xff900000)
9895 // Bit 15 - enci_sync_enable
9896 // Bit 14 - encp_sync_enable
9897 // Bit 13 - enct_sync_enable
9898 // Bit 12 - short_fussy_sync
9899 // Bit 11 - fussy_sync_enable
9900 // Bit 10:0 - sync target line
9901 #define ENCT_SYNC_TO_LINE_EN (0x1c4a)
9902 #define P_ENCT_SYNC_TO_LINE_EN (volatile uint32_t *)((0x1c4a << 2) + 0xff900000)
9903 // Bit 12:0 - sync target pixel
9904 #define ENCT_SYNC_TO_PIXEL (0x1c4b)
9905 #define P_ENCT_SYNC_TO_PIXEL (volatile uint32_t *)((0x1c4b << 2) + 0xff900000)
9906 // Bit 15:11 - sync length
9907 // Bit 10:0 - sync start line
9908 #define ENCL_SYNC_LINE_LENGTH (0x1c4c)
9909 #define P_ENCL_SYNC_LINE_LENGTH (volatile uint32_t *)((0x1c4c << 2) + 0xff900000)
9910 // Bit 15 - sync_pulse_enable
9911 // Bit 12:0 - sync start pixel
9912 #define ENCL_SYNC_PIXEL_EN (0x1c4d)
9913 #define P_ENCL_SYNC_PIXEL_EN (volatile uint32_t *)((0x1c4d << 2) + 0xff900000)
9914 // Bit 15 - enci_sync_enable
9915 // Bit 14 - encp_sync_enable
9916 // Bit 13 - enct_sync_enable
9917 // Bit 12 - short_fussy_sync
9918 // Bit 11 - fussy_sync_enable
9919 // Bit 10:0 - sync target line
9920 #define ENCL_SYNC_TO_LINE_EN (0x1c4e)
9921 #define P_ENCL_SYNC_TO_LINE_EN (volatile uint32_t *)((0x1c4e << 2) + 0xff900000)
9922 // Bit 12:0 - sync target pixel
9923 #define ENCL_SYNC_TO_PIXEL (0x1c4f)
9924 #define P_ENCL_SYNC_TO_PIXEL (volatile uint32_t *)((0x1c4f << 2) + 0xff900000)
9925 // bit 3 cfg_encp_lcd_scaler_bypass. 1=Do not scale LCD input data;
9926 // 0=Scale LCD input data to y [16*4,235*4], c [16*4,240*4].
9927 // bit 2 cfg_encp_vadj_scaler_bypass. 1=Do not scale data to enc480p_vadj;
9928 // 0=Scale enc480p_vadj input data to y [16*4,235*4], c [16*4,240*4].
9929 // bit 1 cfg_vfifo2vd_out_scaler_bypass. 1=Do not scale vfifo2vd's output vdata;
9930 // 0=Scale vfifo2vd's output vdata to y [16,235], c [16,240].
9931 // bit 0 cfg_vfifo_din_full_range. 1=Data from viu fifo is full range [0,1023];
9932 // 0=Data from viu fifo is y [16*4,235*4], c [16*4,240*4].
9933 #define ENCP_VFIFO2VD_CTL2 (0x1c50)
9934 #define P_ENCP_VFIFO2VD_CTL2 (volatile uint32_t *)((0x1c50 << 2) + 0xff900000)
9935 // bit 15:1 Reserved.
9936 // bit 0 cfg_int_dvi_sel_rgb. Applicable for using on-chip hdmi tx module only. This bit controls correct bit-mapping from
9937 // Venc to hdmi_tx depending on whether YCbCr or RGB mode.
9938 // 1=Map data bit from Venc to hdmi_tx for RGB mode;
9939 // 0=Default. Map data bit from Venc to hdmi_tx for YCbCr mode.
9940 #define VENC_DVI_SETTING_MORE (0x1c51)
9941 #define P_VENC_DVI_SETTING_MORE (volatile uint32_t *)((0x1c51 << 2) + 0xff900000)
9942 #define VENC_VDAC_DAC4_FILT_CTRL0 (0x1c54)
9943 #define P_VENC_VDAC_DAC4_FILT_CTRL0 (volatile uint32_t *)((0x1c54 << 2) + 0xff900000)
9944 #define VENC_VDAC_DAC4_FILT_CTRL1 (0x1c55)
9945 #define P_VENC_VDAC_DAC4_FILT_CTRL1 (volatile uint32_t *)((0x1c55 << 2) + 0xff900000)
9946 #define VENC_VDAC_DAC5_FILT_CTRL0 (0x1c56)
9947 #define P_VENC_VDAC_DAC5_FILT_CTRL0 (volatile uint32_t *)((0x1c56 << 2) + 0xff900000)
9948 #define VENC_VDAC_DAC5_FILT_CTRL1 (0x1c57)
9949 #define P_VENC_VDAC_DAC5_FILT_CTRL1 (volatile uint32_t *)((0x1c57 << 2) + 0xff900000)
9950 //Bit 0 filter_en
9951 #define VENC_VDAC_DAC0_FILT_CTRL0 (0x1c58)
9952 #define P_VENC_VDAC_DAC0_FILT_CTRL0 (volatile uint32_t *)((0x1c58 << 2) + 0xff900000)
9953 //dout = ((din + din_d2) * coef1 + (din_d1 * coef0) + 32) >> 6
9954 //Bit 15:8, coef1,
9955 //Bit 7:0, coef0,
9956 #define VENC_VDAC_DAC0_FILT_CTRL1 (0x1c59)
9957 #define P_VENC_VDAC_DAC0_FILT_CTRL1 (volatile uint32_t *)((0x1c59 << 2) + 0xff900000)
9958 //Bit 0 filter_en
9959 #define VENC_VDAC_DAC1_FILT_CTRL0 (0x1c5a)
9960 #define P_VENC_VDAC_DAC1_FILT_CTRL0 (volatile uint32_t *)((0x1c5a << 2) + 0xff900000)
9961 //dout = ((din + din_d2) * coef1 + (din_d1 * coef0) + 32) >> 6
9962 //Bit 15:8, coef1,
9963 //Bit 7:0, coef0,
9964 #define VENC_VDAC_DAC1_FILT_CTRL1 (0x1c5b)
9965 #define P_VENC_VDAC_DAC1_FILT_CTRL1 (volatile uint32_t *)((0x1c5b << 2) + 0xff900000)
9966 //Bit 0 filter_en
9967 #define VENC_VDAC_DAC2_FILT_CTRL0 (0x1c5c)
9968 #define P_VENC_VDAC_DAC2_FILT_CTRL0 (volatile uint32_t *)((0x1c5c << 2) + 0xff900000)
9969 //dout = ((din + din_d2) * coef1 + (din_d1 * coef0) + 32) >> 6
9970 //Bit 15:8, coef1,
9971 //Bit 7:0, coef0,
9972 #define VENC_VDAC_DAC2_FILT_CTRL1 (0x1c5d)
9973 #define P_VENC_VDAC_DAC2_FILT_CTRL1 (volatile uint32_t *)((0x1c5d << 2) + 0xff900000)
9974 //Bit 0 filter_en
9975 #define VENC_VDAC_DAC3_FILT_CTRL0 (0x1c5e)
9976 #define P_VENC_VDAC_DAC3_FILT_CTRL0 (volatile uint32_t *)((0x1c5e << 2) + 0xff900000)
9977 //dout = ((din + din_d2) * coef1 + (din_d1 * coef0) + 32) >> 6
9978 //Bit 15:8, coef1,
9979 //Bit 7:0, coef0,
9980 #define VENC_VDAC_DAC3_FILT_CTRL1 (0x1c5f)
9981 #define P_VENC_VDAC_DAC3_FILT_CTRL1 (volatile uint32_t *)((0x1c5f << 2) + 0xff900000)
9982 //===========================================================================
9983 // ENCT registers
9984 #define ENCT_VIDEO_EN (0x1c60)
9985 #define P_ENCT_VIDEO_EN (volatile uint32_t *)((0x1c60 << 2) + 0xff900000)
9986 #define ENCT_VIDEO_Y_SCL (0x1c61)
9987 #define P_ENCT_VIDEO_Y_SCL (volatile uint32_t *)((0x1c61 << 2) + 0xff900000)
9988 #define ENCT_VIDEO_PB_SCL (0x1c62)
9989 #define P_ENCT_VIDEO_PB_SCL (volatile uint32_t *)((0x1c62 << 2) + 0xff900000)
9990 #define ENCT_VIDEO_PR_SCL (0x1c63)
9991 #define P_ENCT_VIDEO_PR_SCL (volatile uint32_t *)((0x1c63 << 2) + 0xff900000)
9992 #define ENCT_VIDEO_Y_OFFST (0x1c64)
9993 #define P_ENCT_VIDEO_Y_OFFST (volatile uint32_t *)((0x1c64 << 2) + 0xff900000)
9994 #define ENCT_VIDEO_PB_OFFST (0x1c65)
9995 #define P_ENCT_VIDEO_PB_OFFST (volatile uint32_t *)((0x1c65 << 2) + 0xff900000)
9996 #define ENCT_VIDEO_PR_OFFST (0x1c66)
9997 #define P_ENCT_VIDEO_PR_OFFST (volatile uint32_t *)((0x1c66 << 2) + 0xff900000)
9998 //----- Video mode
9999 #define ENCT_VIDEO_MODE (0x1c67)
10000 #define P_ENCT_VIDEO_MODE (volatile uint32_t *)((0x1c67 << 2) + 0xff900000)
10001 #define ENCT_VIDEO_MODE_ADV (0x1c68)
10002 #define P_ENCT_VIDEO_MODE_ADV (volatile uint32_t *)((0x1c68 << 2) + 0xff900000)
10003 //--------------- Debug pins
10004 #define ENCT_DBG_PX_RST (0x1c69)
10005 #define P_ENCT_DBG_PX_RST (volatile uint32_t *)((0x1c69 << 2) + 0xff900000)
10006 #define ENCT_DBG_LN_RST (0x1c6a)
10007 #define P_ENCT_DBG_LN_RST (volatile uint32_t *)((0x1c6a << 2) + 0xff900000)
10008 #define ENCT_DBG_PX_INT (0x1c6b)
10009 #define P_ENCT_DBG_PX_INT (volatile uint32_t *)((0x1c6b << 2) + 0xff900000)
10010 #define ENCT_DBG_LN_INT (0x1c6c)
10011 #define P_ENCT_DBG_LN_INT (volatile uint32_t *)((0x1c6c << 2) + 0xff900000)
10012 //----------- Video Advanced setting
10013 #define ENCT_VIDEO_YFP1_HTIME (0x1c6d)
10014 #define P_ENCT_VIDEO_YFP1_HTIME (volatile uint32_t *)((0x1c6d << 2) + 0xff900000)
10015 #define ENCT_VIDEO_YFP2_HTIME (0x1c6e)
10016 #define P_ENCT_VIDEO_YFP2_HTIME (volatile uint32_t *)((0x1c6e << 2) + 0xff900000)
10017 #define ENCT_VIDEO_YC_DLY (0x1c6f)
10018 #define P_ENCT_VIDEO_YC_DLY (volatile uint32_t *)((0x1c6f << 2) + 0xff900000)
10019 #define ENCT_VIDEO_MAX_PXCNT (0x1c70)
10020 #define P_ENCT_VIDEO_MAX_PXCNT (volatile uint32_t *)((0x1c70 << 2) + 0xff900000)
10021 #define ENCT_VIDEO_HAVON_END (0x1c71)
10022 #define P_ENCT_VIDEO_HAVON_END (volatile uint32_t *)((0x1c71 << 2) + 0xff900000)
10023 #define ENCT_VIDEO_HAVON_BEGIN (0x1c72)
10024 #define P_ENCT_VIDEO_HAVON_BEGIN (volatile uint32_t *)((0x1c72 << 2) + 0xff900000)
10025 #define ENCT_VIDEO_VAVON_ELINE (0x1c73)
10026 #define P_ENCT_VIDEO_VAVON_ELINE (volatile uint32_t *)((0x1c73 << 2) + 0xff900000)
10027 #define ENCT_VIDEO_VAVON_BLINE (0x1c74)
10028 #define P_ENCT_VIDEO_VAVON_BLINE (volatile uint32_t *)((0x1c74 << 2) + 0xff900000)
10029 #define ENCT_VIDEO_HSO_BEGIN (0x1c75)
10030 #define P_ENCT_VIDEO_HSO_BEGIN (volatile uint32_t *)((0x1c75 << 2) + 0xff900000)
10031 #define ENCT_VIDEO_HSO_END (0x1c76)
10032 #define P_ENCT_VIDEO_HSO_END (volatile uint32_t *)((0x1c76 << 2) + 0xff900000)
10033 #define ENCT_VIDEO_VSO_BEGIN (0x1c77)
10034 #define P_ENCT_VIDEO_VSO_BEGIN (volatile uint32_t *)((0x1c77 << 2) + 0xff900000)
10035 #define ENCT_VIDEO_VSO_END (0x1c78)
10036 #define P_ENCT_VIDEO_VSO_END (volatile uint32_t *)((0x1c78 << 2) + 0xff900000)
10037 #define ENCT_VIDEO_VSO_BLINE (0x1c79)
10038 #define P_ENCT_VIDEO_VSO_BLINE (volatile uint32_t *)((0x1c79 << 2) + 0xff900000)
10039 #define ENCT_VIDEO_VSO_ELINE (0x1c7a)
10040 #define P_ENCT_VIDEO_VSO_ELINE (volatile uint32_t *)((0x1c7a << 2) + 0xff900000)
10041 #define ENCT_VIDEO_MAX_LNCNT (0x1c7b)
10042 #define P_ENCT_VIDEO_MAX_LNCNT (volatile uint32_t *)((0x1c7b << 2) + 0xff900000)
10043 #define ENCT_VIDEO_BLANKY_VAL (0x1c7c)
10044 #define P_ENCT_VIDEO_BLANKY_VAL (volatile uint32_t *)((0x1c7c << 2) + 0xff900000)
10045 #define ENCT_VIDEO_BLANKPB_VAL (0x1c7d)
10046 #define P_ENCT_VIDEO_BLANKPB_VAL (volatile uint32_t *)((0x1c7d << 2) + 0xff900000)
10047 #define ENCT_VIDEO_BLANKPR_VAL (0x1c7e)
10048 #define P_ENCT_VIDEO_BLANKPR_VAL (volatile uint32_t *)((0x1c7e << 2) + 0xff900000)
10049 #define ENCT_VIDEO_HOFFST (0x1c7f)
10050 #define P_ENCT_VIDEO_HOFFST (volatile uint32_t *)((0x1c7f << 2) + 0xff900000)
10051 #define ENCT_VIDEO_VOFFST (0x1c80)
10052 #define P_ENCT_VIDEO_VOFFST (volatile uint32_t *)((0x1c80 << 2) + 0xff900000)
10053 #define ENCT_VIDEO_RGB_CTRL (0x1c81)
10054 #define P_ENCT_VIDEO_RGB_CTRL (volatile uint32_t *)((0x1c81 << 2) + 0xff900000)
10055 #define ENCT_VIDEO_FILT_CTRL (0x1c82)
10056 #define P_ENCT_VIDEO_FILT_CTRL (volatile uint32_t *)((0x1c82 << 2) + 0xff900000)
10057 #define ENCT_VIDEO_OFLD_VPEQ_OFST (0x1c83)
10058 #define P_ENCT_VIDEO_OFLD_VPEQ_OFST (volatile uint32_t *)((0x1c83 << 2) + 0xff900000)
10059 #define ENCT_VIDEO_OFLD_VOAV_OFST (0x1c84)
10060 #define P_ENCT_VIDEO_OFLD_VOAV_OFST (volatile uint32_t *)((0x1c84 << 2) + 0xff900000)
10061 #define ENCT_VIDEO_MATRIX_CB (0x1c85)
10062 #define P_ENCT_VIDEO_MATRIX_CB (volatile uint32_t *)((0x1c85 << 2) + 0xff900000)
10063 #define ENCT_VIDEO_MATRIX_CR (0x1c86)
10064 #define P_ENCT_VIDEO_MATRIX_CR (volatile uint32_t *)((0x1c86 << 2) + 0xff900000)
10065 #define ENCT_VIDEO_RGBIN_CTRL (0x1c87)
10066 #define P_ENCT_VIDEO_RGBIN_CTRL (volatile uint32_t *)((0x1c87 << 2) + 0xff900000)
10067 #define ENCT_MAX_LINE_SWITCH_POINT (0x1c88)
10068 #define P_ENCT_MAX_LINE_SWITCH_POINT (volatile uint32_t *)((0x1c88 << 2) + 0xff900000)
10069 #define ENCT_DACSEL_0 (0x1c89)
10070 #define P_ENCT_DACSEL_0 (volatile uint32_t *)((0x1c89 << 2) + 0xff900000)
10071 #define ENCT_DACSEL_1 (0x1c8a)
10072 #define P_ENCT_DACSEL_1 (volatile uint32_t *)((0x1c8a << 2) + 0xff900000)
10073 //===========================================================================
10074 // For ENCL
10075 //===========================================================================
10076 // bit 15:8 -- vfifo2vd_vd_sel
10077 // bit 7 -- vfifo2vd_drop
10078 // bit 6:1 -- vfifo2vd_delay
10079 // bit 0 -- vfifo2vd_en
10080 #define ENCL_VFIFO2VD_CTL (0x1c90)
10081 #define P_ENCL_VFIFO2VD_CTL (volatile uint32_t *)((0x1c90 << 2) + 0xff900000)
10082 // bit 12:0 -- vfifo2vd_pixel_start
10083 #define ENCL_VFIFO2VD_PIXEL_START (0x1c91)
10084 #define P_ENCL_VFIFO2VD_PIXEL_START (volatile uint32_t *)((0x1c91 << 2) + 0xff900000)
10085 // bit 12:00 -- vfifo2vd_pixel_end
10086 #define ENCL_VFIFO2VD_PIXEL_END (0x1c92)
10087 #define P_ENCL_VFIFO2VD_PIXEL_END (volatile uint32_t *)((0x1c92 << 2) + 0xff900000)
10088 // bit 10:0 -- vfifo2vd_line_top_start
10089 #define ENCL_VFIFO2VD_LINE_TOP_START (0x1c93)
10090 #define P_ENCL_VFIFO2VD_LINE_TOP_START (volatile uint32_t *)((0x1c93 << 2) + 0xff900000)
10091 // bit 10:00 -- vfifo2vd_line_top_end
10092 #define ENCL_VFIFO2VD_LINE_TOP_END (0x1c94)
10093 #define P_ENCL_VFIFO2VD_LINE_TOP_END (volatile uint32_t *)((0x1c94 << 2) + 0xff900000)
10094 // bit 10:00 -- vfifo2vd_line_bot_start
10095 #define ENCL_VFIFO2VD_LINE_BOT_START (0x1c95)
10096 #define P_ENCL_VFIFO2VD_LINE_BOT_START (volatile uint32_t *)((0x1c95 << 2) + 0xff900000)
10097 // bit 10:00 -- vfifo2vd_line_bot_end
10098 #define ENCL_VFIFO2VD_LINE_BOT_END (0x1c96)
10099 #define P_ENCL_VFIFO2VD_LINE_BOT_END (volatile uint32_t *)((0x1c96 << 2) + 0xff900000)
10100 #define ENCL_VFIFO2VD_CTL2 (0x1c97)
10101 #define P_ENCL_VFIFO2VD_CTL2 (volatile uint32_t *)((0x1c97 << 2) + 0xff900000)
10102 #define ENCL_TST_EN (0x1c98)
10103 #define P_ENCL_TST_EN (volatile uint32_t *)((0x1c98 << 2) + 0xff900000)
10104 #define ENCL_TST_MDSEL (0x1c99)
10105 #define P_ENCL_TST_MDSEL (volatile uint32_t *)((0x1c99 << 2) + 0xff900000)
10106 #define ENCL_TST_Y (0x1c9a)
10107 #define P_ENCL_TST_Y (volatile uint32_t *)((0x1c9a << 2) + 0xff900000)
10108 #define ENCL_TST_CB (0x1c9b)
10109 #define P_ENCL_TST_CB (volatile uint32_t *)((0x1c9b << 2) + 0xff900000)
10110 #define ENCL_TST_CR (0x1c9c)
10111 #define P_ENCL_TST_CR (volatile uint32_t *)((0x1c9c << 2) + 0xff900000)
10112 #define ENCL_TST_CLRBAR_STRT (0x1c9d)
10113 #define P_ENCL_TST_CLRBAR_STRT (volatile uint32_t *)((0x1c9d << 2) + 0xff900000)
10114 #define ENCL_TST_CLRBAR_WIDTH (0x1c9e)
10115 #define P_ENCL_TST_CLRBAR_WIDTH (volatile uint32_t *)((0x1c9e << 2) + 0xff900000)
10116 #define ENCL_TST_VDCNT_STSET (0x1c9f)
10117 #define P_ENCL_TST_VDCNT_STSET (volatile uint32_t *)((0x1c9f << 2) + 0xff900000)
10118 //===========================================================================
10119 // ENCL registers
10120 #define ENCL_VIDEO_EN (0x1ca0)
10121 #define P_ENCL_VIDEO_EN (volatile uint32_t *)((0x1ca0 << 2) + 0xff900000)
10122 #define ENCL_VIDEO_Y_SCL (0x1ca1)
10123 #define P_ENCL_VIDEO_Y_SCL (volatile uint32_t *)((0x1ca1 << 2) + 0xff900000)
10124 #define ENCL_VIDEO_PB_SCL (0x1ca2)
10125 #define P_ENCL_VIDEO_PB_SCL (volatile uint32_t *)((0x1ca2 << 2) + 0xff900000)
10126 #define ENCL_VIDEO_PR_SCL (0x1ca3)
10127 #define P_ENCL_VIDEO_PR_SCL (volatile uint32_t *)((0x1ca3 << 2) + 0xff900000)
10128 #define ENCL_VIDEO_Y_OFFST (0x1ca4)
10129 #define P_ENCL_VIDEO_Y_OFFST (volatile uint32_t *)((0x1ca4 << 2) + 0xff900000)
10130 #define ENCL_VIDEO_PB_OFFST (0x1ca5)
10131 #define P_ENCL_VIDEO_PB_OFFST (volatile uint32_t *)((0x1ca5 << 2) + 0xff900000)
10132 #define ENCL_VIDEO_PR_OFFST (0x1ca6)
10133 #define P_ENCL_VIDEO_PR_OFFST (volatile uint32_t *)((0x1ca6 << 2) + 0xff900000)
10134 //----- Video mode
10135 #define ENCL_VIDEO_MODE (0x1ca7)
10136 #define P_ENCL_VIDEO_MODE (volatile uint32_t *)((0x1ca7 << 2) + 0xff900000)
10137 #define ENCL_VIDEO_MODE_ADV (0x1ca8)
10138 #define P_ENCL_VIDEO_MODE_ADV (volatile uint32_t *)((0x1ca8 << 2) + 0xff900000)
10139 //--------------- Debug pins
10140 #define ENCL_DBG_PX_RST (0x1ca9)
10141 #define P_ENCL_DBG_PX_RST (volatile uint32_t *)((0x1ca9 << 2) + 0xff900000)
10142 #define ENCL_DBG_LN_RST (0x1caa)
10143 #define P_ENCL_DBG_LN_RST (volatile uint32_t *)((0x1caa << 2) + 0xff900000)
10144 #define ENCL_DBG_PX_INT (0x1cab)
10145 #define P_ENCL_DBG_PX_INT (volatile uint32_t *)((0x1cab << 2) + 0xff900000)
10146 #define ENCL_DBG_LN_INT (0x1cac)
10147 #define P_ENCL_DBG_LN_INT (volatile uint32_t *)((0x1cac << 2) + 0xff900000)
10148 //----------- Video Advanced setting
10149 #define ENCL_VIDEO_YFP1_HTIME (0x1cad)
10150 #define P_ENCL_VIDEO_YFP1_HTIME (volatile uint32_t *)((0x1cad << 2) + 0xff900000)
10151 #define ENCL_VIDEO_YFP2_HTIME (0x1cae)
10152 #define P_ENCL_VIDEO_YFP2_HTIME (volatile uint32_t *)((0x1cae << 2) + 0xff900000)
10153 #define ENCL_VIDEO_YC_DLY (0x1caf)
10154 #define P_ENCL_VIDEO_YC_DLY (volatile uint32_t *)((0x1caf << 2) + 0xff900000)
10155 #define ENCL_VIDEO_MAX_PXCNT (0x1cb0)
10156 #define P_ENCL_VIDEO_MAX_PXCNT (volatile uint32_t *)((0x1cb0 << 2) + 0xff900000)
10157 #define ENCL_VIDEO_HAVON_END (0x1cb1)
10158 #define P_ENCL_VIDEO_HAVON_END (volatile uint32_t *)((0x1cb1 << 2) + 0xff900000)
10159 #define ENCL_VIDEO_HAVON_BEGIN (0x1cb2)
10160 #define P_ENCL_VIDEO_HAVON_BEGIN (volatile uint32_t *)((0x1cb2 << 2) + 0xff900000)
10161 #define ENCL_VIDEO_VAVON_ELINE (0x1cb3)
10162 #define P_ENCL_VIDEO_VAVON_ELINE (volatile uint32_t *)((0x1cb3 << 2) + 0xff900000)
10163 #define ENCL_VIDEO_VAVON_BLINE (0x1cb4)
10164 #define P_ENCL_VIDEO_VAVON_BLINE (volatile uint32_t *)((0x1cb4 << 2) + 0xff900000)
10165 #define ENCL_VIDEO_HSO_BEGIN (0x1cb5)
10166 #define P_ENCL_VIDEO_HSO_BEGIN (volatile uint32_t *)((0x1cb5 << 2) + 0xff900000)
10167 #define ENCL_VIDEO_HSO_END (0x1cb6)
10168 #define P_ENCL_VIDEO_HSO_END (volatile uint32_t *)((0x1cb6 << 2) + 0xff900000)
10169 #define ENCL_VIDEO_VSO_BEGIN (0x1cb7)
10170 #define P_ENCL_VIDEO_VSO_BEGIN (volatile uint32_t *)((0x1cb7 << 2) + 0xff900000)
10171 #define ENCL_VIDEO_VSO_END (0x1cb8)
10172 #define P_ENCL_VIDEO_VSO_END (volatile uint32_t *)((0x1cb8 << 2) + 0xff900000)
10173 #define ENCL_VIDEO_VSO_BLINE (0x1cb9)
10174 #define P_ENCL_VIDEO_VSO_BLINE (volatile uint32_t *)((0x1cb9 << 2) + 0xff900000)
10175 #define ENCL_VIDEO_VSO_ELINE (0x1cba)
10176 #define P_ENCL_VIDEO_VSO_ELINE (volatile uint32_t *)((0x1cba << 2) + 0xff900000)
10177 #define ENCL_VIDEO_MAX_LNCNT (0x1cbb)
10178 #define P_ENCL_VIDEO_MAX_LNCNT (volatile uint32_t *)((0x1cbb << 2) + 0xff900000)
10179 #define ENCL_VIDEO_BLANKY_VAL (0x1cbc)
10180 #define P_ENCL_VIDEO_BLANKY_VAL (volatile uint32_t *)((0x1cbc << 2) + 0xff900000)
10181 #define ENCL_VIDEO_BLANKPB_VAL (0x1cbd)
10182 #define P_ENCL_VIDEO_BLANKPB_VAL (volatile uint32_t *)((0x1cbd << 2) + 0xff900000)
10183 #define ENCL_VIDEO_BLANKPR_VAL (0x1cbe)
10184 #define P_ENCL_VIDEO_BLANKPR_VAL (volatile uint32_t *)((0x1cbe << 2) + 0xff900000)
10185 #define ENCL_VIDEO_HOFFST (0x1cbf)
10186 #define P_ENCL_VIDEO_HOFFST (volatile uint32_t *)((0x1cbf << 2) + 0xff900000)
10187 #define ENCL_VIDEO_VOFFST (0x1cc0)
10188 #define P_ENCL_VIDEO_VOFFST (volatile uint32_t *)((0x1cc0 << 2) + 0xff900000)
10189 #define ENCL_VIDEO_RGB_CTRL (0x1cc1)
10190 #define P_ENCL_VIDEO_RGB_CTRL (volatile uint32_t *)((0x1cc1 << 2) + 0xff900000)
10191 #define ENCL_VIDEO_FILT_CTRL (0x1cc2)
10192 #define P_ENCL_VIDEO_FILT_CTRL (volatile uint32_t *)((0x1cc2 << 2) + 0xff900000)
10193 #define ENCL_VIDEO_OFLD_VPEQ_OFST (0x1cc3)
10194 #define P_ENCL_VIDEO_OFLD_VPEQ_OFST (volatile uint32_t *)((0x1cc3 << 2) + 0xff900000)
10195 #define ENCL_VIDEO_OFLD_VOAV_OFST (0x1cc4)
10196 #define P_ENCL_VIDEO_OFLD_VOAV_OFST (volatile uint32_t *)((0x1cc4 << 2) + 0xff900000)
10197 #define ENCL_VIDEO_MATRIX_CB (0x1cc5)
10198 #define P_ENCL_VIDEO_MATRIX_CB (volatile uint32_t *)((0x1cc5 << 2) + 0xff900000)
10199 #define ENCL_VIDEO_MATRIX_CR (0x1cc6)
10200 #define P_ENCL_VIDEO_MATRIX_CR (volatile uint32_t *)((0x1cc6 << 2) + 0xff900000)
10201 #define ENCL_VIDEO_RGBIN_CTRL (0x1cc7)
10202 #define P_ENCL_VIDEO_RGBIN_CTRL (volatile uint32_t *)((0x1cc7 << 2) + 0xff900000)
10203 #define ENCL_MAX_LINE_SWITCH_POINT (0x1cc8)
10204 #define P_ENCL_MAX_LINE_SWITCH_POINT (volatile uint32_t *)((0x1cc8 << 2) + 0xff900000)
10205 #define ENCL_DACSEL_0 (0x1cc9)
10206 #define P_ENCL_DACSEL_0 (volatile uint32_t *)((0x1cc9 << 2) + 0xff900000)
10207 #define ENCL_DACSEL_1 (0x1cca)
10208 #define P_ENCL_DACSEL_1 (volatile uint32_t *)((0x1cca << 2) + 0xff900000)
10209 //
10210 // Closing file: venc2_regs.h
10211 //
10212 //`define VPP_VCBUS_BASE 8'h1d
10213 //
10214 // Reading file: vpp_regs.h
10215 //
10216 // synopsys translate_off
10217 // synopsys translate_on
10218 // -----------------------------------------------
10219 // CBUS_BASE: VPP_VCBUS_BASE = 0x1d
10220 // -----------------------------------------------
10221 //===========================================================================
10222 // Video postprocesing Registers
10223 //===========================================================================
10224 // dummy data used in the VPP preblend and scaler
10225 // Bit 23:16 Y
10226 // Bit 15:8 CB
10227 // Bit 7:0 CR
10228 #define VPP_DUMMY_DATA (0x1d00)
10229 #define P_VPP_DUMMY_DATA (volatile uint32_t *)((0x1d00 << 2) + 0xff900000)
10230 //input line length used in VPP
10231 #define VPP_LINE_IN_LENGTH (0x1d01)
10232 #define P_VPP_LINE_IN_LENGTH (volatile uint32_t *)((0x1d01 << 2) + 0xff900000)
10233 //input Picture height used in VPP
10234 #define VPP_PIC_IN_HEIGHT (0x1d02)
10235 #define P_VPP_PIC_IN_HEIGHT (volatile uint32_t *)((0x1d02 << 2) + 0xff900000)
10236 //Because there are many coefficients used in the vertical filter and horizontal filters,
10237 //indirect access the coefficients of vertical filter and horizontal filter is used.
10238 //For vertical filter, there are 33x4 coefficients
10239 //For horizontal filter, there are 33x4 coefficients
10240 //Bit 15 index increment, if bit9 == 1 then (0: index increase 1, 1: index increase 2) else (index increase 2)
10241 //Bit 14 1: read coef through cbus enable, just for debug purpose in case when we wanna check the coef in ram in correct or not
10242 //Bit 13 if true, vertical separated coef enable
10243 //Bit 9 if true, use 9bit resolution coef, other use 8bit resolution coef
10244 //Bit 8:7 type of index, 00: vertical coef, 01: vertical chroma coef: 10: horizontal coef, 11: resevered
10245 //Bit 6:0 coef index
10246 #define VPP_SCALE_COEF_IDX (0x1d03)
10247 #define P_VPP_SCALE_COEF_IDX (volatile uint32_t *)((0x1d03 << 2) + 0xff900000)
10248 //coefficients for vertical filter and horizontal filter
10249 #define VPP_SCALE_COEF (0x1d04)
10250 #define P_VPP_SCALE_COEF (volatile uint32_t *)((0x1d04 << 2) + 0xff900000)
10251 //these following registers are the absolute line address pointer for output divided screen
10252 //The output divided screen is shown in the following:
10253 //
10254 // -------------------------- <------ line zero
10255 // .
10256 // .
10257 // . region0 <---------- nonlinear region or nonscaling region
10258 // .
10259 // ---------------------------
10260 // --------------------------- <------ region1_startp
10261 // .
10262 // . region1 <---------- nonlinear region
10263 // .
10264 // .
10265 // ---------------------------
10266 // --------------------------- <------ region2_startp
10267 // .
10268 // . region2 <---------- linear region
10269 // .
10270 // .
10271 // ---------------------------
10272 // --------------------------- <------ region3_startp
10273 // .
10274 // . region3 <---------- nonlinear region
10275 // .
10276 // .
10277 // ---------------------------
10278 // --------------------------- <------ region4_startp
10279 // .
10280 // . region4 <---------- nonlinear region or nonoscaling region
10281 // .
10282 // .
10283 // --------------------------- <------ region4_endp
10284 //Bit 28:16 region1 startp
10285 //Bit 12:0 region2 startp
10286 #define VPP_VSC_REGION12_STARTP (0x1d05)
10287 #define P_VPP_VSC_REGION12_STARTP (volatile uint32_t *)((0x1d05 << 2) + 0xff900000)
10288 //Bit 28:16 region3 startp
10289 //Bit 12:0 region4 startp
10290 #define VPP_VSC_REGION34_STARTP (0x1d06)
10291 #define P_VPP_VSC_REGION34_STARTP (volatile uint32_t *)((0x1d06 << 2) + 0xff900000)
10292 #define VPP_VSC_REGION4_ENDP (0x1d07)
10293 #define P_VPP_VSC_REGION4_ENDP (volatile uint32_t *)((0x1d07 << 2) + 0xff900000)
10294 //vertical start phase step, (source/dest)*(2^24)
10295 //Bit 27:24 integer part
10296 //Bit 23:0 fraction part
10297 #define VPP_VSC_START_PHASE_STEP (0x1d08)
10298 #define P_VPP_VSC_START_PHASE_STEP (volatile uint32_t *)((0x1d08 << 2) + 0xff900000)
10299 //vertical scaler region0 phase slope, Bit24 signed bit
10300 #define VPP_VSC_REGION0_PHASE_SLOPE (0x1d09)
10301 #define P_VPP_VSC_REGION0_PHASE_SLOPE (volatile uint32_t *)((0x1d09 << 2) + 0xff900000)
10302 //vertical scaler region1 phase slope, Bit24 signed bit
10303 #define VPP_VSC_REGION1_PHASE_SLOPE (0x1d0a)
10304 #define P_VPP_VSC_REGION1_PHASE_SLOPE (volatile uint32_t *)((0x1d0a << 2) + 0xff900000)
10305 //vertical scaler region3 phase slope, Bit24 signed bit
10306 #define VPP_VSC_REGION3_PHASE_SLOPE (0x1d0b)
10307 #define P_VPP_VSC_REGION3_PHASE_SLOPE (volatile uint32_t *)((0x1d0b << 2) + 0xff900000)
10308 //vertical scaler region4 phase slope, Bit24 signed bit
10309 #define VPP_VSC_REGION4_PHASE_SLOPE (0x1d0c)
10310 #define P_VPP_VSC_REGION4_PHASE_SLOPE (volatile uint32_t *)((0x1d0c << 2) + 0xff900000)
10311 //Bit 18:17 double line mode, input/output line width of vscaler becomes 2X,
10312 // so only 2 line buffer in this case, use for 3D line by line interleave scaling
10313 // bit1 true, double the input width and half input height, bit0 true, change line buffer 2 lines instead of 4 lines
10314 //Bit 16 0: progressive output, 1: interlace output
10315 //Bit 15 vertical scaler output line0 in advance or not for bottom field
10316 //Bit 14:13 vertical scaler initial repeat line0 number for bottom field
10317 //Bit 11:8 vertical scaler initial receiving number for bottom field
10318 //Bit 7 vertical scaler output line0 in advance or not for top field
10319 //Bit 6:5 vertical scaler initial repeat line0 number for top field
10320 //Bit 3:0 vertical scaler initial receiving number for top field
10321 #define VPP_VSC_PHASE_CTRL (0x1d0d)
10322 #define P_VPP_VSC_PHASE_CTRL (volatile uint32_t *)((0x1d0d << 2) + 0xff900000)
10323 //Bit 31:16 vertical scaler field initial phase for bottom field
10324 //Bit 15:0 vertical scaler field initial phase for top field
10325 #define VPP_VSC_INI_PHASE (0x1d0e)
10326 #define P_VPP_VSC_INI_PHASE (volatile uint32_t *)((0x1d0e << 2) + 0xff900000)
10327 //Bit 28:16 region1 startp
10328 //Bit 12:0 region2 startp
10329 #define VPP_HSC_REGION12_STARTP (0x1d10)
10330 #define P_VPP_HSC_REGION12_STARTP (volatile uint32_t *)((0x1d10 << 2) + 0xff900000)
10331 //Bit 28:16 region3 startp
10332 //Bit 12:0 region4 startp
10333 #define VPP_HSC_REGION34_STARTP (0x1d11)
10334 #define P_VPP_HSC_REGION34_STARTP (volatile uint32_t *)((0x1d11 << 2) + 0xff900000)
10335 #define VPP_HSC_REGION4_ENDP (0x1d12)
10336 #define P_VPP_HSC_REGION4_ENDP (volatile uint32_t *)((0x1d12 << 2) + 0xff900000)
10337 //horizontal start phase step, (source/dest)*(2^24)
10338 //Bit 27:24 integer part
10339 //Bit 23:0 fraction part
10340 #define VPP_HSC_START_PHASE_STEP (0x1d13)
10341 #define P_VPP_HSC_START_PHASE_STEP (volatile uint32_t *)((0x1d13 << 2) + 0xff900000)
10342 //horizontal scaler region0 phase slope, Bit24 signed bit
10343 #define VPP_HSC_REGION0_PHASE_SLOPE (0x1d14)
10344 #define P_VPP_HSC_REGION0_PHASE_SLOPE (volatile uint32_t *)((0x1d14 << 2) + 0xff900000)
10345 //horizontal scaler region1 phase slope, Bit24 signed bit
10346 #define VPP_HSC_REGION1_PHASE_SLOPE (0x1d15)
10347 #define P_VPP_HSC_REGION1_PHASE_SLOPE (volatile uint32_t *)((0x1d15 << 2) + 0xff900000)
10348 //horizontal scaler region3 phase slope, Bit24 signed bit
10349 #define VPP_HSC_REGION3_PHASE_SLOPE (0x1d16)
10350 #define P_VPP_HSC_REGION3_PHASE_SLOPE (volatile uint32_t *)((0x1d16 << 2) + 0xff900000)
10351 //horizontal scaler region4 phase slope, Bit24 signed bit
10352 #define VPP_HSC_REGION4_PHASE_SLOPE (0x1d17)
10353 #define P_VPP_HSC_REGION4_PHASE_SLOPE (volatile uint32_t *)((0x1d17 << 2) + 0xff900000)
10354 //Bit 22:21 horizontal scaler initial repeat pixel0 number0
10355 //Bit 19:16 horizontal scaler initial receiving number0
10356 //Bit 15:0 horizontal scaler top field initial phase0
10357 #define VPP_HSC_PHASE_CTRL (0x1d18)
10358 #define P_VPP_HSC_PHASE_CTRL (volatile uint32_t *)((0x1d18 << 2) + 0xff900000)
10359 // Bit 22 if true, divide VSC line length 2 as the HSC input length, othwise VSC length length is the same as the VSC line length,
10360 // just for special usage, more flexibility
10361 // Bit 21 if true, prevsc uses lin buffer, otherwise prevsc does not use line buffer, it should be same as prevsc_en
10362 // Bit 20 prehsc_en
10363 // Bit 19 prevsc_en
10364 // Bit 18 vsc_en
10365 // Bit 17 hsc_en
10366 // Bit 16 scale_top_en
10367 // Bit 15 video1 scale out enable
10368 // Bit 12 if true, region0,region4 are nonlinear regions, otherwise they are not scaling regions, for horizontal scaler
10369 // Bit 10:8 horizontal scaler bank length
10370 // Bit 5, vertical scaler phase field mode, if true, disable the opposite parity line output, more bandwith needed if output 1080i
10371 // Bit 4 if true, region0,region4 are nonlinear regions, otherwise they are not scaling regions, for vertical scaler
10372 // Bit 2:0 vertical scaler bank length
10373 #define VPP_SC_MISC (0x1d19)
10374 #define P_VPP_SC_MISC (volatile uint32_t *)((0x1d19 << 2) + 0xff900000)
10375 // preblend video1 horizontal start and end
10376 //Bit 28:16 start
10377 //Bit 12:0 end
10378 #define VPP_PREBLEND_VD1_H_START_END (0x1d1a)
10379 #define P_VPP_PREBLEND_VD1_H_START_END (volatile uint32_t *)((0x1d1a << 2) + 0xff900000)
10380 // preblend video1 vertical start and end
10381 //Bit 28:16 start
10382 //Bit 12:0 end
10383 #define VPP_PREBLEND_VD1_V_START_END (0x1d1b)
10384 #define P_VPP_PREBLEND_VD1_V_START_END (volatile uint32_t *)((0x1d1b << 2) + 0xff900000)
10385 // postblend video1 horizontal start and end
10386 //Bit 28:16 start
10387 //Bit 12:0 end
10388 #define VPP_POSTBLEND_VD1_H_START_END (0x1d1c)
10389 #define P_VPP_POSTBLEND_VD1_H_START_END (volatile uint32_t *)((0x1d1c << 2) + 0xff900000)
10390 // postblend video1 vertical start and end
10391 //Bit 28:16 start
10392 //Bit 12:0 end
10393 #define VPP_POSTBLEND_VD1_V_START_END (0x1d1d)
10394 #define P_VPP_POSTBLEND_VD1_V_START_END (volatile uint32_t *)((0x1d1d << 2) + 0xff900000)
10395 // preblend/postblend video2 horizontal start and end
10396 //Bit 28:16 start
10397 //Bit 12:0 end
10398 #define VPP_BLEND_VD2_H_START_END (0x1d1e)
10399 #define P_VPP_BLEND_VD2_H_START_END (volatile uint32_t *)((0x1d1e << 2) + 0xff900000)
10400 // preblend/postblend video2 vertical start and end
10401 //Bit 28:16 start
10402 //Bit 12:0 end
10403 #define VPP_BLEND_VD2_V_START_END (0x1d1f)
10404 #define P_VPP_BLEND_VD2_V_START_END (volatile uint32_t *)((0x1d1f << 2) + 0xff900000)
10405 // preblend horizontal size
10406 #define VPP_PREBLEND_H_SIZE (0x1d20)
10407 #define P_VPP_PREBLEND_H_SIZE (volatile uint32_t *)((0x1d20 << 2) + 0xff900000)
10408 // postblend horizontal size
10409 #define VPP_POSTBLEND_H_SIZE (0x1d21)
10410 #define P_VPP_POSTBLEND_H_SIZE (volatile uint32_t *)((0x1d21 << 2) + 0xff900000)
10411 //VPP hold lines
10412 //Bit 29:24
10413 //Bit 21:16
10414 //Bit 15:8 preblend hold lines
10415 //Bit 7:0 postblend hold lines
10416 #define VPP_HOLD_LINES (0x1d22)
10417 #define P_VPP_HOLD_LINES (volatile uint32_t *)((0x1d22 << 2) + 0xff900000)
10418 //Bit 26 if true, automatic change post blend output to one color if field ==1
10419 //Bit 25 if true, change screen to one color value for preblender
10420 //Bit 24 if true, change screen to one color value for postblender
10421 // Bit 23:16 one color Y
10422 // Bit 15:8 one color Cb
10423 // Bit 7:0 one color Cr
10424 #define VPP_BLEND_ONECOLOR_CTRL (0x1d23)
10425 #define P_VPP_BLEND_ONECOLOR_CTRL (volatile uint32_t *)((0x1d23 << 2) + 0xff900000)
10426 //Read Only, VPP preblend current_x, current_y
10427 //Bit 28:16 current_x
10428 //Bit 12:0 current_y
10429 #define VPP_PREBLEND_CURRENT_XY (0x1d24)
10430 #define P_VPP_PREBLEND_CURRENT_XY (volatile uint32_t *)((0x1d24 << 2) + 0xff900000)
10431 //Read Only, VPP postblend current_x, current_y
10432 //Bit 28:16 current_x
10433 //Bit 12:0 current_y
10434 #define VPP_POSTBLEND_CURRENT_XY (0x1d25)
10435 #define P_VPP_POSTBLEND_CURRENT_XY (volatile uint32_t *)((0x1d25 << 2) + 0xff900000)
10436 // Bit 31 vd1_bgosd_exchange_en for preblend
10437 // Bit 30 vd1_bgosd_exchange_en for postblend
10438 // Bit 28 color management enable
10439 // Bit 27, if true, vd2 use viu2 output as the input, otherwise use normal vd2 from memory
10440 // Bit 26:18, vd2 alpha
10441 // Bit 17, osd2 enable for preblend
10442 // Bit 16, osd1 enable for preblend
10443 // Bit 15, vd2 enable for preblend
10444 // Bit 14, vd1 enable for preblend
10445 // Bit 13, osd2 enable for postblend
10446 // Bit 12, osd1 enable for postblend
10447 // Bit 11, vd2 enable for postblend
10448 // Bit 10, vd1 enable for postblend
10449 // Bit 9, if true, osd1 is alpha premultipiled
10450 // Bit 8, if true, osd2 is alpha premultipiled
10451 // Bit 7, postblend module enable
10452 // Bit 6, preblend module enable
10453 // Bit 5, if true, osd2 foreground compared with osd1 in preblend
10454 // Bit 4, if true, osd2 foreground compared with osd1 in postblend
10455 // Bit 3,
10456 // Bit 2, if true, disable resetting async fifo every vsync, otherwise every vsync
10457 // the aync fifo will be reseted.
10458 // Bit 1,
10459 // Bit 0 if true, the output result of VPP is saturated
10460 #define VPP_MISC (0x1d26)
10461 #define P_VPP_MISC (volatile uint32_t *)((0x1d26 << 2) + 0xff900000)
10462 //Bit 31:20 ofifo line length minus 1
10463 //Bit 19 if true invert input vs
10464 //Bit 18 if true invert input hs
10465 //Bit 17 force top/bottom field, enable
10466 //Bit 16 force top/bottom field, 0: top, 1: bottom
10467 //Bit 15 force one go_field, one pluse, write only
10468 //Bit 14 force one go_line, one pluse, write only
10469 //Bit 12:0 ofifo size (actually only bit 10:1 is valid), always even number
10470 #define VPP_OFIFO_SIZE (0x1d27)
10471 #define P_VPP_OFIFO_SIZE (volatile uint32_t *)((0x1d27 << 2) + 0xff900000)
10472 //Read only
10473 //Bit 28:18 current scale out fifo counter
10474 //Bit 17:13 current afifo counter
10475 //Bit 12:0 current ofifo counter
10476 #define VPP_FIFO_STATUS (0x1d28)
10477 #define P_VPP_FIFO_STATUS (volatile uint32_t *)((0x1d28 << 2) + 0xff900000)
10478 // Bit 5 SMOKE3 postblend enable only when postblend vd2 is not enable
10479 // Bit 4 SMOKE3 preblend enable only when preblend vd2 is not enable
10480 // Bit 3 SMOKE2 postblend enable only when postblend osd2 is not enable
10481 // Bit 2 SMOKE2 preblend enable only when preblend osd2 is not enable
10482 // Bit 1 SMOKE1 postblend enable only when postblend osd1 is not enable
10483 // Bit 0 SMOKE1 preblend enable only when preblend osd1 is not enable
10484 #define VPP_SMOKE_CTRL (0x1d29)
10485 #define P_VPP_SMOKE_CTRL (volatile uint32_t *)((0x1d29 << 2) + 0xff900000)
10486 //smoke can be used only when that blending is disable and then be used as smoke function
10487 //smoke1 for OSD1 chanel
10488 //smoke2 for OSD2 chanel
10489 //smoke3 for VD2 chanel
10490 //31:24 Y
10491 //23:16 Cb
10492 //15:8 Cr
10493 //7:0 Alpha
10494 #define VPP_SMOKE1_VAL (0x1d2a)
10495 #define P_VPP_SMOKE1_VAL (volatile uint32_t *)((0x1d2a << 2) + 0xff900000)
10496 #define VPP_SMOKE2_VAL (0x1d2b)
10497 #define P_VPP_SMOKE2_VAL (volatile uint32_t *)((0x1d2b << 2) + 0xff900000)
10498 #define VPP_SMOKE3_VAL (0x1d2c)
10499 #define P_VPP_SMOKE3_VAL (volatile uint32_t *)((0x1d2c << 2) + 0xff900000)
10500 //Bit 28:16 start
10501 //Bit 12:0 end
10502 #define VPP_SMOKE1_H_START_END (0x1d2d)
10503 #define P_VPP_SMOKE1_H_START_END (volatile uint32_t *)((0x1d2d << 2) + 0xff900000)
10504 //Bit 28:16 start
10505 //Bit 12:0 end
10506 #define VPP_SMOKE1_V_START_END (0x1d2e)
10507 #define P_VPP_SMOKE1_V_START_END (volatile uint32_t *)((0x1d2e << 2) + 0xff900000)
10508 //Bit 28:16 start
10509 //Bit 12:0 end
10510 #define VPP_SMOKE2_H_START_END (0x1d2f)
10511 #define P_VPP_SMOKE2_H_START_END (volatile uint32_t *)((0x1d2f << 2) + 0xff900000)
10512 //Bit 28:16 start
10513 //Bit 12:0 end
10514 #define VPP_SMOKE2_V_START_END (0x1d30)
10515 #define P_VPP_SMOKE2_V_START_END (volatile uint32_t *)((0x1d30 << 2) + 0xff900000)
10516 //Bit 28:16 start
10517 //Bit 12:0 end
10518 #define VPP_SMOKE3_H_START_END (0x1d31)
10519 #define P_VPP_SMOKE3_H_START_END (volatile uint32_t *)((0x1d31 << 2) + 0xff900000)
10520 //Bit 28:16 start
10521 //Bit 12:0 end
10522 #define VPP_SMOKE3_V_START_END (0x1d32)
10523 #define P_VPP_SMOKE3_V_START_END (volatile uint32_t *)((0x1d32 << 2) + 0xff900000)
10524 //Bit 27:16 scale out fifo line length minus 1
10525 //Bit 12:0 scale out fifo size (actually only bit 11:1 is valid, 11:1, max 1024), always even number
10526 #define VPP_SCO_FIFO_CTRL (0x1d33)
10527 #define P_VPP_SCO_FIFO_CTRL (volatile uint32_t *)((0x1d33 << 2) + 0xff900000)
10528 //for 3D quincunx sub-sampling and horizontal pixel by pixel 3D interleaving
10529 //Bit 27:24, prehsc_mode, bit 3:2, prehsc odd line interp mode, bit 1:0, prehsc even line interp mode,
10530 // each 2bit, 00: pix0+pix1/2, average, 01: pix1, 10: pix0
10531 //Bit 23 horizontal scaler double pixel mode
10532 //Bit 22:21 horizontal scaler initial repeat pixel0 number1
10533 //Bit 19:16 horizontal scaler initial receiving number1
10534 //Bit 15:0 horizontal scaler top field initial phase1
10535 #define VPP_HSC_PHASE_CTRL1 (0x1d34)
10536 #define P_VPP_HSC_PHASE_CTRL1 (volatile uint32_t *)((0x1d34 << 2) + 0xff900000)
10537 //for 3D quincunx sub-sampling
10538 //31:24 prehsc pattern, each patten 1 bit, from lsb -> msb
10539 //22:20 prehsc pattern start
10540 //18:16 prehsc pattern end
10541 //15:8 hsc pattern, each patten 1 bit, from lsb -> msb
10542 //6:4 hsc pattern start
10543 //2:0 hsc pattern end
10544 #define VPP_HSC_INI_PAT_CTRL (0x1d35)
10545 #define P_VPP_HSC_INI_PAT_CTRL (volatile uint32_t *)((0x1d35 << 2) + 0xff900000)
10546 //Bit 3 minus black level enable for vadj2
10547 //Bit 2 Video adjustment enable for vadj2
10548 //Bit 1 minus black level enable for vadj1
10549 //Bit 0 Video adjustment enable for vadj1
10550 #define VPP_VADJ_CTRL (0x1d40)
10551 #define P_VPP_VADJ_CTRL (volatile uint32_t *)((0x1d40 << 2) + 0xff900000)
10552 //Bit 16:8 brightness, signed value
10553 //Bit 7:0 contrast, unsigned value, contrast from 0 <= contrast <2
10554 #define VPP_VADJ1_Y (0x1d41)
10555 #define P_VPP_VADJ1_Y (volatile uint32_t *)((0x1d41 << 2) + 0xff900000)
10556 //cb' = cb*ma + cr*mb
10557 //cr' = cb*mc + cr*md
10558 //all are bit 9:0, signed value, -2 < ma/mb/mc/md < 2
10559 #define VPP_VADJ1_MA_MB (0x1d42)
10560 #define P_VPP_VADJ1_MA_MB (volatile uint32_t *)((0x1d42 << 2) + 0xff900000)
10561 #define VPP_VADJ1_MC_MD (0x1d43)
10562 #define P_VPP_VADJ1_MC_MD (volatile uint32_t *)((0x1d43 << 2) + 0xff900000)
10563 //Bit 16:8 brightness, signed value
10564 //Bit 7:0 contrast, unsigned value, contrast from 0 <= contrast <2
10565 #define VPP_VADJ2_Y (0x1d44)
10566 #define P_VPP_VADJ2_Y (volatile uint32_t *)((0x1d44 << 2) + 0xff900000)
10567 //cb' = cb*ma + cr*mb
10568 //cr' = cb*mc + cr*md
10569 //all are bit 9:0, signed value, -2 < ma/mb/mc/md < 2
10570 #define VPP_VADJ2_MA_MB (0x1d45)
10571 #define P_VPP_VADJ2_MA_MB (volatile uint32_t *)((0x1d45 << 2) + 0xff900000)
10572 #define VPP_VADJ2_MC_MD (0x1d46)
10573 #define P_VPP_VADJ2_MC_MD (volatile uint32_t *)((0x1d46 << 2) + 0xff900000)
10574 //Bit 2 horizontal chroma sharp/blur selection, 0:sharp, 1: blur
10575 //Bit 1 horizontal luma sharp/blur selection, 0:sharp, 1: blur
10576 //Bit 0 horizontal sharpness enable
10577 #define VPP_HSHARP_CTRL (0x1d50)
10578 #define P_VPP_HSHARP_CTRL (volatile uint32_t *)((0x1d50 << 2) + 0xff900000)
10579 //{1'b0,threhsold} < diff
10580 //Bit 26:16 luma threshold0
10581 //Bit 10:0 luma threshold1
10582 #define VPP_HSHARP_LUMA_THRESH01 (0x1d51)
10583 #define P_VPP_HSHARP_LUMA_THRESH01 (volatile uint32_t *)((0x1d51 << 2) + 0xff900000)
10584 //
10585 //Bit 26:16 luma threshold2
10586 //Bit 10:0 luma threshold3
10587 #define VPP_HSHARP_LUMA_THRESH23 (0x1d52)
10588 #define P_VPP_HSHARP_LUMA_THRESH23 (volatile uint32_t *)((0x1d52 << 2) + 0xff900000)
10589 //Bit 26:16 chroma threshold0
10590 //Bit 10:0 chroma threshold1
10591 #define VPP_HSHARP_CHROMA_THRESH01 (0x1d53)
10592 #define P_VPP_HSHARP_CHROMA_THRESH01 (volatile uint32_t *)((0x1d53 << 2) + 0xff900000)
10593 //Bit 26:16 chroma threshold2
10594 //Bit 10:0 chroma threshold3
10595 #define VPP_HSHARP_CHROMA_THRESH23 (0x1d54)
10596 #define P_VPP_HSHARP_CHROMA_THRESH23 (volatile uint32_t *)((0x1d54 << 2) + 0xff900000)
10597 //Bit 23:16 luma gain2
10598 //Bit 15:8 luma gain1
10599 //Bit 7:0 luma gain0
10600 #define VPP_HSHARP_LUMA_GAIN (0x1d55)
10601 #define P_VPP_HSHARP_LUMA_GAIN (volatile uint32_t *)((0x1d55 << 2) + 0xff900000)
10602 //
10603 //Bit 23:16 chroma gain2
10604 //Bit 15:8 chroma gain1
10605 //Bit 7:0 chroma gain0
10606 #define VPP_HSHARP_CHROMA_GAIN (0x1d56)
10607 #define P_VPP_HSHARP_CHROMA_GAIN (volatile uint32_t *)((0x1d56 << 2) + 0xff900000)
10608 //Read only
10609 //Bit 31, if it is true, it means this probe is valid in the last field/frame
10610 //Bit 29:20 component 0
10611 //Bit 19:10 component 1
10612 //Bit 9:0 component 2
10613 #define VPP_MATRIX_PROBE_COLOR (0x1d5c)
10614 #define P_VPP_MATRIX_PROBE_COLOR (volatile uint32_t *)((0x1d5c << 2) + 0xff900000)
10615 #define VPP_MATRIX_PROBE_COLOR1 (0x1dd7)
10616 #define P_VPP_MATRIX_PROBE_COLOR1 (volatile uint32_t *)((0x1dd7 << 2) + 0xff900000)
10617 //Bit 23:16 component 0
10618 //Bit 15:8 component 1
10619 //Bit 7:0 component 2
10620 #define VPP_MATRIX_HL_COLOR (0x1d5d)
10621 #define P_VPP_MATRIX_HL_COLOR (volatile uint32_t *)((0x1d5d << 2) + 0xff900000)
10622 //28:16 probe x, postion
10623 //12:0 probe y, position
10624 #define VPP_MATRIX_PROBE_POS (0x1d5e)
10625 #define P_VPP_MATRIX_PROBE_POS (volatile uint32_t *)((0x1d5e << 2) + 0xff900000)
10626 //Bit 16, highlight_en
10627 //Bit 15 probe_post, if true, probe pixel data after matrix, otherwise probe pixel data before matrix
10628 //Bit 14:12 probe_sel, 000: select post matrix, 001: select vd1 matrix, 010: select vd2 matrix
10629 //Bit 9:8 matrix coef idx selection, 00: select post matrix, 01: select vd1 matrix, 10: select vd2 matrix
10630 //Bit 5 vd1 conversion matrix enable
10631 //Bit 4 vd2 conversion matrix enable
10632 //Bit 2 output y/cb/cr saturation enable, only for post matrix (y saturate to 16-235, cb/cr saturate to 16-240)
10633 //Bit 1 input y/cb/cr saturation enable, only for post matrix (y saturate to 16-235, cb/cr saturate to 16-240)
10634 //Bit 0 post conversion matrix enable
10635 #define VPP_MATRIX_CTRL (0x1d5f)
10636 #define P_VPP_MATRIX_CTRL (volatile uint32_t *)((0x1d5f << 2) + 0xff900000)
10637 //Bit 28:16 coef00
10638 //Bit 12:0 coef01
10639 #define VPP_MATRIX_COEF00_01 (0x1d60)
10640 #define P_VPP_MATRIX_COEF00_01 (volatile uint32_t *)((0x1d60 << 2) + 0xff900000)
10641 //Bit 28:16 coef02
10642 //Bit 12:0 coef10
10643 #define VPP_MATRIX_COEF02_10 (0x1d61)
10644 #define P_VPP_MATRIX_COEF02_10 (volatile uint32_t *)((0x1d61 << 2) + 0xff900000)
10645 //Bit 28:16 coef11
10646 //Bit 12:0 coef12
10647 #define VPP_MATRIX_COEF11_12 (0x1d62)
10648 #define P_VPP_MATRIX_COEF11_12 (volatile uint32_t *)((0x1d62 << 2) + 0xff900000)
10649 //Bit 28:16 coef20
10650 //Bit 12:0 coef21
10651 #define VPP_MATRIX_COEF20_21 (0x1d63)
10652 #define P_VPP_MATRIX_COEF20_21 (volatile uint32_t *)((0x1d63 << 2) + 0xff900000)
10653 #define VPP_MATRIX_COEF22 (0x1d64)
10654 #define P_VPP_MATRIX_COEF22 (volatile uint32_t *)((0x1d64 << 2) + 0xff900000)
10655 //Bit 26:16 offset0
10656 //Bit 10:0 offset1
10657 #define VPP_MATRIX_OFFSET0_1 (0x1d65)
10658 #define P_VPP_MATRIX_OFFSET0_1 (volatile uint32_t *)((0x1d65 << 2) + 0xff900000)
10659 //Bit 10:0 offset2
10660 #define VPP_MATRIX_OFFSET2 (0x1d66)
10661 #define P_VPP_MATRIX_OFFSET2 (volatile uint32_t *)((0x1d66 << 2) + 0xff900000)
10662 //Bit 26:16 pre_offset0
10663 //Bit 10:0 pre_offset1
10664 #define VPP_MATRIX_PRE_OFFSET0_1 (0x1d67)
10665 #define P_VPP_MATRIX_PRE_OFFSET0_1 (volatile uint32_t *)((0x1d67 << 2) + 0xff900000)
10666 //Bit 10:0 pre_offset2
10667 #define VPP_MATRIX_PRE_OFFSET2 (0x1d68)
10668 #define P_VPP_MATRIX_PRE_OFFSET2 (volatile uint32_t *)((0x1d68 << 2) + 0xff900000)
10669 // dummy data used in the VPP postblend
10670 // Bit 23:16 Y
10671 // Bit 15:8 CB
10672 // Bit 7:0 CR
10673 #define VPP_DUMMY_DATA1 (0x1d69)
10674 #define P_VPP_DUMMY_DATA1 (volatile uint32_t *)((0x1d69 << 2) + 0xff900000)
10675 //Bit 31 gainoff module enable
10676 //Bit 26:16 gain0, 1.10 unsigned data
10677 //Bit 10:0 gain1, 1.10 unsigned dat
10678 #define VPP_GAINOFF_CTRL0 (0x1d6a)
10679 #define P_VPP_GAINOFF_CTRL0 (volatile uint32_t *)((0x1d6a << 2) + 0xff900000)
10680 //Bit 26:16 gain2, 1.10 unsigned data
10681 //Bit 10:0, offset0, signed data
10682 #define VPP_GAINOFF_CTRL1 (0x1d6b)
10683 #define P_VPP_GAINOFF_CTRL1 (volatile uint32_t *)((0x1d6b << 2) + 0xff900000)
10684 //Bit 26:16, offset1, signed data
10685 //Bit 10:0, offset2, signed data
10686 #define VPP_GAINOFF_CTRL2 (0x1d6c)
10687 #define P_VPP_GAINOFF_CTRL2 (volatile uint32_t *)((0x1d6c << 2) + 0xff900000)
10688 //Bit 26:16, pre_offset0, signed data
10689 //Bit 10:0, pre_offset1, signed data
10690 #define VPP_GAINOFF_CTRL3 (0x1d6d)
10691 #define P_VPP_GAINOFF_CTRL3 (volatile uint32_t *)((0x1d6d << 2) + 0xff900000)
10692 //Bit 10:0, pre_offset2, signed data
10693 #define VPP_GAINOFF_CTRL4 (0x1d6e)
10694 #define P_VPP_GAINOFF_CTRL4 (volatile uint32_t *)((0x1d6e << 2) + 0xff900000)
10695 //only two registers used in the color management, which are defined in the chroma_reg.h
10696 //`define VPP_CHROMA_ADDR_PORT 8'h70
10697 //`define VPP_CHROMA_DATA_PORT 8'h71
10698 //
10699 // Reading file: chroma_reg.h
10700 //
10701 //**********************************************************************************
10702 //* Copyright (c) 2008, AMLOGIC Inc.
10703 //* All rights reserved
10704 //**********************************************************************************
10705 //* File : chroma_reg.v
10706 //* Author : Terrence Wang
10707 //* Date : Dec 2008
10708 //* Description :
10709 //*
10710 //**********************************************************************************
10711 //* Modification History:
10712 //* Date Modified By Reason
10713 //**********************************************************************************
10714 // synopsys translate_off
10715 // synopsys translate_on
10716 #define VPP_CHROMA_ADDR_PORT (0x1d70)
10717 #define P_VPP_CHROMA_ADDR_PORT (volatile uint32_t *)((0x1d70 << 2) + 0xff900000)
10718 #define VPP_CHROMA_DATA_PORT (0x1d71)
10719 #define P_VPP_CHROMA_DATA_PORT (volatile uint32_t *)((0x1d71 << 2) + 0xff900000)
10720 //`define CHROMA_ADDR_PORT 8'h67
10721 //`define CHROMA_DATA_PORT 8'h68
10722
10723 // CHROMA_GAIN_REG_XX(00-07)
10724 // hue gain, sat gain function control
10725 // Bit 31 reg_sat_en enable sat adjustment in current region
10726 // Bit 27 reg_sat_increase sat adjustment increase or decrease
10727 // 1'b1: increase 1'b0: decrease
10728 // Bit 26:25 reg_sat_central_en sat adjustment with central biggest or one side biggest
10729 // 2'b01 central biggest 2'b00 one side biggest
10730 // Bit 24 reg_sat_shape when sat adjustment one side biggest, define left or right
10731 // 1'b1: left side biggest 1'b0 right side biggest
10732 // Bit 23:16 reg_sat_gain define the sat gain when sat adjustment
10733 // 0x00-0xff
10734 // Bit 15 reg_hue_en enable hue adjustment in current region
10735 // Bit 11 reg_hue_clockwise hue adjustment clockwise or anti-clockwise
10736 // 1'b1: clockwise 1'b0: anti-clockwise
10737 // Bit 10:9 reg_hue_central_en when hue adjustment, parabola curve or non-symmetry curve
10738 // 1'b1: parabola curve 1'b0: non-symmetry curve
10739 // Bit 8 reg_hue_shape when non-symmetry curve, define which side change more
10740 // 1'b1: right side change more 1'b0: left side change more
10741 // Bit 7:0 reg_hue_gain define the hue gain when hue adjustment
10742 // 0x00-0x80, note: should be no bigger than 0x80
10743
10744 #define CHROMA_GAIN_REG00 0x00
10745
10746
10747 // HUE_HUE_RANGE_REG_XX(00-07)
10748 // hue range select
10749 // Bit 31:24 no use now
10750 // Bit 23:16 reg_hue_shift_range define the angle of target region
10751 // 0x00-0xff,(0x100 means 120 degree though it can not be set)
10752 // must be greater or equal than 8'd8
10753 // Bit 15 reg_symmetry_en this is used for create one symmetry region
10754 // the symmetry region hue_shift_start = reg_hue_hue_shift_start + reg_hue_shift_range<<5
10755 // the symmetry region hue_shift_range = reg_hue_shift_range
10756 // in symmetry region, all the sat and hue setting will be same with original region,
10757 // except reg_hue_shape, reg_sat_shape, reg_hue_clockwise will be reversed
10758 // Bit 14:0 reg_hue_hue_shift_start define the start angle of target region
10759 // 0x6000 means 360 degree
10760 // only region 0 and 1 can exceed 360 degrees.
10761
10762 #define HUE_HUE_RANGE_REG00 0x01
10763
10764
10765 // HUE_RANGE_INV_REG_XX
10766 // Calculation should be follow
10767 // HUE_RANGE_INV_REG0X[15:0] = ((1<<20)/HUE_HUE_RANGE_REG0X[23:16]+1)>>1
10768 // HUE_RANGE_INV_REG_XX is to used to save divider
10769
10770 #define HUE_RANGE_INV_REG00 0x02
10771
10772
10773
10774 // for belowing each low, high, low_slope, high_slope group:
10775 // a_____________b
10776 // / \ a = low + 2^low_slope
10777 // / \ b = high - 2^high_slope
10778 // / \ low_slope <= 7; high_slope <= 7
10779 // / \ b >= a
10780 // ______/_____________________\________
10781 // low high
10782 //
10783 //
10784 // HUE_LUM_RANGE_REG_XX(00-07)
10785 // luma range selection for hue adjustment
10786 // Bit 31:24 reg_sat_lum_low define the low level of luma value for sat adjustment
10787 // 0x00-0xff
10788 // Bit 23:20 reg_hue_lum_high_slope define the slope area below high level of luma value for hue adjustment
10789 // 0x00-0x07
10790 // Bit 19:16 reg_hue_lum_low_slope define the slope area above low level of luma value for hue adjustment
10791 // 0x00-0x07
10792 // Bit 15:8 reg_hue_lum_high define the high level of luma value for hue adjustment
10793 // 0x00-0xff
10794 // Bit 7:0 reg_hue_lum_low define the low level of luma value for hue adjustment
10795 // 0x00-0xff
10796
10797 #define HUE_LUM_RANGE_REG00 0x03
10798
10799 // HUE_SAT_RANGE_REG_XX(00-07)
10800 // sat range selection for hue adjustment
10801 // Bit 31:24 reg_sat_lum_high define the high level of luma value for sat adjustment
10802 // 0x00-0xff
10803 // Bit 23:20 reg_hue_sat_high_slope define the slope area below high level of sat value for hue adjustment
10804 // 0x00-0x07
10805 // Bit 19:16 reg_hue_sat_low_slope define the slope area above low level of sat value for hue adjustment
10806 // 0x00-0x07
10807 // Bit 15:8 reg_hue_sat_high define the high level of sat value for hue adjustment
10808 // 0x00-0xff
10809 // Bit 7:0 reg_hue_sat_low define the low level of sat value for hue adjustment
10810 // 0x00-0xff
10811
10812 #define HUE_SAT_RANGE_REG00 0x04
10813
10814 // SAT_SAT_RANGE_REG_XX(00-07)
10815 // sat range selection for hue adjustment
10816 // Bit 31:28 reg_sat_lum_high_slope define the slope area below high level of luma value for sat adjustment
10817 // 0x00-0x07
10818 // Bit 27:24 reg_sat_lum_low_slope define the slope area above low level of luma value for sat adjustment
10819 // 0x00-0x07
10820 // Bit 23:20 reg_sat_sat_high_slope define the slope area below high level of sat value for sat adjustment
10821 // 0x00-0x07
10822 // Bit 19:16 reg_sat_sat_low_slope define the slope area above low level of sat value for sat adjustment
10823 // 0x00-0x07
10824 // Bit 15:8 reg_sat_sat_high define the high level of sat value for sat adjustment
10825 // 0x00-0xff
10826 // Bit 7:0 reg_sat_sat_low define the low level of sat value for sat adjustment
10827 // 0x00-0xff
10828
10829 #define SAT_SAT_RANGE_REG00 0x05
10830
10831
10832 #define CHROMA_GAIN_REG01 0x06
10833 #define HUE_HUE_RANGE_REG01 0x07
10834 #define HUE_RANGE_INV_REG01 0x08
10835 #define HUE_LUM_RANGE_REG01 0x09
10836 #define HUE_SAT_RANGE_REG01 0x0a
10837 #define SAT_SAT_RANGE_REG01 0x0b
10838
10839 #define CHROMA_GAIN_REG02 0x0c
10840 #define HUE_HUE_RANGE_REG02 0x0d
10841 #define HUE_RANGE_INV_REG02 0x0e
10842 #define HUE_LUM_RANGE_REG02 0x0f
10843 #define HUE_SAT_RANGE_REG02 0x10
10844 #define SAT_SAT_RANGE_REG02 0x11
10845
10846
10847 #define CHROMA_GAIN_REG03 0x12
10848 #define HUE_HUE_RANGE_REG03 0x13
10849 #define HUE_RANGE_INV_REG03 0x14
10850 #define HUE_LUM_RANGE_REG03 0x15
10851 #define HUE_SAT_RANGE_REG03 0x16
10852 #define SAT_SAT_RANGE_REG03 0x17
10853
10854 #define CHROMA_GAIN_REG04 0x18
10855 #define HUE_HUE_RANGE_REG04 0x19
10856 #define HUE_RANGE_INV_REG04 0x1a
10857 #define HUE_LUM_RANGE_REG04 0x1b
10858 #define HUE_SAT_RANGE_REG04 0x1c
10859 #define SAT_SAT_RANGE_REG04 0x1d
10860
10861 #define CHROMA_GAIN_REG05 0x1e
10862 #define HUE_HUE_RANGE_REG05 0x1f
10863 #define HUE_RANGE_INV_REG05 0x20
10864 #define HUE_LUM_RANGE_REG05 0x21
10865 #define HUE_SAT_RANGE_REG05 0x22
10866 #define SAT_SAT_RANGE_REG05 0x23
10867
10868 #define CHROMA_GAIN_REG06 0x24
10869 #define HUE_HUE_RANGE_REG06 0x25
10870 #define HUE_RANGE_INV_REG06 0x26
10871 #define HUE_LUM_RANGE_REG06 0x27
10872 #define HUE_SAT_RANGE_REG06 0x28
10873 #define SAT_SAT_RANGE_REG06 0x29
10874
10875 #define CHROMA_GAIN_REG07 0x2a
10876 #define HUE_HUE_RANGE_REG07 0x2b
10877 #define HUE_RANGE_INV_REG07 0x2c
10878 #define HUE_LUM_RANGE_REG07 0x2d
10879 #define HUE_SAT_RANGE_REG07 0x2e
10880 #define SAT_SAT_RANGE_REG07 0x2f
10881
10882 // REG_CHROMA_CONTROL
10883 // Bit 31 reg_chroma_en enable color manage function
10884 // 1'b1: enable 1'b0: bypass
10885 // Bit 6 sat_sel uv_max or u^2+v^2 selected as sat for reference
10886 // 1'b1: uv_max(default) 1'b0: u^2+v^2
10887 // Bit 5 uv_adj_en final uv_adjust enable
10888 // 1'b1: enable 1'b0: bypass
10889 // Bit 2 hue_en rgb to hue enable
10890 // 1'b1: enable(default) 1'b0: bypass
10891 // Bit 1:0 csc_sel define input YUV with different color type
10892 // 2'b00: 601(16-235) 2'b01: 709(16-235)
10893 // 2'b10: 601(0-255) 2'b11: 709(0-255)
10894 #define REG_CHROMA_CONTROL 0x30 // default 32h'80000024
10895 #define REG_DEMO_CENTER_BAR 0x31 // default 32h'0
10896 #define REG_DEMO_HLIGHT_MODE 0x32 // default 32h'0
10897 #define REG_DEMO_OWR_DATA 0x33 // default 32h'0
10898
10899
10900 ////===========================================////
10901 //// CM2 ADDR
10902 ////===========================================////
10903
10904 #define SAT_BYYB_NODE_REG0 0x200 // default 32'h0
10905 //Bit 31:24, sat_byyb_node3 the 4th node
10906 //Bit 23:16, sat_byyb_node2 the 3th node
10907 //Bit 15: 8, sat_byyb_node1 signed, the 2th node about saturation
10908 //Bit 7: 0, sat_byyb_node0 signed, the 1th node about saturation
10909 //gain offset along y coordinate,the gain normalized to 128 as "1"
10910
10911 #define SAT_BYYB_NODE_REG1 0x201 // default 32'h0
10912 //Bit 31:24, sat_byyb_node7 the 8th node
10913 //Bit 23:16, sat_byyb_node6 the 7th node
10914 //Bit 15: 8, sat_byyb_node5 signed, the 6th node about saturation
10915 //Bit 7: 0, sat_byyb_node4 signed, the 5th node about saturation
10916 //gain offset along y coordinate,the gain normalized to 128 as "1"
10917
10918 #define SAT_BYYB_NODE_REG2 0x202 // default 32'h0
10919 //Bit 31: 8, reserved
10920 //Bit 7: 0, sat_byyb_node4 signed, the 5th node about saturation
10921
10922
10923 #define SAT_SRC_NODE_REG 0x203 // default 32'h0
10924 //Bit 31:28, reserved
10925 //Bit 27:16, sat_src_node1
10926 //Bit 15:12, reserved
10927 //Bit 11: 0, sat_src_node0 usigned, threshold of input saturation for first and second piece
10928
10929 #define CM_ENH_SFT_MODE_REG 0x204 // default 32'h0
10930 //Bit 31: 9, reserved
10931 //Bit 8: 6, hue_lsft_mode hue offset adjustments scale
10932 //Bit 5: 4, luma_lsft_mode luma offset adjustments scale for reg_cm2_adj_luma_via_hue
10933 //Bit 3: 2, sat_byy_rsft_mode saturation gain adjustments scale for reg_cm2_adj_sat_via_y
10934 //Bit 1: 0, sat_byhs_rsft_mode saturation gain adjustments scale for reg_cm2_adj_sat_via_hs[:][:] 0:no scale up/down 1:dnscale by 2(-128,127)/2
10935
10936 #define FRM_SIZE_REG 0x205 // default 32'h0
10937 //Bit 31:29, reserved
10938 //Bit 28:16, reg_frm_height the frame height size
10939 //Bit 15:13, reserved
10940 //Bit 12: 0, reg_frm_width the frame width size
10941
10942 #define FITLER_CFG_REG 0x206 // default 32'h0
10943 //Bit 31: 5, reserved
10944 //Bit 4: 4, inteleav_mod horizontal interleave filter(zero-padding) for 3D considerations 0:using non-zero padding lpf 1:using zero-padding lpf
10945 //Bit 3: 2, lpf_slt_uv apply cm on lp portion or original video pixels options
10946 //Bit 1: 0, lpf_slt_y apply cm on lp portion or original video pixels options
10947
10948 #define CM_GLOBAL_GAIN_REG 0x207 // default 32'h0
10949 //Bit 31:28, reserved
10950 //Bit 27:16, cm2_global_sat global saturation gain for general color adjustments(0~4095 <=> 0~8),512 normalized to "1"
10951 //Bit 15:12, reserved
10952 //Bit 11: 0, cm2_global_hue global hue offsets for general color adjustments(0~4095 <=> 0~360 degree)
10953
10954 #define CM_ENH_CTL_REG 0x208 // default 32'h0
10955 //Bit 31:7, reserved
10956 //Bit 6, hue_adj_en cm2 hue adjustments
10957 //Bit 5, sat_adj_en cm2 saturation adjustments
10958 //Bit 4, luma_adj_en enable siganl for cm2 luma adjustments
10959 //Bit 3, reserved
10960 //Bit 2, cm2_filt_en apply cm on lp portion enable
10961 //Bit 1, cm2_en cm2 enable siganl
10962 //Bit 0, cm1_en
10963
10964 #define ROI_X_SCOPE_REG 0x209 // default 32'h0
10965 //Bit 31:29, reserved
10966 //Bit 28:16, roi_x_end ending col index of the region of interest
10967 //Bit 15:13, reserved
10968 //Bit 12: 0, roi_x_beg start col index of the region of interest
10969
10970 #define ROI_Y_SCOPE_REG 0x20a // default 32'h0
10971 //Bit 31:29, reserved
10972 //Bit 28:16, roi_y_end ending row index of the region of interest
10973 //Bit 15:13, reserved
10974 //Bit 12: 0, roi_y_beg start row index of the region of interest
10975
10976 #define POI_XY_DIR_REG 0x20b // default 32'h0
10977 //Bit 31:29, reserved
10978 //Bit 28:16, poi_y_dir ending row index of the region of interest
10979 //Bit 15:13, reserved
10980 //Bit 12: 0, poi_x_dir start row index of the region of interest
10981
10982 #define COI_Y_SCOPE_REG 0x20c // default 32'h0
10983 //Bit 31:16, reserved
10984 //Bit 15: 8, coi_y_end
10985 //Bit 7: 0, coi_y_beg
10986
10987 #define COI_H_SCOPE_REG 0x20d // default 32'h0
10988 //Bit 31:28, reserved
10989 //Bit 27:16, coi_h_end
10990 //Bit 15:12, reserved
10991 //Bit 11: 0, coi_h_beg lower bound of hue value for color of interest ,12 bits precision
10992
10993 #define COI_S_SCOPE_REG 0x20e // default 32'h0
10994 //Bit 31:28, reserved
10995 //Bit 27:16, coi_s_end
10996 //Bit 15:12, reserved
10997 //Bit 11: 0, coi_s_beg lower bound of sat value for color of interest ,12 bits precision
10998 #define IFO_MODE_REG 0x20f // default 32'h0
10999 //Bit 31:8, reserved
11000 //Bit 7:6, ifo_mode3
11001 //Bit 5:4, ifo_mode2
11002 //Bit 3:2, ifo_mode1
11003 //Bit 1:0, ifo_mode0
11004 #define POI_RPL_MODE_REG 0x210 // default 32'h0
11005 //Bit 31:4, reserved
11006 //Bit 3:0, poi_rpl_mode enhance mode control of pixels inside and outside region of interest bit[3:2]control roi
11007 #define DEMO_OWR_YHS_REG 0x211 // default 32'h0
11008 //Bit 31: 0, demo_owr_yhs
11009
11010 #define DEMO_POI_Y_REG 0x212 // default 32'h0
11011 //Bit 31: 8, reserved
11012 //Bit 7: 0, luma_data_poi_r only get locked higher 8bits
11013 #define DEMO_POI_H_REG 0x213 // default 32'h0
11014 //Bit 31: 12, reserved
11015 //Bit 11: 0, hue_data_poi_r only get locked higher 12bits
11016 #define DEMO_POI_S_REG 0x214 // default 32'h0
11017 //Bit 31: 12, reserved
11018 //Bit 11: 0, sat_data_poi_r only get locked higher 12bits
11019 //#define LUMA_BYH_LIMT_REG 0x215 // default 32'h0
11020 #define LUMA_ADJ_LIMT_REG 0x215 // default 32'h0
11021 //Bit 31:24, reserved
11022 //Bit 23:16, luma_lmt_satslp slope to do the luma adjustment degrade
11023 //Bit 15:12, reserved
11024 //Bit 11:0, luma_lmt_satth threshold to saturation
11025 #define SAT_ADJ_LIMT_REG 0x216 // default 32'h0
11026 //Bit 31:24, reserved
11027 //Bit 23:16, sat_lmt_satslp slope to do the adjustment degrade
11028 //Bit 15:12, reserved
11029 //Bit 11:0, sat_lmt_satth threshold to saturation
11030 #define HUE_ADJ_LIMT_REG 0x217 // default 32'h0
11031 //Bit 31: 24, reserved
11032 //Bit 23: 16, hue_lmt_satslp slope to do the adjustment degrade
11033 //Bit 15: 12, reserved
11034 //Bit 11: 0, hue_lmt_satth threshold to saturation
11035 #define UVHS_OFST_REG 0x218 // default 32'h0
11036 //Bit 31: 24, hs2uv_v_ofst
11037 //Bit 23: 16, hs2uv_u_ofst
11038 //Bit 15: 8, uv2hs_v_ofst
11039 //Bit 7: 0, uv2hs_u_ofst
11040 #define HUE_CFG_PARA_REG 0x219 // default 32'h0
11041 //Bit 31: 17, reserved
11042 //Bit 16, hue_protect_en
11043 //Bit 15: 13, cm2_hue_byhs_mode
11044 //Bit 12, cm2_hue_div_mode
11045 //Bit 11: 0, cm2_before_hue_ofst
11046 #define DEMO_SPLT_CFG_REG 0x21a // default 32'h0
11047 //Bit 31: 22, reserved
11048 //Bit 21: 20, demo_split_mode
11049 //Bit 19: 16, demo_split_width slope to do the adjustment degrade
11050 //Bit 15: 13, reserved
11051 //Bit 12: 0, demo_split_post threshold to saturation
11052 #define DEMO_SPLT_YHS_REG 0x21b // default 32'h0
11053 //Bit 31: 0, demo_splt_yhs threshold to saturation
11054
11055 #define XVYCC_YSCP_REG 0x21c // default 32'h0
11056 //Bit 31: 28, reserved
11057 //Bit 27: 16, xvycc_y_max
11058 //Bit 15: 12, reserved
11059 //Bit 11: 0, xvycc_y_min
11060 #define XVYCC_USCP_REG 0x21d // default 32'h0
11061 //Bit 31: 28, reserved
11062 //Bit 27: 16, xvycc_u_max
11063 //Bit 15: 12, reserved
11064 //Bit 11: 0, xvycc_u_min
11065 #define XVYCC_VSCP_REG 0x21e // default 32'h0
11066 //Bit 31: 28, reserved
11067 //Bit 27: 16, xvycc_v_max
11068 //Bit 15: 12, reserved
11069 //Bit 11: 0, xvycc_v_min
11070
11071 ////========= NODE 0 COEFFICIENT ==============////
11072
11073 #define REG_CM2_ENH_COEFF0_H00 0x100 // default 32'H0
11074 //Bit 31: 24, reg_cm2_adj_sat_via_hs_2
11075 //Bit 23: 16, reg_cm2_adj_sat_via_hs_1
11076 //Bit 15: 8, reg_cm2_adj_sat_via_hs_0
11077 //Bit 7: 0, reg_cm2_adj_luma_via_h
11078 // [ 7: 0] : luma_byh_hx / [15: 8] : sat_byhs_s0hx
11079 // [23:16] : sat_byhs_s0hx / [31:24] : sat_byhs_s2hx
11080 #define REG_CM2_ENH_COEFF1_H00 0x101 // default 32'H0
11081 // [ 7: 0] : hue_byh_hx / [15: 8] : hue_byy_y0hx
11082 // [23:16] : hue_byy_y1hx / [31:24] : hue_byy_y2hx
11083 #define REG_CM2_ENH_COEFF2_H00 0x102 // default 32'H0
11084 // [ 7: 0] : hue_byy_y3hx / [15: 8] : hue_byy_y4hx
11085 // [23:16] : hue_bys_s0hx / [31:24] : hue_bys_s1hx
11086 #define REG_CM2_ENH_COEFF3_H00 0x103 // default 32'H0
11087 // [ 7: 0] : hue_bys_s2hx / [15: 8] : hue_bys_s3hx
11088 // [23:16] : hue_bys_s4hx / [31:24] : hue_byya_y0hx
11089 #define REG_CM2_ENH_COEFF4_H00 0x104 // default 32'H0
11090 // [ 7: 0] : hue_byya_y1hx / [15: 8] : hue_byya_y2hx
11091 // [23:16] : hue_byya_y3hx / [31:24] : hue_byya_y4hx
11092
11093 ////========= NODE 1 COEFFICIENT ==============////
11094
11095 #define REG_CM2_ENH_COEFF0_H01 0x108 // default 32'H0
11096 // [ 7: 0] : luma_byh_hx / [15: 8] : sat_byhs_s0hx
11097 // [23:16] : sat_byhs_s0hx / [31:24] : sat_byhs_s2hx
11098 #define REG_CM2_ENH_COEFF1_H01 0x109 // default 32'H0
11099 // [ 7: 0] : hue_byh_hx / [15: 8] : hue_byy_y0hx
11100 // [23:16] : hue_byy_y1hx / [31:24] : hue_byy_y2hx
11101 #define REG_CM2_ENH_COEFF2_H01 0x10a // default 32'H0
11102 // [ 7: 0] : hue_byy_y3hx / [15: 8] : hue_byy_y4hx
11103 // [23:16] : hue_bys_s0hx / [31:24] : hue_bys_s1hx
11104 #define REG_CM2_ENH_COEFF3_H01 0x10b // default 32'H0
11105 // [ 7: 0] : hue_bys_s2hx / [15: 8] : hue_bys_s3hx
11106 // [23:16] : hue_bys_s4hx / [31:24] : hue_byya_y0hx
11107 #define REG_CM2_ENH_COEFF4_H01 0x10c // default 32'H0
11108 // [ 7: 0] : hue_byya_y1hx / [15: 8] : hue_byya_y2hx
11109 // [23:16] : hue_byya_y3hx / [31:24] : hue_byya_y4hx
11110
11111 ////========= NODE 2 COEFFICIENT ==============////
11112
11113 #define REG_CM2_ENH_COEFF0_H02 0x110 // default 32'H0
11114 // [ 7: 0] : luma_byh_hx / [15: 8] : sat_byhs_s0hx
11115 // [23:16] : sat_byhs_s0hx / [31:24] : sat_byhs_s2hx
11116 #define REG_CM2_ENH_COEFF1_H02 0x111 // default 32'H0
11117 // [ 7: 0] : hue_byh_hx / [15: 8] : hue_byy_y0hx
11118 // [23:16] : hue_byy_y1hx / [31:24] : hue_byy_y2hx
11119 #define REG_CM2_ENH_COEFF2_H02 0x112 // default 32'H0
11120 // [ 7: 0] : hue_byy_y3hx / [15: 8] : hue_byy_y4hx
11121 // [23:16] : hue_bys_s0hx / [31:24] : hue_bys_s1hx
11122 #define REG_CM2_ENH_COEFF3_H02 0x113 // default 32'H0
11123 // [ 7: 0] : hue_bys_s2hx / [15: 8] : hue_bys_s3hx
11124 // [23:16] : hue_bys_s4hx / [31:24] : hue_byya_y0hx
11125 #define REG_CM2_ENH_COEFF4_H02 0x114 // default 32'H0
11126 // [ 7: 0] : hue_byya_y1hx / [15: 8] : hue_byya_y2hx
11127 // [23:16] : hue_byya_y3hx / [31:24] : hue_byya_y4hx
11128
11129 ////========= NODE 3 COEFFICIENT ==============////
11130
11131 #define REG_CM2_ENH_COEFF0_H03 0x118 // default 32'H0
11132 // [ 7: 0] : luma_byh_hx / [15: 8] : sat_byhs_s0hx
11133 // [23:16] : sat_byhs_s0hx / [31:24] : sat_byhs_s2hx
11134 #define REG_CM2_ENH_COEFF1_H03 0x119 // default 32'H0
11135 // [ 7: 0] : hue_byh_hx / [15: 8] : hue_byy_y0hx
11136 // [23:16] : hue_byy_y1hx / [31:24] : hue_byy_y2hx
11137 #define REG_CM2_ENH_COEFF2_H03 0x11a // default 32'H0
11138 // [ 7: 0] : hue_byy_y3hx / [15: 8] : hue_byy_y4hx
11139 // [23:16] : hue_bys_s0hx / [31:24] : hue_bys_s1hx
11140 #define REG_CM2_ENH_COEFF3_H03 0x11b // default 32'H0
11141 // [ 7: 0] : hue_bys_s2hx / [15: 8] : hue_bys_s3hx
11142 // [23:16] : hue_bys_s4hx / [31:24] : hue_byya_y0hx
11143 #define REG_CM2_ENH_COEFF4_H03 0x11c // default 32'H0
11144 // [ 7: 0] : hue_byya_y1hx / [15: 8] : hue_byya_y2hx
11145 // [23:16] : hue_byya_y3hx / [31:24] : hue_byya_y4hx
11146
11147 ////========= NODE 4 COEFFICIENT ==============////
11148
11149 #define REG_CM2_ENH_COEFF0_H04 0x120 // default 32'H0
11150 // [ 7: 0] : luma_byh_hx / [15: 8] : sat_byhs_s0hx
11151 // [23:16] : sat_byhs_s0hx / [31:24] : sat_byhs_s2hx
11152 #define REG_CM2_ENH_COEFF1_H04 0x121 // default 32'H0
11153 // [ 7: 0] : hue_byh_hx / [15: 8] : hue_byy_y0hx
11154 // [23:16] : hue_byy_y1hx / [31:24] : hue_byy_y2hx
11155 #define REG_CM2_ENH_COEFF2_H04 0x122 // default 32'H0
11156 // [ 7: 0] : hue_byy_y3hx / [15: 8] : hue_byy_y4hx
11157 // [23:16] : hue_bys_s0hx / [31:24] : hue_bys_s1hx
11158 #define REG_CM2_ENH_COEFF3_H04 0x123 // default 32'H0
11159 // [ 7: 0] : hue_bys_s2hx / [15: 8] : hue_bys_s3hx
11160 // [23:16] : hue_bys_s4hx / [31:24] : hue_byya_y0hx
11161 #define REG_CM2_ENH_COEFF4_H04 0x124 // default 32'H0
11162 // [ 7: 0] : hue_byya_y1hx / [15: 8] : hue_byya_y2hx
11163 // [23:16] : hue_byya_y3hx / [31:24] : hue_byya_y4hx
11164
11165 ////========= NODE 5 COEFFICIENT ==============////
11166
11167 #define REG_CM2_ENH_COEFF0_H05 0x128 // default 32'H0
11168 // [ 7: 0] : luma_byh_hx / [15: 8] : sat_byhs_s0hx
11169 // [23:16] : sat_byhs_s0hx / [31:24] : sat_byhs_s2hx
11170 #define REG_CM2_ENH_COEFF1_H05 0x129 // default 32'H0
11171 // [ 7: 0] : hue_byh_hx / [15: 8] : hue_byy_y0hx
11172 // [23:16] : hue_byy_y1hx / [31:24] : hue_byy_y2hx
11173 #define REG_CM2_ENH_COEFF2_H05 0x12a // default 32'H0
11174 // [ 7: 0] : hue_byy_y3hx / [15: 8] : hue_byy_y4hx
11175 // [23:16] : hue_bys_s0hx / [31:24] : hue_bys_s1hx
11176 #define REG_CM2_ENH_COEFF3_H05 0x12b // default 32'H0
11177 // [ 7: 0] : hue_bys_s2hx / [15: 8] : hue_bys_s3hx
11178 // [23:16] : hue_bys_s4hx / [31:24] : hue_byya_y0hx
11179 #define REG_CM2_ENH_COEFF4_H05 0x12c // default 32'H0
11180 // [ 7: 0] : hue_byya_y1hx / [15: 8] : hue_byya_y2hx
11181 // [23:16] : hue_byya_y3hx / [31:24] : hue_byya_y4hx
11182
11183 ////========= NODE 6 COEFFICIENT ==============////
11184
11185 #define REG_CM2_ENH_COEFF0_H06 0x130 // default 32'H0
11186 // [ 7: 0] : luma_byh_hx / [15: 8] : sat_byhs_s0hx
11187 // [23:16] : sat_byhs_s0hx / [31:24] : sat_byhs_s2hx
11188 #define REG_CM2_ENH_COEFF1_H06 0x131 // default 32'H0
11189 // [ 7: 0] : hue_byh_hx / [15: 8] : hue_byy_y0hx
11190 // [23:16] : hue_byy_y1hx / [31:24] : hue_byy_y2hx
11191 #define REG_CM2_ENH_COEFF2_H06 0x132 // default 32'H0
11192 // [ 7: 0] : hue_byy_y3hx / [15: 8] : hue_byy_y4hx
11193 // [23:16] : hue_bys_s0hx / [31:24] : hue_bys_s1hx
11194 #define REG_CM2_ENH_COEFF3_H06 0x133 // default 32'H0
11195 // [ 7: 0] : hue_bys_s2hx / [15: 8] : hue_bys_s3hx
11196 // [23:16] : hue_bys_s4hx / [31:24] : hue_byya_y0hx
11197 #define REG_CM2_ENH_COEFF4_H06 0x134 // default 32'H0
11198 // [ 7: 0] : hue_byya_y1hx / [15: 8] : hue_byya_y2hx
11199 // [23:16] : hue_byya_y3hx / [31:24] : hue_byya_y4hx
11200
11201 ////========= NODE 7 COEFFICIENT ==============////
11202
11203 #define REG_CM2_ENH_COEFF0_H07 0x138 // default 32'H0
11204 // [ 7: 0] : luma_byh_hx / [15: 8] : sat_byhs_s0hx
11205 // [23:16] : sat_byhs_s0hx / [31:24] : sat_byhs_s2hx
11206 #define REG_CM2_ENH_COEFF1_H07 0x139 // default 32'H0
11207 // [ 7: 0] : hue_byh_hx / [15: 8] : hue_byy_y0hx
11208 // [23:16] : hue_byy_y1hx / [31:24] : hue_byy_y2hx
11209 #define REG_CM2_ENH_COEFF2_H07 0x13a // default 32'H0
11210 // [ 7: 0] : hue_byy_y3hx / [15: 8] : hue_byy_y4hx
11211 // [23:16] : hue_bys_s0hx / [31:24] : hue_bys_s1hx
11212 #define REG_CM2_ENH_COEFF3_H07 0x13b // default 32'H0
11213 // [ 7: 0] : hue_bys_s2hx / [15: 8] : hue_bys_s3hx
11214 // [23:16] : hue_bys_s4hx / [31:24] : hue_byya_y0hx
11215 #define REG_CM2_ENH_COEFF4_H07 0x13c // default 32'H0
11216 // [ 7: 0] : hue_byya_y1hx / [15: 8] : hue_byya_y2hx
11217 // [23:16] : hue_byya_y3hx / [31:24] : hue_byya_y4hx
11218
11219 ////========= NODE 8 COEFFICIENT ==============////
11220
11221 #define REG_CM2_ENH_COEFF0_H08 0x140 // default 32'H0
11222 // [ 7: 0] : luma_byh_hx / [15: 8] : sat_byhs_s0hx
11223 // [23:16] : sat_byhs_s0hx / [31:24] : sat_byhs_s2hx
11224 #define REG_CM2_ENH_COEFF1_H08 0x141 // default 32'H0
11225 // [ 7: 0] : hue_byh_hx / [15: 8] : hue_byy_y0hx
11226 // [23:16] : hue_byy_y1hx / [31:24] : hue_byy_y2hx
11227 #define REG_CM2_ENH_COEFF2_H08 0x142 // default 32'H0
11228 // [ 7: 0] : hue_byy_y3hx / [15: 8] : hue_byy_y4hx
11229 // [23:16] : hue_bys_s0hx / [31:24] : hue_bys_s1hx
11230 #define REG_CM2_ENH_COEFF3_H08 0x143 // default 32'H0
11231 // [ 7: 0] : hue_bys_s2hx / [15: 8] : hue_bys_s3hx
11232 // [23:16] : hue_bys_s4hx / [31:24] : hue_byya_y0hx
11233 #define REG_CM2_ENH_COEFF4_H08 0x144 // default 32'H0
11234 // [ 7: 0] : hue_byya_y1hx / [15: 8] : hue_byya_y2hx
11235 // [23:16] : hue_byya_y3hx / [31:24] : hue_byya_y4hx
11236
11237 ////========= NODE 9 COEFFICIENT ==============////
11238
11239 #define REG_CM2_ENH_COEFF0_H09 0x148 // default 32'H0
11240 // [ 7: 0] : luma_byh_hx / [15: 8] : sat_byhs_s0hx
11241 // [23:16] : sat_byhs_s0hx / [31:24] : sat_byhs_s2hx
11242 #define REG_CM2_ENH_COEFF1_H09 0x149 // default 32'H0
11243 // [ 7: 0] : hue_byh_hx / [15: 8] : hue_byy_y0hx
11244 // [23:16] : hue_byy_y1hx / [31:24] : hue_byy_y2hx
11245 #define REG_CM2_ENH_COEFF2_H09 0x14a // default 32'H0
11246 // [ 7: 0] : hue_byy_y3hx / [15: 8] : hue_byy_y4hx
11247 // [23:16] : hue_bys_s0hx / [31:24] : hue_bys_s1hx
11248 #define REG_CM2_ENH_COEFF3_H09 0x14b // default 32'H0
11249 // [ 7: 0] : hue_bys_s2hx / [15: 8] : hue_bys_s3hx
11250 // [23:16] : hue_bys_s4hx / [31:24] : hue_byya_y0hx
11251 #define REG_CM2_ENH_COEFF4_H09 0x14c // default 32'H0
11252 // [ 7: 0] : hue_byya_y1hx / [15: 8] : hue_byya_y2hx
11253 // [23:16] : hue_byya_y3hx / [31:24] : hue_byya_y4hx
11254
11255 ////========= NODE 10 COEFFICIENT ==============////
11256
11257 #define REG_CM2_ENH_COEFF0_H10 0x150 // default 32'H0
11258 // [ 7: 0] : luma_byh_hx / [15: 8] : sat_byhs_s0hx
11259 // [23:16] : sat_byhs_s0hx / [31:24] : sat_byhs_s2hx
11260 #define REG_CM2_ENH_COEFF1_H10 0x151 // default 32'H0
11261 // [ 7: 0] : hue_byh_hx / [15: 8] : hue_byy_y0hx
11262 // [23:16] : hue_byy_y1hx / [31:24] : hue_byy_y2hx
11263 #define REG_CM2_ENH_COEFF2_H10 0x152 // default 32'H0
11264 // [ 7: 0] : hue_byy_y3hx / [15: 8] : hue_byy_y4hx
11265 // [23:16] : hue_bys_s0hx / [31:24] : hue_bys_s1hx
11266 #define REG_CM2_ENH_COEFF3_H10 0x153 // default 32'H0
11267 // [ 7: 0] : hue_bys_s2hx / [15: 8] : hue_bys_s3hx
11268 // [23:16] : hue_bys_s4hx / [31:24] : hue_byya_y0hx
11269 #define REG_CM2_ENH_COEFF4_H10 0x154 // default 32'H0
11270 // [ 7: 0] : hue_byya_y1hx / [15: 8] : hue_byya_y2hx
11271 // [23:16] : hue_byya_y3hx / [31:24] : hue_byya_y4hx
11272
11273 ////========= NODE 11 COEFFICIENT ==============////
11274
11275 #define REG_CM2_ENH_COEFF0_H11 0x158 // default 32'H0
11276 // [ 7: 0] : luma_byh_hx / [15: 8] : sat_byhs_s0hx
11277 // [23:16] : sat_byhs_s0hx / [31:24] : sat_byhs_s2hx
11278 #define REG_CM2_ENH_COEFF1_H11 0x159 // default 32'H0
11279 // [ 7: 0] : hue_byh_hx / [15: 8] : hue_byy_y0hx
11280 // [23:16] : hue_byy_y1hx / [31:24] : hue_byy_y2hx
11281 #define REG_CM2_ENH_COEFF2_H11 0x15a // default 32'H0
11282 // [ 7: 0] : hue_byy_y3hx / [15: 8] : hue_byy_y4hx
11283 // [23:16] : hue_bys_s0hx / [31:24] : hue_bys_s1hx
11284 #define REG_CM2_ENH_COEFF3_H11 0x15b // default 32'H0
11285 // [ 7: 0] : hue_bys_s2hx / [15: 8] : hue_bys_s3hx
11286 // [23:16] : hue_bys_s4hx / [31:24] : hue_byya_y0hx
11287 #define REG_CM2_ENH_COEFF4_H11 0x15c // default 32'H0
11288 // [ 7: 0] : hue_byya_y1hx / [15: 8] : hue_byya_y2hx
11289 // [23:16] : hue_byya_y3hx / [31:24] : hue_byya_y4hx
11290
11291 ////========= NODE 12 COEFFICIENT ==============////
11292
11293 #define REG_CM2_ENH_COEFF0_H12 0x160 // default 32'H0
11294 // [ 7: 0] : luma_byh_hx / [15: 8] : sat_byhs_s0hx
11295 // [23:16] : sat_byhs_s0hx / [31:24] : sat_byhs_s2hx
11296 #define REG_CM2_ENH_COEFF1_H12 0x161 // default 32'H0
11297 // [ 7: 0] : hue_byh_hx / [15: 8] : hue_byy_y0hx
11298 // [23:16] : hue_byy_y1hx / [31:24] : hue_byy_y2hx
11299 #define REG_CM2_ENH_COEFF2_H12 0x162 // default 32'H0
11300 // [ 7: 0] : hue_byy_y3hx / [15: 8] : hue_byy_y4hx
11301 // [23:16] : hue_bys_s0hx / [31:24] : hue_bys_s1hx
11302 #define REG_CM2_ENH_COEFF3_H12 0x163 // default 32'H0
11303 // [ 7: 0] : hue_bys_s2hx / [15: 8] : hue_bys_s3hx
11304 // [23:16] : hue_bys_s4hx / [31:24] : hue_byya_y0hx
11305 #define REG_CM2_ENH_COEFF4_H12 0x164 // default 32'H0
11306 // [ 7: 0] : hue_byya_y1hx / [15: 8] : hue_byya_y2hx
11307 // [23:16] : hue_byya_y3hx / [31:24] : hue_byya_y4hx
11308
11309 ////========= NODE 13 COEFFICIENT ==============////
11310
11311 #define REG_CM2_ENH_COEFF0_H13 0x168 // default 32'H0
11312 // [ 7: 0] : luma_byh_hx / [15: 8] : sat_byhs_s0hx
11313 // [23:16] : sat_byhs_s0hx / [31:24] : sat_byhs_s2hx
11314 #define REG_CM2_ENH_COEFF1_H13 0x169 // default 32'H0
11315 // [ 7: 0] : hue_byh_hx / [15: 8] : hue_byy_y0hx
11316 // [23:16] : hue_byy_y1hx / [31:24] : hue_byy_y2hx
11317 #define REG_CM2_ENH_COEFF2_H13 0x16a // default 32'H0
11318 // [ 7: 0] : hue_byy_y3hx / [15: 8] : hue_byy_y4hx
11319 // [23:16] : hue_bys_s0hx / [31:24] : hue_bys_s1hx
11320 #define REG_CM2_ENH_COEFF3_H13 0x16b // default 32'H0
11321 // [ 7: 0] : hue_bys_s2hx / [15: 8] : hue_bys_s3hx
11322 // [23:16] : hue_bys_s4hx / [31:24] : hue_byya_y0hx
11323 #define REG_CM2_ENH_COEFF4_H13 0x16c // default 32'H0
11324 // [ 7: 0] : hue_byya_y1hx / [15: 8] : hue_byya_y2hx
11325 // [23:16] : hue_byya_y3hx / [31:24] : hue_byya_y4hx
11326
11327
11328 /* Constraints
11329 0)
11330 there are 16 regions totally. 8 regions are for hue adjustment, 8 regions are for sat adjustment.
11331 the hue range of the 16 regions can be set to overlap, but if overlap, the hue range(start and end) must be same.
11332 the 8 regions for hue adjustment should not overlap. if corresponding reg_hue_en_00 - 07 == 1
11333 the 8 regions for hue adjustment are defined by: (example are for region 0)
11334 a) hue:
11335 start: reg_hue_hue_shift_start_00[14:0]
11336 end:
11337 if reg_symmetry_en_00 == 0
11338 reg_hue_hue_shift_start_00[14:0] + (reg_hue_hue_shift_range_00[7:0]<<5)
11339 if reg_symmetry_en_00 == 1
11340 reg_hue_hue_shift_start_00[14:0] + (reg_hue_hue_shift_range_00[7:0]<<6)
11341 b) sat:
11342 start: reg_hue_sat_low_00
11343 end: reg_hue_sat_high_00
11344
11345 the 8 regions for sat adjustment should not overlap. if corresponding reg_sat_en_00 - 07 == 1
11346 the 8 regions for sat adjustment are defined by: (example are for region 0)
11347 a) hue: same as that for hue adjustment.
11348 start: reg_hue_hue_shift_start_00[14:0]
11349 end:
11350 if reg_symmetry_en_00 == 0
11351 reg_hue_hue_shift_start_00[14:0] + (reg_hue_hue_shift_range_00[7:0]<<5)
11352 if reg_symmetry_en_00 == 1
11353 reg_hue_hue_shift_start_00[14:0] + (reg_hue_hue_shift_range_00[7:0]<<6)
11354 b) sat:
11355 start: reg_sat_sat_low_00
11356 end: reg_sat_sat_high_00
11357
11358 1)
11359 reg_hue_hue_shift_range_00[7:0]:
11360 reg_hue_hue_shift_range_01[7:0]:
11361 reg_hue_hue_shift_range_02[7:0]:
11362 reg_hue_hue_shift_range_03[7:0]:
11363 reg_hue_hue_shift_range_04[7:0]:
11364 reg_hue_hue_shift_range_05[7:0]:
11365 reg_hue_hue_shift_range_06[7:0]:
11366 reg_hue_hue_shift_range_07[7:0]:
11367 must be greater or equal than 8'd8, so as reg_hue_range_inv_regxx can be represented by 0.0000_0000_xxxx_xxxx_xxxx_xxxx
11368
11369 2)
11370 all regions of 0-7 should meet below requirement. below is just an example for region 7.
11371 (reg_hue_lum_high_07 - reg_hue_lum_low_07) >=
11372 (1<<reg_hue_lum_low_slope_07) + (1<<reg_hue_lum_high_slope_07)
11373
11374 (reg_hue_sat_high_07 - reg_hue_sat_low_07) >=
11375 (1<<reg_hue_sat_low_slope_07) + (1<<reg_hue_sat_high_slope_07)
11376
11377 (reg_sat_lum_high_07 - reg_sat_lum_low_07) >=
11378 (1<<reg_sat_lum_low_slope_07) + (1<<reg_sat_lum_high_slope_07)
11379
11380 (reg_sat_sat_high_07 - reg_sat_sat_low_07) >=
11381 (1<<reg_sat_sat_low_slope_07) + (1<<reg_sat_sat_high_slope_07)
11382
11383 3)
11384 all of reg_hue_hue_shift_start_00[14:0] ~ 07[14:0] < 0x6000.
11385 only region 0 and 1 can exceed 360 degrees. ie:
11386 reg_hue_hue_shift_start_00 + (reg_hue_hue_shift_range_00<<5) can greater than 0x6000.
11387 reg_hue_hue_shift_start_01 + (reg_hue_hue_shift_range_01<<5) can greater than 0x6000.
11388 but below should be met:
11389 reg_hue_hue_shift_start_00 + (reg_hue_hue_shift_range_00<<5) < 0x8000. if reg_symmetry_en_00 == 0
11390 reg_hue_hue_shift_start_01 + (reg_hue_hue_shift_range_00<<5) < 0x8000. if reg_symmetry_en_00 == 0
11391 reg_hue_hue_shift_start_00 + (reg_hue_hue_shift_range_00<<6) < 0x8000. if reg_symmetry_en_00 == 1
11392 reg_hue_hue_shift_start_01 + (reg_hue_hue_shift_range_00<<6) < 0x8000. if reg_symmetry_en_00 == 1
11393
11394 others could not exceed 360 degrees. ie:
11395 reg_hue_hue_shift_start_02(to 7) + (reg_hue_hue_shift_range_02 (to 7) <<5) < 0x6000. if reg_symmetry_en_02 (to 7) == 0.
11396 reg_hue_hue_shift_start_02(to 7) + (reg_hue_hue_shift_range_02 (to 7) <<6) < 0x6000. if reg_symmetry_en_02 (to 7) == 1.
11397
11398 4)
11399 reg_hue_gain_00[7:0] <= 0x80.
11400 reg_hue_gain_01[7:0] <= 0x80.
11401 reg_hue_gain_02[7:0] <= 0x80.
11402 reg_hue_gain_03[7:0] <= 0x80.
11403 reg_hue_gain_04[7:0] <= 0x80.
11404 reg_hue_gain_05[7:0] <= 0x80.
11405 reg_hue_gain_06[7:0] <= 0x80.
11406 reg_hue_gain_07[7:0] <= 0x80.
11407
11408 5)
11409 below registers can only have two setting: 00 and 01.
11410 reg_hue_central_en_00[1:0] .. _07[1:0]
11411 reg_sat_central_en_00[1:0] .. _07[1:0]
11412
11413 6)
11414 all reg_..._slope_00-07 should not be greater than 7, ie: maximum value is 7.
11415 for example: below is for region 0:
11416 reg_hue_lum_low_slope_00[3:0] <= 7
11417 reg_hue_lum_high_slope_00[3:0] <= 7
11418 reg_hue_sat_low_slope_00[3:0] <= 7
11419 reg_hue_sat_high_slope_00[3:0] <= 7
11420 reg_sat_lum_low_slope_00[3:0] <= 7
11421 reg_sat_lum_high_slope_00[3:0] <= 7
11422 reg_sat_sat_low_slope_00[3:0] <= 7
11423 reg_sat_sat_high_slope_00[3:0] <= 7
11424 */
11425
11426 // synopsys translate_off
11427 // synopsys translate_on
11428 //
11429 // Closing file: chroma_reg.h
11430 //
11431 //(hsvsharp), (blue), gainoff, mat_vd1,mat_vd2, mat_post, prebld, postbld,(hsharp),sco_ff, vadj1, vadj2, ofifo, (chroma1), clk0(free_clk) vpp_reg
11432 //each item 2bits, for each 2bits, if bit 2*i+1 == 1, free clk, else if bit 2*i == 1 no clk, else auto gated clock
11433 //bit1 is not used, because I can not turn off vpp_reg clk because I can not turn on again
11434 //because the register itself canot be set again without clk
11435 //Bit 31:0
11436 #define VPP_GCLK_CTRL0 (0x1d72)
11437 #define P_VPP_GCLK_CTRL0 (volatile uint32_t *)((0x1d72 << 2) + 0xff900000)
11438 //(front_lti), (front_cti), Chroma2_filter, Chroma2, (Ccoring), (blackext), dnlp
11439 //Bit 13:0
11440 #define VPP_GCLK_CTRL1 (0x1d73)
11441 #define P_VPP_GCLK_CTRL1 (volatile uint32_t *)((0x1d73 << 2) + 0xff900000)
11442 //prehsc_clk, line_buf, prevsc, vsc, hsc_clk, clk0(free_clk)
11443 //Bit 11:0
11444 #define VPP_SC_GCLK_CTRL (0x1d74)
11445 #define P_VPP_SC_GCLK_CTRL (volatile uint32_t *)((0x1d74 << 2) + 0xff900000)
11446 //Bit 17:9 VD1 alpha for preblend
11447 //Bit 8:0 VD1 alpha for postblend
11448 #define VPP_MISC1 (0x1d76)
11449 #define P_VPP_MISC1 (volatile uint32_t *)((0x1d76 << 2) + 0xff900000)
11450 //Bit 31:0 super scalar clock control
11451 #define VPP_SRSCL_GCLK_CTRL (0x1d77)
11452 #define P_VPP_SRSCL_GCLK_CTRL (volatile uint32_t *)((0x1d77 << 2) + 0xff900000)
11453 //Bit 31:0 OSD super scalar clock control
11454 #define VPP_OSDSR_GCLK_CTRL (0x1d78)
11455 #define P_VPP_OSDSR_GCLK_CTRL (volatile uint32_t *)((0x1d78 << 2) + 0xff900000)
11456 //Bit 31:0 vvycc clock control
11457 #define VPP_XVYCC_GCLK_CTRL (0x1d79)
11458 #define P_VPP_XVYCC_GCLK_CTRL (volatile uint32_t *)((0x1d79 << 2) + 0xff900000)
11459 //Bit 31:24 blackext_start
11460 //Bit 23:16 blackext_slope1
11461 //Bit 15:8 blackext_midpt
11462 //Bit 7:0 blackext_slope2
11463 #define VPP_BLACKEXT_CTRL (0x1d80)
11464 #define P_VPP_BLACKEXT_CTRL (volatile uint32_t *)((0x1d80 << 2) + 0xff900000)
11465 //Bit 31:24 bottom of region03 output value
11466 //Bit 23:16 bottom of region02 output value
11467 //Bit 15:8 bottom of region01 output value
11468 //Bit 7:0 bottom of region00 output value
11469 #define VPP_DNLP_CTRL_00 (0x1d81)
11470 #define P_VPP_DNLP_CTRL_00 (volatile uint32_t *)((0x1d81 << 2) + 0xff900000)
11471 //Bit 31:24 bottom of region07 output value
11472 //Bit 23:16 bottom of region06 output value
11473 //Bit 15:8 bottom of region05 output value
11474 //Bit 7:0 bottom of region04 output value
11475 #define VPP_DNLP_CTRL_01 (0x1d82)
11476 #define P_VPP_DNLP_CTRL_01 (volatile uint32_t *)((0x1d82 << 2) + 0xff900000)
11477 //Bit 31:24 bottom of region11 output value
11478 //Bit 23:16 bottom of region10 output value
11479 //Bit 15:8 bottom of region09 output value
11480 //Bit 7:0 bottom of region08 output value
11481 #define VPP_DNLP_CTRL_02 (0x1d83)
11482 #define P_VPP_DNLP_CTRL_02 (volatile uint32_t *)((0x1d83 << 2) + 0xff900000)
11483 //Bit 31:24 bottom of region15 output value
11484 //Bit 23:16 bottom of region14 output value
11485 //Bit 15:8 bottom of region13 output value
11486 //Bit 7:0 bottom of region12 output value
11487 #define VPP_DNLP_CTRL_03 (0x1d84)
11488 #define P_VPP_DNLP_CTRL_03 (volatile uint32_t *)((0x1d84 << 2) + 0xff900000)
11489 //Bit 31:24 bottom of region19 output value
11490 //Bit 23:16 bottom of region18 output value
11491 //Bit 15:8 bottom of region17 output value
11492 //Bit 7:0 bottom of region16 output value
11493 #define VPP_DNLP_CTRL_04 (0x1d85)
11494 #define P_VPP_DNLP_CTRL_04 (volatile uint32_t *)((0x1d85 << 2) + 0xff900000)
11495 //Bit 31:24 bottom of region23 output value
11496 //Bit 23:16 bottom of region22 output value
11497 //Bit 15:8 bottom of region21 output value
11498 //Bit 7:0 bottom of region20 output value
11499 #define VPP_DNLP_CTRL_05 (0x1d86)
11500 #define P_VPP_DNLP_CTRL_05 (volatile uint32_t *)((0x1d86 << 2) + 0xff900000)
11501 //Bit 31:24 bottom of region27 output value
11502 //Bit 23:16 bottom of region26 output value
11503 //Bit 15:8 bottom of region25 output value
11504 //Bit 7:0 bottom of region24 output value
11505 #define VPP_DNLP_CTRL_06 (0x1d87)
11506 #define P_VPP_DNLP_CTRL_06 (volatile uint32_t *)((0x1d87 << 2) + 0xff900000)
11507 //Bit 31:24 bottom of region31 output value
11508 //Bit 23:16 bottom of region30 output value
11509 //Bit 15:8 bottom of region29 output value
11510 //Bit 7:0 bottom of region28 output value
11511 #define VPP_DNLP_CTRL_07 (0x1d88)
11512 #define P_VPP_DNLP_CTRL_07 (volatile uint32_t *)((0x1d88 << 2) + 0xff900000)
11513 //Bit 31:24 bottom of region35 output value
11514 //Bit 23:16 bottom of region34 output value
11515 //Bit 15:8 bottom of region33 output value
11516 //Bit 7:0 bottom of region32 output value
11517 #define VPP_DNLP_CTRL_08 (0x1d89)
11518 #define P_VPP_DNLP_CTRL_08 (volatile uint32_t *)((0x1d89 << 2) + 0xff900000)
11519 //Bit 31:24 bottom of region39 output value
11520 //Bit 23:16 bottom of region38 output value
11521 //Bit 15:8 bottom of region37 output value
11522 //Bit 7:0 bottom of region36 output value
11523 #define VPP_DNLP_CTRL_09 (0x1d8a)
11524 #define P_VPP_DNLP_CTRL_09 (volatile uint32_t *)((0x1d8a << 2) + 0xff900000)
11525 //Bit 31:24 bottom of region43 output value
11526 //Bit 23:16 bottom of region42 output value
11527 //Bit 15:8 bottom of region41 output value
11528 //Bit 7:0 bottom of region40 output value
11529 #define VPP_DNLP_CTRL_10 (0x1d8b)
11530 #define P_VPP_DNLP_CTRL_10 (volatile uint32_t *)((0x1d8b << 2) + 0xff900000)
11531 //Bit 31:24 bottom of region47 output value
11532 //Bit 23:16 bottom of region46 output value
11533 //Bit 15:8 bottom of region45 output value
11534 //Bit 7:0 bottom of region44 output value
11535 #define VPP_DNLP_CTRL_11 (0x1d8c)
11536 #define P_VPP_DNLP_CTRL_11 (volatile uint32_t *)((0x1d8c << 2) + 0xff900000)
11537 //Bit 31:24 bottom of region51 output value
11538 //Bit 23:16 bottom of region50 output value
11539 //Bit 15:8 bottom of region49 output value
11540 //Bit 7:0 bottom of region48 output value
11541 #define VPP_DNLP_CTRL_12 (0x1d8d)
11542 #define P_VPP_DNLP_CTRL_12 (volatile uint32_t *)((0x1d8d << 2) + 0xff900000)
11543 //Bit 31:24 bottom of region55 output value
11544 //Bit 23:16 bottom of region54 output value
11545 //Bit 15:8 bottom of region53 output value
11546 //Bit 7:0 bottom of region52 output value
11547 #define VPP_DNLP_CTRL_13 (0x1d8e)
11548 #define P_VPP_DNLP_CTRL_13 (volatile uint32_t *)((0x1d8e << 2) + 0xff900000)
11549 //Bit 31:24 bottom of region59 output value
11550 //Bit 23:16 bottom of region58 output value
11551 //Bit 15:8 bottom of region57 output value
11552 //Bit 7:0 bottom of region56 output value
11553 #define VPP_DNLP_CTRL_14 (0x1d8f)
11554 #define P_VPP_DNLP_CTRL_14 (volatile uint32_t *)((0x1d8f << 2) + 0xff900000)
11555 //Bit 31:24 bottom of region63 output value
11556 //Bit 23:16 bottom of region62 output value
11557 //Bit 15:8 bottom of region61 output value
11558 //Bit 7:0 bottom of region60 output value
11559 #define VPP_DNLP_CTRL_15 (0x1d90)
11560 #define P_VPP_DNLP_CTRL_15 (volatile uint32_t *)((0x1d90 << 2) + 0xff900000)
11561 // `define VPP_PEAKING_HGAIN 8'h91 //32'h0
11562 // `define VPP_PEAKING_VGAIN 8'h92 //32'h0
11563 // `define VPP_PEAKING_NLP_1 8'h93 //32'h0
11564 // `define VPP_PEAKING_NLP_2 8'h94 //32'h0
11565 // `define VPP_PEAKING_NLP_3 8'h95 //32'h0
11566 // `define VPP_PEAKING_NLP_4 8'h96 //32'h0
11567 // `define VPP_PEAKING_NLP_5 8'h97 //32'h0
11568 // `define VPP_SHARP_LIMIT 8'h98 //32'h0
11569 // `define VPP_VLTI_CTRL 8'h99 //32'h0
11570 // `define VPP_HLTI_CTRL 8'h9a //32'h0
11571 // `define VPP_CTI_CTRL 8'h9b //32'h0
11572 #define VPP_SRSHARP0_CTRL (0x1d91)
11573 #define P_VPP_SRSHARP0_CTRL (volatile uint32_t *)((0x1d91 << 2) + 0xff900000)
11574 //Bit 31:29 reserved
11575 //Bit 28:16 srsharp_demo_split_sz srsharp demo top/bot left/right width
11576 //Bit 15:6 reserved
11577 //Bit 5:4 srsharp_demo_disp_post srsharp demo display postion
11578 //Bit 3 srsharp_demo_en srsharp demo enable
11579 //Bit 2 srsharp_c444to422_en srsharp format444 convert 422 enable
11580 //Bit 1, srsharp_buf_en srsharp buffer enable
11581 //Bit 0, srsharp_en srsharp enable
11582 #define VPP_SRSHARP1_CTRL (0x1d92)
11583 #define P_VPP_SRSHARP1_CTRL (volatile uint32_t *)((0x1d92 << 2) + 0xff900000)
11584 //Bit 31:29 reserved
11585 //Bit 28:16 srsharp_demo_split_sz srsharp demo top/bot left/right width
11586 //Bit 15:6 reserved
11587 //Bit 5:4 srsharp_demo_disp_post srsharp demo display postion
11588 //Bit 3 srsharp_demo_en srsharp demo enable
11589 //Bit 2 srsharp_c444to422_en srsharp format444 convert 422 enable
11590 //Bit 1, srsharp_buf_en srsharp buffer enable
11591 //Bit 0, srsharp_en srsharp enable
11592 #define VPP_DOLBY_CTRL (0x1d93)
11593 #define P_VPP_DOLBY_CTRL (volatile uint32_t *)((0x1d93 << 2) + 0xff900000)
11594 //todo
11595 #define VPP_DAT_CONV_PARA0 (0x1d94)
11596 #define P_VPP_DAT_CONV_PARA0 (volatile uint32_t *)((0x1d94 << 2) + 0xff900000)
11597 #define VPP_DAT_CONV_PARA1 (0x1d95)
11598 #define P_VPP_DAT_CONV_PARA1 (volatile uint32_t *)((0x1d95 << 2) + 0xff900000)
11599 //todo
11600 #define VPP_SYNC_SEL0 (0x1d96)
11601 #define P_VPP_SYNC_SEL0 (volatile uint32_t *)((0x1d96 << 2) + 0xff900000)
11602 #define VPP_VADJ1_BLACK_VAL (0x1d97)
11603 #define P_VPP_VADJ1_BLACK_VAL (volatile uint32_t *)((0x1d97 << 2) + 0xff900000)
11604 #define VPP_VADJ2_BLACK_VAL (0x1d98)
11605 #define P_VPP_VADJ2_BLACK_VAL (volatile uint32_t *)((0x1d98 << 2) + 0xff900000)
11606 //Bit 29 blue_stretch_cb_inc
11607 //Bit 28 blue_stretch_cr_inc
11608 //Bit 27 the MSB of blue_stretch_error_crp_inv[11:0]
11609 //Bit 26 the MSB of blue_stretch_error_crn_inv[11:0]
11610 //Bit 25 the MSB of blue_stretch_error_cbp_inv[11:0]
11611 //Bit 24 the MSB of blue_stretch_error_cbn_inv[11:0]
11612 //Bit 23:16 blue_stretch_gain
11613 //Bit 15:8 blue_stretch_gain_cb4cr
11614 //Bit 7:0 blue_stretch_luma_high
11615 #define VPP_BLUE_STRETCH_1 (0x1d9c)
11616 #define P_VPP_BLUE_STRETCH_1 (volatile uint32_t *)((0x1d9c << 2) + 0xff900000)
11617 //Bit 31:27 blue_stretch_error_crp
11618 //Bit 26:16 the 11 LSB of blue_stretch_error_crp_inv[11:0]
11619 //Bit 15:11 blue_stretch_error_crn
11620 //Bit 10:0 the 11 LSB of blue_stretch_error_crn_inv[11:0]
11621 #define VPP_BLUE_STRETCH_2 (0x1d9d)
11622 #define P_VPP_BLUE_STRETCH_2 (volatile uint32_t *)((0x1d9d << 2) + 0xff900000)
11623 //Bit 31:27 blue_stretch_error_cbp
11624 //Bit 26:16 the 11 LSB of blue_stretch_error_cbp_inv[11:0]
11625 //Bit 15:11 blue_stretch_error_cbn
11626 //Bit 10:0 the 11 LSB of blue_stretch_error_cbn_inv[11:0]
11627 #define VPP_BLUE_STRETCH_3 (0x1d9e)
11628 #define P_VPP_BLUE_STRETCH_3 (volatile uint32_t *)((0x1d9e << 2) + 0xff900000)
11629 //Bit 25:16 bypass_ccoring_ythd
11630 //Bit 15:8, Chroma coring threshold
11631 //Bit 3:0, Chroma coring slope
11632 #define VPP_CCORING_CTRL (0x1da0)
11633 #define P_VPP_CCORING_CTRL (volatile uint32_t *)((0x1da0 << 2) + 0xff900000)
11634 //Bit 20 demo chroma coring enable
11635 //Bit 19 demo black enxtension enable
11636 //Bit 18 demo dynamic nonlinear luma processing enable
11637 //Bit 17 demo hsvsharp enable
11638 //Bit 16 demo bluestretch enable
11639 //Bit 15:14, 2'b00: demo adjust on top, 2'b01: demo adjust on bottom, 2'b10: demo adjust on left, 2'b11: demo adjust on right
11640 //Bit 4 chroma coring enable
11641 //Bit 3 black enxtension enable
11642 //Bit 2 dynamic nonlinear luma processing enable
11643 //Bit 1 hsvsharp enable
11644 //Bit 0 bluestretch enable
11645 #define VPP_VE_ENABLE_CTRL (0x1da1)
11646 #define P_VPP_VE_ENABLE_CTRL (volatile uint32_t *)((0x1da1 << 2) + 0xff900000)
11647 //Bit 12:0, demo left or top screen width
11648 #define VPP_VE_DEMO_LEFT_TOP_SCREEN_WIDTH (0x1da2)
11649 #define P_VPP_VE_DEMO_LEFT_TOP_SCREEN_WIDTH (volatile uint32_t *)((0x1da2 << 2) + 0xff900000)
11650 #define VPP_VE_DEMO_CENTER_BAR (0x1da3)
11651 #define P_VPP_VE_DEMO_CENTER_BAR (volatile uint32_t *)((0x1da3 << 2) + 0xff900000)
11652 //28:16 ve_line_length
11653 //12:0 ve_pic_height
11654 #define VPP_VE_H_V_SIZE (0x1da4)
11655 #define P_VPP_VE_H_V_SIZE (volatile uint32_t *)((0x1da4 << 2) + 0xff900000)
11656 //28:16 vppout_line_length
11657 //12:0 vppout_pic_height
11658 #define VPP_OUT_H_V_SIZE (0x1da5)
11659 #define P_VPP_OUT_H_V_SIZE (volatile uint32_t *)((0x1da5 << 2) + 0xff900000)
11660 //28:16 vppin_line_length
11661 //12:0 vppin_pic_height
11662 #define VPP_IN_H_V_SIZE (0x1da6)
11663 #define P_VPP_IN_H_V_SIZE (volatile uint32_t *)((0x1da6 << 2) + 0xff900000)
11664 //Bit 10 reset bit, high active
11665 //Bit 9 0: measuring rising edge, 1: measuring falling edge
11666 //Bit 8 if true, accumulate the counter number, otherwise not
11667 //Bit 7:0 vsync_span, define how many vsync span need to measure
11668 #define VPP_VDO_MEAS_CTRL (0x1da8)
11669 #define P_VPP_VDO_MEAS_CTRL (volatile uint32_t *)((0x1da8 << 2) + 0xff900000)
11670 //Read only
11671 //19:16 ind_meas_count_n, every number of sync_span vsyncs, this counter add 1
11672 //15:0, high bit portion of counter
11673 #define VPP_VDO_MEAS_VS_COUNT_HI (0x1da9)
11674 #define P_VPP_VDO_MEAS_VS_COUNT_HI (volatile uint32_t *)((0x1da9 << 2) + 0xff900000)
11675 //Read only
11676 //31:0, low bit portion of counter
11677 #define VPP_VDO_MEAS_VS_COUNT_LO (0x1daa)
11678 #define P_VPP_VDO_MEAS_VS_COUNT_LO (volatile uint32_t *)((0x1daa << 2) + 0xff900000)
11679 //bit 11:9 vd2_sel, 001: select vd1_din, 010: select vd2_din, 011: select d2d3_l_din, 100: d2d3_r_din, otherwise no selection
11680 //bit 8:6 vd1_l_sel, 001: select vd1_din, 010: select vd2_din, 011: select d2d3_l_din, 100: d2d3_r_din, otherwise no selection
11681 //bit 5:3 vd1_r_sel, 001: select vd1_din, 010: select vd2_din, 011: select d2d3_l_din, 100: d2d3_r_din, otherwise no selection
11682 //note: the source vd1_l_sel selected cannot be used as the source of vd1_r_sel or vd2_sel
11683 // vd1_r_sel is useful only vd1_interleave_mode is not 00. And the source vd1_r_sel used can not used for the vd2_sel any more.
11684 //bit 2:0 vd1_interleave_mode, 000: no interleave, 001: pixel interleaving, 010: line interleaving, 011: 2 pixel interleaving,
11685 // 100: 2 line interleaving
11686 #define VPP_INPUT_CTRL (0x1dab)
11687 #define P_VPP_INPUT_CTRL (volatile uint32_t *)((0x1dab << 2) + 0xff900000)
11688 //bit 25:24 cti_bpf_sel
11689 //bit 20:16 cti_blend_factor_gama
11690 //bit 12:8 cti_blend_factor_beta
11691 //bit 4:0 cti_blend_factor_alpha
11692 #define VPP_CTI_CTRL2 (0x1dac)
11693 #define P_VPP_CTI_CTRL2 (volatile uint32_t *)((0x1dac << 2) + 0xff900000)
11694 #define VPP_PEAKING_SAT_THD1 (0x1dad)
11695 #define P_VPP_PEAKING_SAT_THD1 (volatile uint32_t *)((0x1dad << 2) + 0xff900000)
11696 #define VPP_PEAKING_SAT_THD2 (0x1dae)
11697 #define P_VPP_PEAKING_SAT_THD2 (volatile uint32_t *)((0x1dae << 2) + 0xff900000)
11698 #define VPP_PEAKING_SAT_THD3 (0x1daf)
11699 #define P_VPP_PEAKING_SAT_THD3 (volatile uint32_t *)((0x1daf << 2) + 0xff900000)
11700 #define VPP_PEAKING_SAT_THD4 (0x1db0)
11701 #define P_VPP_PEAKING_SAT_THD4 (volatile uint32_t *)((0x1db0 << 2) + 0xff900000)
11702 #define VPP_PEAKING_SAT_THD5 (0x1db1)
11703 #define P_VPP_PEAKING_SAT_THD5 (volatile uint32_t *)((0x1db1 << 2) + 0xff900000)
11704 #define VPP_PEAKING_SAT_THD6 (0x1db2)
11705 #define P_VPP_PEAKING_SAT_THD6 (volatile uint32_t *)((0x1db2 << 2) + 0xff900000)
11706 #define VPP_PEAKING_SAT_THD7 (0x1db3)
11707 #define P_VPP_PEAKING_SAT_THD7 (volatile uint32_t *)((0x1db3 << 2) + 0xff900000)
11708 #define VPP_PEAKING_SAT_THD8 (0x1db4)
11709 #define P_VPP_PEAKING_SAT_THD8 (volatile uint32_t *)((0x1db4 << 2) + 0xff900000)
11710 #define VPP_PEAKING_SAT_THD9 (0x1db5)
11711 #define P_VPP_PEAKING_SAT_THD9 (volatile uint32_t *)((0x1db5 << 2) + 0xff900000)
11712 #define VPP_PEAKING_GAIN_ADD1 (0x1db6)
11713 #define P_VPP_PEAKING_GAIN_ADD1 (volatile uint32_t *)((0x1db6 << 2) + 0xff900000)
11714 #define VPP_PEAKING_GAIN_ADD2 (0x1db7)
11715 #define P_VPP_PEAKING_GAIN_ADD2 (volatile uint32_t *)((0x1db7 << 2) + 0xff900000)
11716 //bit 23:16 peaking_dnlp_gain, u5.3, DNLP effect
11717 //bit 15:8 peaking_factor
11718 //bit 5 peaking_dnlp_demo_en
11719 //bit 4 peaking_dnlp_en
11720 //bit 3:0 peaking_filter_sel
11721 #define VPP_PEAKING_DNLP (0x1db8)
11722 #define P_VPP_PEAKING_DNLP (volatile uint32_t *)((0x1db8 << 2) + 0xff900000)
11723 //bit 24 sharp_demo_win_en
11724 //bit 23:12 sharp_demo_win_vend
11725 //bit 11:0 sharp_demo_win_vstart
11726 #define VPP_SHARP_DEMO_WIN_CTRL1 (0x1db9)
11727 #define P_VPP_SHARP_DEMO_WIN_CTRL1 (volatile uint32_t *)((0x1db9 << 2) + 0xff900000)
11728 //bit 23:12 sharp_demo_win_hend
11729 //bit 11:0 sharp_demo_win_hstart
11730 #define VPP_SHARP_DEMO_WIN_CTRL2 (0x1dba)
11731 #define P_VPP_SHARP_DEMO_WIN_CTRL2 (volatile uint32_t *)((0x1dba << 2) + 0xff900000)
11732 //Bit 31:24 front_hlti_neg_gain
11733 //Bit 23:16 front_hlti_pos_gain
11734 //Bit 15:8 front_hlti_threshold
11735 //Bit 7:0 front_hlti_blend_factor
11736 #define VPP_FRONT_HLTI_CTRL (0x1dbb)
11737 #define P_VPP_FRONT_HLTI_CTRL (volatile uint32_t *)((0x1dbb << 2) + 0xff900000)
11738 //Bit 31 front_enable, enable the front LTI&CTI before scaler
11739 //Bit 26:24 front_cti_step2
11740 //Bit 23:21 front_cti_step
11741 //Bit 20:16 front_cti_blend_factor
11742 //Bit 15 front_cti_median_mode
11743 //Bit 14:8 front_cti_threshold
11744 //Bit 7:0 front_cti_gain
11745 #define VPP_FRONT_CTI_CTRL (0x1dbc)
11746 #define P_VPP_FRONT_CTI_CTRL (volatile uint32_t *)((0x1dbc << 2) + 0xff900000)
11747 //bit 29:28 front_hlti_step
11748 //bit 25:24 front_cti_bpf_sel
11749 //bit 20:16 front_cti_blend_factor_gama
11750 //bit 12:8 front_cti_blend_factor_beta
11751 //bit 4:0 front_cti_blend_factor_alpha
11752 #define VPP_FRONT_CTI_CTRL2 (0x1dbd)
11753 #define P_VPP_FRONT_CTI_CTRL2 (volatile uint32_t *)((0x1dbd << 2) + 0xff900000)
11754 //vertical scaler phase step
11755 //Bit 27:0, 4.24 format
11756 #define VPP_OSD_VSC_PHASE_STEP (0x1dc0)
11757 #define P_VPP_OSD_VSC_PHASE_STEP (volatile uint32_t *)((0x1dc0 << 2) + 0xff900000)
11758 //Bit 31:16, botttom vertical scaler initial phase
11759 //Bit 15:0, top vertical scaler initial phase
11760 #define VPP_OSD_VSC_INI_PHASE (0x1dc1)
11761 #define P_VPP_OSD_VSC_INI_PHASE (volatile uint32_t *)((0x1dc1 << 2) + 0xff900000)
11762 //Bit 24 osd vertical Scaler enable
11763 //Bit 23 osd_prog_interlace 0: current field is progressive, 1: current field is interlace
11764 //Bit 22:21 osd_vsc_double_line_mode, bit1, double input width and half input height, bit0, change line buffer becomes 2 lines
11765 //Bit 20 osd_vsc_phase0_always_en
11766 //Bit 19 osd_vsc_nearest_en
11767 //Bit 17:16 osd_vsc_bot_rpt_l0_num
11768 //Bit 14:11 osd_vsc_bot_ini_rcv_num
11769 //Bit 9:8 osd_vsc_top_rpt_l0_num
11770 //Bit 6:3 osd_vsc_top_ini_rcv_num
11771 //Bit 2:0 osd_vsc_bank_length
11772 #define VPP_OSD_VSC_CTRL0 (0x1dc2)
11773 #define P_VPP_OSD_VSC_CTRL0 (volatile uint32_t *)((0x1dc2 << 2) + 0xff900000)
11774 //horizontal scaler phase step
11775 //Bit 27:0, 4.24 format
11776 #define VPP_OSD_HSC_PHASE_STEP (0x1dc3)
11777 #define P_VPP_OSD_HSC_PHASE_STEP (volatile uint32_t *)((0x1dc3 << 2) + 0xff900000)
11778 //Bit 31:16, horizontal scaler initial phase1
11779 //Bit 15:0, horizontal scaler initial phase0
11780 #define VPP_OSD_HSC_INI_PHASE (0x1dc4)
11781 #define P_VPP_OSD_HSC_INI_PHASE (volatile uint32_t *)((0x1dc4 << 2) + 0xff900000)
11782 //Bit 22 osd horizontal scaler enable
11783 //Bit 21 osd_hsc_double_pix_mode
11784 //Bit 20 osd_hsc_phase0_always_en
11785 //Bit 19 osd_hsc_nearest_en
11786 //Bit 17:16 osd_hsc_rpt_p0_num1
11787 //Bit 14:11 osd_hsc_ini_rcv_num1
11788 //Bit 9:8 osd_hsc_rpt_p0_num0
11789 //Bit 6:3 osd_hsc_ini_rcv_num0
11790 //Bit 2:0 osd_hsc_bank_length
11791 #define VPP_OSD_HSC_CTRL0 (0x1dc5)
11792 #define P_VPP_OSD_HSC_CTRL0 (volatile uint32_t *)((0x1dc5 << 2) + 0xff900000)
11793 //for 3D quincunx sub-sampling
11794 //bit 15:8 pattern, each patten 1 bit, from lsb -> msb
11795 //bit 6:4 pattern start
11796 //bit 2:0 pattern end
11797 #define VPP_OSD_HSC_INI_PAT_CTRL (0x1dc6)
11798 #define P_VPP_OSD_HSC_INI_PAT_CTRL (volatile uint32_t *)((0x1dc6 << 2) + 0xff900000)
11799 //bit 31:24, componet 0
11800 //bit 23:16, component 1
11801 //bit 15:8, component 2
11802 //bit 7:0 component 3, alpha
11803 #define VPP_OSD_SC_DUMMY_DATA (0x1dc7)
11804 #define P_VPP_OSD_SC_DUMMY_DATA (volatile uint32_t *)((0x1dc7 << 2) + 0xff900000)
11805 //Bit 14 osc_sc_din_osd1_alpha_mode, 1: (alpha >= 128) ? alpha -1: alpha, 0: (alpha >=1) ? alpha - 1: alpha.
11806 //Bit 13 osc_sc_din_osd2_alpha_mode, 1: (alpha >= 128) ? alpha -1: alpha, 0: (alpha >=1) ? alpha - 1: alpha.
11807 //Bit 12 osc_sc_dout_alpha_mode, 1: (alpha >= 128) ? alpha + 1: alpha, 0: (alpha >=1) ? alpha + 1: alpha.
11808 //Bit 12 osc_sc_alpha_mode, 1: (alpha >= 128) ? alpha + 1: alpha, 0: (alpha >=1) ? alpha + 1: alpha.
11809 //Bit 11:4 default alpha for vd1 or vd2 if they are selected as the source
11810 //Bit 3 osd scaler path enable
11811 //Bit 1:0 osd_sc_sel, 00: select osd1 input, 01: select osd2 input, 10: select vd1 input, 11: select vd2 input after matrix
11812 #define VPP_OSD_SC_CTRL0 (0x1dc8)
11813 #define P_VPP_OSD_SC_CTRL0 (volatile uint32_t *)((0x1dc8 << 2) + 0xff900000)
11814 //Bit 28:16 OSD scaler input width minus 1
11815 //Bit 12:0 OSD scaler input height minus 1
11816 #define VPP_OSD_SCI_WH_M1 (0x1dc9)
11817 #define P_VPP_OSD_SCI_WH_M1 (volatile uint32_t *)((0x1dc9 << 2) + 0xff900000)
11818 //Bit 28:16 OSD scaler output horizontal start
11819 //Bit 12:0 OSD scaler output horizontal end
11820 #define VPP_OSD_SCO_H_START_END (0x1dca)
11821 #define P_VPP_OSD_SCO_H_START_END (volatile uint32_t *)((0x1dca << 2) + 0xff900000)
11822 //Bit 28:16 OSD scaler output vertical start
11823 //Bit 12:0 OSD scaler output vertical end
11824 #define VPP_OSD_SCO_V_START_END (0x1dcb)
11825 #define P_VPP_OSD_SCO_V_START_END (volatile uint32_t *)((0x1dcb << 2) + 0xff900000)
11826 //Because there are many coefficients used in the vertical filter and horizontal filters,
11827 //indirect access the coefficients of vertical filter and horizontal filter is used.
11828 //For vertical filter, there are 33x4 coefficients
11829 //For horizontal filter, there are 33x4 coefficients
11830 //Bit 15 index increment, if bit9 == 1 then (0: index increase 1, 1: index increase 2) else (index increase 2)
11831 //Bit 14 1: read coef through cbus enable, just for debug purpose in case when we wanna check the coef in ram in correct or not
11832 //Bit 9 if true, use 9bit resolution coef, other use 8bit resolution coef
11833 //Bit 8 type of index, 0: vertical coef, 1: horizontal coef
11834 //Bit 6:0 coef index
11835 #define VPP_OSD_SCALE_COEF_IDX (0x1dcc)
11836 #define P_VPP_OSD_SCALE_COEF_IDX (volatile uint32_t *)((0x1dcc << 2) + 0xff900000)
11837 //coefficients for vertical filter and horizontal filter
11838 #define VPP_OSD_SCALE_COEF (0x1dcd)
11839 #define P_VPP_OSD_SCALE_COEF (volatile uint32_t *)((0x1dcd << 2) + 0xff900000)
11840 //Bit 12:0 line number use to generate interrupt when line == this number
11841 #define VPP_INT_LINE_NUM (0x1dce)
11842 #define P_VPP_INT_LINE_NUM (volatile uint32_t *)((0x1dce << 2) + 0xff900000)
11843 #define VPP_XVYCC_MISC (0x1dcf)
11844 #define P_VPP_XVYCC_MISC (volatile uint32_t *)((0x1dcf << 2) + 0xff900000)
11845 // new add lti/cti in 120924
11846 //Bit 3: 0 //default== 0 reg_hlti_dn_flt_coe[0]
11847 //Bit 7: 4 //default== 0 reg_hlti_dn_flt_coe[1]
11848 //Bit 11: 8 //default== 0 reg_hlti_dn_flt_coe[2]
11849 //Bit 15:12 //default== 2 reg_hlti_dn_flt_coe[3]
11850 //Bit 19:16 //default== 4 reg_hlti_dn_flt_coe[4]
11851 //Bit 22:20 //default== 3 reg_hlti_dn_flt_nrm u3: 3~7
11852 #define VPP_HLTI_DN_FLT (0x1dd0)
11853 #define P_VPP_HLTI_DN_FLT (volatile uint32_t *)((0x1dd0 << 2) + 0xff900000)
11854 //Bit 7: 0 //default== 8 reg_hlti_bst_gain u8, norm 16 as "1"
11855 //Bit 15: 8 //default== 20 reg_hlti_bst_core u8, norm 32 as "1"
11856 //Bit 23:16 //default== 32 reg_hlti_oob_gain u8, norm 32 as "1"
11857 //Bit 28:24 //default== 0 reg_hlti_oob_core u5
11858 #define VPP_HLTI_GAIN (0x1dd1)
11859 #define P_VPP_HLTI_GAIN (volatile uint32_t *)((0x1dd1 << 2) + 0xff900000)
11860 //Bit 7: 0 //default== 2 reg_hlti_clp_ofst u8,
11861 //Bit 8 //default== 0 reg_hlti_clp_mode u1,
11862 //Bit 11: 9 //default== 1 reg_hlti_clp_wind u3,
11863 //Bit 14:12 //default== 1 reg_hlti_bst_fltr u3,
11864 //Bit 15 //default== 1 reg_hlti_enable u1,
11865 #define VPP_HLTI_PARA (0x1dd2)
11866 #define P_VPP_HLTI_PARA (volatile uint32_t *)((0x1dd2 << 2) + 0xff900000)
11867 //Bit 3: 0 //default== 0 reg_hcti_dn_flt_coe[0]
11868 //Bit 7: 4 //default== 0 reg_hcti_dn_flt_coe[1]
11869 //Bit 11: 8 //default== 1 reg_hcti_dn_flt_coe[2]
11870 //Bit 15:12 //default== 2 reg_hcti_dn_flt_coe[3]
11871 //Bit 19:16 //default== 2 reg_hcti_dn_flt_coe[4]
11872 //Bit 22:20 //default== 3 reg_hcti_dn_flt_nrm u3: 3~7
11873 #define VPP_HCTI_DN_FLT (0x1dd3)
11874 #define P_VPP_HCTI_DN_FLT (volatile uint32_t *)((0x1dd3 << 2) + 0xff900000)
11875 //Bit 7: 0 //default== 48 reg_hcti_bst_gain u8, norm 16 as "1"
11876 //Bit15: 8 //default== 17 reg_hcti_bst_core u8, norm 32 as "1"
11877 //Bit23:16 //default== 16 reg_hcti_oob_gain u8, norm 32 as "1"
11878 //Bit28:24 //default== 0 reg_hcti_oob_core u5
11879 #define VPP_HCTI_GAIN (0x1dd4)
11880 #define P_VPP_HCTI_GAIN (volatile uint32_t *)((0x1dd4 << 2) + 0xff900000)
11881 //Bit 7: 0 //default== 0 reg_hcti_clp_ofst u8,
11882 //Bit 8 //default== 1 reg_hcti_clp_mode u1,
11883 //Bit 11: 9 //default== 3 reg_hcti_clp_wind u3,
11884 //Bit 14:12 //default== 6 reg_hcti_bst_fltr u3,
11885 //Bit 15 //default== 1 reg_hcti_enable u1,
11886 #define VPP_HCTI_PARA (0x1dd5)
11887 #define P_VPP_HCTI_PARA (volatile uint32_t *)((0x1dd5 << 2) + 0xff900000)
11888 //Bit 7: 0 //default== 48 reg_vcti_bst_gain u8, normalize 16 as "1"
11889 //Bit 15: 8 //default== 10 reg_vcti_bst_core u8
11890 //Bit 19:16 //default== 10 reg_vcti_clp_ofst u4
11891 //Bit 20 //default== 1 reg_vcti_clp_wind u1, 0: wind 3, 1: wind5
11892 #define VPP_VCTI_PARA (0x1dd6)
11893 #define P_VPP_VCTI_PARA (volatile uint32_t *)((0x1dd6 << 2) + 0xff900000)
11894 //`define VPP_MATRIX_PROBE_COLOR1 8'hd7 //defined before
11895 //Bit 31 //default== 0, urgent fifo hold enable
11896 //Bit 28:12 //default== 0, urgent fifo hold line threshold
11897 //Bit 15 //default== 0, urgent_ctrl_en
11898 //Bit 14 //default== 0, urgent_wr, if true for write buffer
11899 //Bit 13 //default== 0, out_inv_en
11900 //Bit 12 //default == 0, urgent_ini_value
11901 //Bit 11:6 //default == 0, up_th up threshold
11902 //Bit 5:0 //default == 0, dn_th dn threshold
11903 #define VPP_OFIFO_URG_CTRL (0x1dd8)
11904 #define P_VPP_OFIFO_URG_CTRL (volatile uint32_t *)((0x1dd8 << 2) + 0xff900000)
11905 #define VPP_CLIP_MISC0 (0x1dd9)
11906 #define P_VPP_CLIP_MISC0 (volatile uint32_t *)((0x1dd9 << 2) + 0xff900000)
11907 //Bit 29:20 // default == 1023, final clip r channel top
11908 //Bit 19:10 // default == 1023, final clip g channel top
11909 //Bit 9: 0 // default == 1023, final clip b channel top
11910 #define VPP_CLIP_MISC1 (0x1dda)
11911 #define P_VPP_CLIP_MISC1 (volatile uint32_t *)((0x1dda << 2) + 0xff900000)
11912 //Bit 29:20 // default == 0, final clip r channel bottom
11913 //Bit 19:10 // default == 0, final clip g channel bottom
11914 //Bit 9: 0 // default == 0, final clip b channel bottom
11915 #define VPP_MATRIX_COEF13_14 (0x1ddb)
11916 #define P_VPP_MATRIX_COEF13_14 (volatile uint32_t *)((0x1ddb << 2) + 0xff900000)
11917 //Bit 28:16 // default == 0, matrix coef13
11918 //Bit 12:0 // default == 0, matrix coef14
11919 #define VPP_MATRIX_COEF23_24 (0x1ddc)
11920 #define P_VPP_MATRIX_COEF23_24 (volatile uint32_t *)((0x1ddc << 2) + 0xff900000)
11921 //Bit 28:16 // default == 0, matrix coef23
11922 //Bit 12:0 // default == 0, matrix coef24
11923 #define VPP_MATRIX_COEF15_25 (0x1ddd)
11924 #define P_VPP_MATRIX_COEF15_25 (volatile uint32_t *)((0x1ddd << 2) + 0xff900000)
11925 //Bit 28:16 // default == 0, matrix coef15
11926 //Bit 12:0 // default == 0, matrix coef25
11927 #define VPP_MATRIX_CLIP (0x1dde)
11928 #define P_VPP_MATRIX_CLIP (volatile uint32_t *)((0x1dde << 2) + 0xff900000)
11929 //Bit 7:5 // default == 0, mat rs
11930 //Bit 4:3 // default == 0, mat clmod
11931 //Bit 2:0 // default == 0, mat clip enable
11932 #define VPP_XVYCC_MISC0 (0x1ddf)
11933 #define P_VPP_XVYCC_MISC0 (volatile uint32_t *)((0x1ddf << 2) + 0xff900000)
11934 //Bit 29:20 // default == 1023, xvycc clip r channel top
11935 //Bit 19:10 // default == 1023, xvycc clip g channel top
11936 //Bit 9: 0 // default == 1023, xvycc clip b channel top
11937 #define VPP_XVYCC_MISC1 (0x1de0)
11938 #define P_VPP_XVYCC_MISC1 (volatile uint32_t *)((0x1de0 << 2) + 0xff900000)
11939 //Bit 29:20 // default == 0, xvycc clip r channel bottom
11940 //Bit 19:10 // default == 0, xvycc clip g channel bottom
11941 //Bit 9: 0 // default == 0, xvycc clip b channel bottom
11942 #define VPP_VD1_CLIP_MISC0 (0x1de1)
11943 #define P_VPP_VD1_CLIP_MISC0 (volatile uint32_t *)((0x1de1 << 2) + 0xff900000)
11944 //Bit 29:20 // default == 1023, vd1 clip r channel top
11945 //Bit 19:10 // default == 1023, vd1 clip g channel top
11946 //Bit 9: 0 // default == 1023, vd1 clip b channel top
11947 #define VPP_VD1_CLIP_MISC1 (0x1de2)
11948 #define P_VPP_VD1_CLIP_MISC1 (volatile uint32_t *)((0x1de2 << 2) + 0xff900000)
11949 //Bit 29:20 // default == 0, vd1 clip r channel bottom
11950 //Bit 19:10 // default == 0, vd1 clip g channel bottom
11951 //Bit 9: 0 // default == 0, vd1 clip b channel bottom
11952 #define VPP_VD2_CLIP_MISC0 (0x1de3)
11953 #define P_VPP_VD2_CLIP_MISC0 (volatile uint32_t *)((0x1de3 << 2) + 0xff900000)
11954 //Bit 29:20 // default == 1023, vd2 clip r channel top
11955 //Bit 19:10 // default == 1023, vd2 clip g channel top
11956 //Bit 9: 0 // default == 1023, vd2 clip b channel top
11957 #define VPP_VD2_CLIP_MISC1 (0x1de4)
11958 #define P_VPP_VD2_CLIP_MISC1 (volatile uint32_t *)((0x1de4 << 2) + 0xff900000)
11959 //Bit 29:20 // default == 0, vd2 clip r channel bottom
11960 //Bit 19:10 // default == 0, vd2 clip g channel bottom
11961 //Bit 9: 0 // default == 0, vd2 clip b channel bottom
11962 // synopsys translate_off
11963 // synopsys translate_on
11964 //
11965 // Closing file: vpp_regs.h
11966 //
11967 //`define VIU2_VCBUS_BASE 8'h1e
11968 //
11969 // Reading file: v2regs.h
11970 //
11971 // synopsys translate_off
11972 // synopsys translate_on
11973 //===========================================================================
11974 // Video Interface 2 Registers 0xe00 - 0xeff
11975 //===========================================================================
11976 // -----------------------------------------------
11977 // CBUS_BASE: VIU2_VCBUS_BASE = 0x1e
11978 // -----------------------------------------------
11979 #define VIU2_ADDR_START (0x1e00)
11980 #define P_VIU2_ADDR_START (volatile uint32_t *)((0x1e00 << 2) + 0xff900000)
11981 #define VIU2_ADDR_END (0x1eff)
11982 #define P_VIU2_ADDR_END (volatile uint32_t *)((0x1eff << 2) + 0xff900000)
11983 //------------------------------------------------------------------------------
11984 // VIU2 top-level registers
11985 //------------------------------------------------------------------------------
11986 // Bit 0 RW, osd1_reset
11987 // Bit 1 RW, osd2_reset
11988 // Bit 2 RW, vd1_reset
11989 // Bit 3 RW, vd1_fmt_reset
11990 // Bit 7 RW, vpp_reset
11991 #define VIU2_SW_RESET (0x1e01)
11992 #define P_VIU2_SW_RESET (volatile uint32_t *)((0x1e01 << 2) + 0xff900000)
11993 #define VIU2_SW_RESET0 (0x1e02)
11994 #define P_VIU2_SW_RESET0 (volatile uint32_t *)((0x1e02 << 2) + 0xff900000)
11995 // Bit 0 RW, software reset for mcvecrd_mif
11996 // Bit 1 RW, software reset for mcinfowr_mif
11997 // Bit 2 RW, software reset for mcinford_mif
11998 //bit 8 if true, vsync interrup is generate only field == 0
11999 //bit 7:0 fix_disable
12000 #define VIU2_MISC_CTRL0 (0x1e06)
12001 #define P_VIU2_MISC_CTRL0 (volatile uint32_t *)((0x1e06 << 2) + 0xff900000)
12002 //------------------------------------------------------------------------------
12003 // OSD1 registers
12004 //------------------------------------------------------------------------------
12005 // Bit 31 Reserved
12006 // Bit 30 RW, enable_free_clk: 1=use free-running clock to drive logics;
12007 // 0=use gated clock for low power.
12008 // Bit 29 R, test_rd_dsr
12009 // Bit 28 R, osd_done
12010 // Bit 27:24 R, osd_blk_mode
12011 // Bit 23:22 R, osd_blk_ptr
12012 // Bit 21 R, osd_enable
12013 //
12014 // Bit 20:12 RW, global_alpha
12015 // Bit 11 RW, test_rd_en
12016 // Bit 10: 9 Reserved for control signals
12017 // Bit 8: 5 RW, ctrl_mtch_y
12018 // Bit 4 RW, ctrl_422to444
12019 // Bit 3: 0 RW, osd_blk_enable. Bit 0 to enable block 0: 1=enable, 0=disable;
12020 // Bit 1 to enable block 1, and so on.
12021 #define VIU2_OSD1_CTRL_STAT (0x1e10)
12022 #define P_VIU2_OSD1_CTRL_STAT (volatile uint32_t *)((0x1e10 << 2) + 0xff900000)
12023 // Bit 31:26 Reserved
12024 // Bit 25:16 R, fifo_count
12025 // Bit 15: 6 Reserved
12026 // Bit 5: 4 RW, hold_fifo_lines[6:5]
12027 // Bit 3 RW, rgb2yuv_full_range
12028 // Bit 2 RW, alpha_9b_mode
12029 // Bit 1 RW, reserved
12030 // Bit 0 RW, color_expand_mode
12031 #define VIU2_OSD1_CTRL_STAT2 (0x1e2d)
12032 #define P_VIU2_OSD1_CTRL_STAT2 (volatile uint32_t *)((0x1e2d << 2) + 0xff900000)
12033 // Bit 31: 9 Reserved
12034 // Bit 8 RW, 0 = Write LUT, 1 = Read LUT
12035 // Bit 7: 0 RW, lut_addr
12036 #define VIU2_OSD1_COLOR_ADDR (0x1e11)
12037 #define P_VIU2_OSD1_COLOR_ADDR (volatile uint32_t *)((0x1e11 << 2) + 0xff900000)
12038 // Bit 31:24 RW, Y or R
12039 // Bit 23:16 RW, Cb or G
12040 // Bit 15: 8 RW, Cr or B
12041 // Bit 7: 0 RW, Alpha
12042 #define VIU2_OSD1_COLOR (0x1e12)
12043 #define P_VIU2_OSD1_COLOR (volatile uint32_t *)((0x1e12 << 2) + 0xff900000)
12044 // Bit 31:24 RW, Y or R
12045 // Bit 23:16 RW, Cb or G
12046 // Bit 15: 8 RW, Cr or B
12047 // Bit 7: 0 RW, Alpha
12048 #define VIU2_OSD1_TCOLOR_AG0 (0x1e17)
12049 #define P_VIU2_OSD1_TCOLOR_AG0 (volatile uint32_t *)((0x1e17 << 2) + 0xff900000)
12050 #define VIU2_OSD1_TCOLOR_AG1 (0x1e18)
12051 #define P_VIU2_OSD1_TCOLOR_AG1 (volatile uint32_t *)((0x1e18 << 2) + 0xff900000)
12052 #define VIU2_OSD1_TCOLOR_AG2 (0x1e19)
12053 #define P_VIU2_OSD1_TCOLOR_AG2 (volatile uint32_t *)((0x1e19 << 2) + 0xff900000)
12054 #define VIU2_OSD1_TCOLOR_AG3 (0x1e1a)
12055 #define P_VIU2_OSD1_TCOLOR_AG3 (volatile uint32_t *)((0x1e1a << 2) + 0xff900000)
12056 // Bit 31:30 Reserved
12057 // Bit 29 RW, y_rev: 0=normal read, 1=reverse read in Y direction
12058 // Bit 28 RW, x_rev: 0=normal read, 1=reverse read in X direction
12059 // Bit 27:24 Reserved
12060 // Bit 23:16 RW, tbl_addr
12061 // Bit 15 RW, little_endian: 0=big endian, 1=little endian
12062 // Bit 14 RW, rpt_y
12063 // Bit 13:12 RW, interp_ctrl. 0x=No interpolation; 10=Interpolate with previous
12064 // pixel; 11=Interpolate with the average value
12065 // between previous and next pixel.
12066 // Bit 11: 8 RW, osd_blk_mode
12067 // Bit 7 RW, rgb_en
12068 // Bit 6 RW, tc_alpha_en
12069 // Bit 5: 2 RW, color_matrix
12070 // Bit 1 RW, interlace_en
12071 // Bit 0 RW, interlace_sel_odd
12072 #define VIU2_OSD1_BLK0_CFG_W0 (0x1e1b)
12073 #define P_VIU2_OSD1_BLK0_CFG_W0 (volatile uint32_t *)((0x1e1b << 2) + 0xff900000)
12074 #define VIU2_OSD1_BLK1_CFG_W0 (0x1e1f)
12075 #define P_VIU2_OSD1_BLK1_CFG_W0 (volatile uint32_t *)((0x1e1f << 2) + 0xff900000)
12076 #define VIU2_OSD1_BLK2_CFG_W0 (0x1e23)
12077 #define P_VIU2_OSD1_BLK2_CFG_W0 (volatile uint32_t *)((0x1e23 << 2) + 0xff900000)
12078 #define VIU2_OSD1_BLK3_CFG_W0 (0x1e27)
12079 #define P_VIU2_OSD1_BLK3_CFG_W0 (volatile uint32_t *)((0x1e27 << 2) + 0xff900000)
12080 // Bit 31:29 Reserved
12081 // Bit 28:16 RW, x_end
12082 // Bit 15:13 Reserved
12083 // Bit 12: 0 RW, x_start
12084 #define VIU2_OSD1_BLK0_CFG_W1 (0x1e1c)
12085 #define P_VIU2_OSD1_BLK0_CFG_W1 (volatile uint32_t *)((0x1e1c << 2) + 0xff900000)
12086 #define VIU2_OSD1_BLK1_CFG_W1 (0x1e20)
12087 #define P_VIU2_OSD1_BLK1_CFG_W1 (volatile uint32_t *)((0x1e20 << 2) + 0xff900000)
12088 #define VIU2_OSD1_BLK2_CFG_W1 (0x1e24)
12089 #define P_VIU2_OSD1_BLK2_CFG_W1 (volatile uint32_t *)((0x1e24 << 2) + 0xff900000)
12090 #define VIU2_OSD1_BLK3_CFG_W1 (0x1e28)
12091 #define P_VIU2_OSD1_BLK3_CFG_W1 (volatile uint32_t *)((0x1e28 << 2) + 0xff900000)
12092 // Bit 31:29 Reserved
12093 // Bit 28:16 RW, y_end
12094 // Bit 15:13 Reserved
12095 // Bit 12: 0 RW, y_start
12096 #define VIU2_OSD1_BLK0_CFG_W2 (0x1e1d)
12097 #define P_VIU2_OSD1_BLK0_CFG_W2 (volatile uint32_t *)((0x1e1d << 2) + 0xff900000)
12098 #define VIU2_OSD1_BLK1_CFG_W2 (0x1e21)
12099 #define P_VIU2_OSD1_BLK1_CFG_W2 (volatile uint32_t *)((0x1e21 << 2) + 0xff900000)
12100 #define VIU2_OSD1_BLK2_CFG_W2 (0x1e25)
12101 #define P_VIU2_OSD1_BLK2_CFG_W2 (volatile uint32_t *)((0x1e25 << 2) + 0xff900000)
12102 #define VIU2_OSD1_BLK3_CFG_W2 (0x1e29)
12103 #define P_VIU2_OSD1_BLK3_CFG_W2 (volatile uint32_t *)((0x1e29 << 2) + 0xff900000)
12104 // Bit 31:28 Reserved
12105 // Bit 27:16 RW, h_end
12106 // Bit 15:12 Reserved
12107 // Bit 11: 0 RW, h_start
12108 #define VIU2_OSD1_BLK0_CFG_W3 (0x1e1e)
12109 #define P_VIU2_OSD1_BLK0_CFG_W3 (volatile uint32_t *)((0x1e1e << 2) + 0xff900000)
12110 #define VIU2_OSD1_BLK1_CFG_W3 (0x1e22)
12111 #define P_VIU2_OSD1_BLK1_CFG_W3 (volatile uint32_t *)((0x1e22 << 2) + 0xff900000)
12112 #define VIU2_OSD1_BLK2_CFG_W3 (0x1e26)
12113 #define P_VIU2_OSD1_BLK2_CFG_W3 (volatile uint32_t *)((0x1e26 << 2) + 0xff900000)
12114 #define VIU2_OSD1_BLK3_CFG_W3 (0x1e2a)
12115 #define P_VIU2_OSD1_BLK3_CFG_W3 (volatile uint32_t *)((0x1e2a << 2) + 0xff900000)
12116 // Bit 31:28 Reserved
12117 // Bit 27:16 RW, v_end
12118 // Bit 15:12 Reserved
12119 // Bit 11: 0 RW, v_start
12120 #define VIU2_OSD1_BLK0_CFG_W4 (0x1e13)
12121 #define P_VIU2_OSD1_BLK0_CFG_W4 (volatile uint32_t *)((0x1e13 << 2) + 0xff900000)
12122 #define VIU2_OSD1_BLK1_CFG_W4 (0x1e14)
12123 #define P_VIU2_OSD1_BLK1_CFG_W4 (volatile uint32_t *)((0x1e14 << 2) + 0xff900000)
12124 #define VIU2_OSD1_BLK2_CFG_W4 (0x1e15)
12125 #define P_VIU2_OSD1_BLK2_CFG_W4 (volatile uint32_t *)((0x1e15 << 2) + 0xff900000)
12126 #define VIU2_OSD1_BLK3_CFG_W4 (0x1e16)
12127 #define P_VIU2_OSD1_BLK3_CFG_W4 (volatile uint32_t *)((0x1e16 << 2) + 0xff900000)
12128 // Bit 31 RW, burst_len_sel[2] of [2:0]
12129 // Bit 30 RW, byte_swap: In addition to endian control, further define
12130 // whether to swap upper and lower byte within a 16-bit mem word.
12131 // 0=No swap; 1=Swap data[15:0] to be {data[7:0], data[15:8]}
12132 // Bit 29 RW, div_swap : swap the 2 64bits words in 128 bit word
12133 // Bit 28:24 RW, fifo_lim : when osd fifo is small than the fifo_lim*16, closed the rq port of osd_rd_mif
12134 // Bit 23:22 RW, fifo_ctrl: 00 : for 1 word in 1 burst , 01 : for 2words in 1burst, 10: for 4words in 1burst, 11: reserved
12135 // Bit 21:20 R, fifo_st. 0=IDLE, 1=FILL, 2=ABORT
12136 // Bit 19 R, fifo_overflow
12137 //
12138 // Bit 18:12 RW, fifo_depth_val, max value=64: set actual fifo depth to fifo_depth_val*8.
12139 // Bit 11:10 RW, burst_len_sel[1:0] of [2:0]. 0=24(default), 1=32, 2=48, 3=64, 4=96, 5=128.
12140 // Bit 9: 5 RW, hold_fifo_lines[4:0]
12141 // Bit 4 RW, clear_err: one pulse to clear fifo_overflow
12142 // Bit 3 RW, fifo_sync_rst
12143 // Bit 2: 1 RW, endian
12144 // Bit 0 RW, urgent
12145 #define VIU2_OSD1_FIFO_CTRL_STAT (0x1e2b)
12146 #define P_VIU2_OSD1_FIFO_CTRL_STAT (volatile uint32_t *)((0x1e2b << 2) + 0xff900000)
12147 // Bit 31:24 R, Y or R
12148 // Bit 23:16 R, Cb or G
12149 // Bit 15: 8 R, Cr or B
12150 // Bit 7: 0 R, Output Alpha[8:1]
12151 #define VIU2_OSD1_TEST_RDDATA (0x1e2c)
12152 #define P_VIU2_OSD1_TEST_RDDATA (volatile uint32_t *)((0x1e2c << 2) + 0xff900000)
12153 // Bit 15 RW, prot_en: 1=Borrow PROT's FIFO storage, either for rotate or non-rotate.
12154 // Bit 12: 0 RW, effective FIFO size when prot_en=1.
12155 #define VIU2_OSD1_PROT_CTRL (0x1e2e)
12156 #define P_VIU2_OSD1_PROT_CTRL (volatile uint32_t *)((0x1e2e << 2) + 0xff900000)
12157 //------------------------------------------------------------------------------
12158 // OSD2 registers
12159 //------------------------------------------------------------------------------
12160 // Bit 31 Reserved
12161 // Bit 30 RW, enable_free_clk: 1=use free-running clock to drive logics;
12162 // 0=use gated clock for low power.
12163 // Bit 29 R, test_rd_dsr
12164 // Bit 28 R, osd_done
12165 // Bit 27:24 R, osd_blk_mode
12166 // Bit 23:22 R, osd_blk_ptr
12167 // Bit 21 R, osd_enable
12168 //
12169 // Bit 20:12 RW, global_alpha
12170 // Bit 11 RW, test_rd_en
12171 // Bit 10 RW, hl2_en
12172 // Bit 9 RW, hl1_en
12173 // Bit 8: 5 RW, ctrl_mtch_y
12174 // Bit 4 RW, ctrl_422to444
12175 // Bit 3: 0 RW, osd_blk_enable. Bit 0 to enable block 0: 1=enable, 0=disable;
12176 // Bit 1 to enable block 1, and so on.
12177 #define VIU2_OSD2_CTRL_STAT (0x1e30)
12178 #define P_VIU2_OSD2_CTRL_STAT (volatile uint32_t *)((0x1e30 << 2) + 0xff900000)
12179 // Bit 31:26 Reserved
12180 // Bit 25:16 R, fifo_count
12181 // Bit 15: 6 Reserved
12182 // Bit 5: 4 RW, hold_fifo_lines[6:5]
12183 // Bit 3 RW, rgb2yuv_full_range
12184 // Bit 2 RW, alpha_9b_mode
12185 // Bit 1 RW, reserved
12186 // Bit 0 RW, color_expand_mode
12187 #define VIU2_OSD2_CTRL_STAT2 (0x1e4d)
12188 #define P_VIU2_OSD2_CTRL_STAT2 (volatile uint32_t *)((0x1e4d << 2) + 0xff900000)
12189 // Bit 31: 9 Reserved
12190 // Bit 8 RW, 0 = Write LUT, 1 = Read LUT
12191 // Bit 7: 0 RW, lut_addr
12192 #define VIU2_OSD2_COLOR_ADDR (0x1e31)
12193 #define P_VIU2_OSD2_COLOR_ADDR (volatile uint32_t *)((0x1e31 << 2) + 0xff900000)
12194 // Bit 31:24 RW, Y or R
12195 // Bit 23:16 RW, Cb or G
12196 // Bit 15: 8 RW, Cr or B
12197 // Bit 7: 0 RW, Alpha
12198 #define VIU2_OSD2_COLOR (0x1e32)
12199 #define P_VIU2_OSD2_COLOR (volatile uint32_t *)((0x1e32 << 2) + 0xff900000)
12200 // Bit 31:28 Reserved
12201 // Bit 27:16 RW, hl[1-2]_h/v_start
12202 // Bit 15:12 Reserved
12203 // Bit 11: 0 RW, hl[1-2]_h/v_end
12204 #define VIU2_OSD2_HL1_H_START_END (0x1e33)
12205 #define P_VIU2_OSD2_HL1_H_START_END (volatile uint32_t *)((0x1e33 << 2) + 0xff900000)
12206 #define VIU2_OSD2_HL1_V_START_END (0x1e34)
12207 #define P_VIU2_OSD2_HL1_V_START_END (volatile uint32_t *)((0x1e34 << 2) + 0xff900000)
12208 #define VIU2_OSD2_HL2_H_START_END (0x1e35)
12209 #define P_VIU2_OSD2_HL2_H_START_END (volatile uint32_t *)((0x1e35 << 2) + 0xff900000)
12210 #define VIU2_OSD2_HL2_V_START_END (0x1e36)
12211 #define P_VIU2_OSD2_HL2_V_START_END (volatile uint32_t *)((0x1e36 << 2) + 0xff900000)
12212 // Bit 31:24 RW, Y or R
12213 // Bit 23:16 RW, Cb or G
12214 // Bit 15: 8 RW, Cr or B
12215 // Bit 7: 0 RW, Alpha
12216 #define VIU2_OSD2_TCOLOR_AG0 (0x1e37)
12217 #define P_VIU2_OSD2_TCOLOR_AG0 (volatile uint32_t *)((0x1e37 << 2) + 0xff900000)
12218 #define VIU2_OSD2_TCOLOR_AG1 (0x1e38)
12219 #define P_VIU2_OSD2_TCOLOR_AG1 (volatile uint32_t *)((0x1e38 << 2) + 0xff900000)
12220 #define VIU2_OSD2_TCOLOR_AG2 (0x1e39)
12221 #define P_VIU2_OSD2_TCOLOR_AG2 (volatile uint32_t *)((0x1e39 << 2) + 0xff900000)
12222 #define VIU2_OSD2_TCOLOR_AG3 (0x1e3a)
12223 #define P_VIU2_OSD2_TCOLOR_AG3 (volatile uint32_t *)((0x1e3a << 2) + 0xff900000)
12224 // Bit 31:24 Reserved
12225 // Bit 23:16 RW, tbl_addr
12226 // Bit 15 RW, little_endian: 0=big endian, 1=little endian
12227 // Bit 14 RW, rpt_y
12228 // Bit 13:12 RW, interp_ctrl. 0x=No interpolation; 10=Interpolate with previous
12229 // pixel; 11=Interpolate with the average value
12230 // between previous and next pixel.
12231 // Bit 11: 8 RW, osd_blk_mode
12232 // Bit 7 RW, rgb_en
12233 // Bit 6 RW, tc_alpha_en
12234 // Bit 5: 2 RW, color_matrix
12235 // Bit 1 RW, interlace_en
12236 // Bit 0 RW, interlace_sel_odd
12237 #define VIU2_OSD2_BLK0_CFG_W0 (0x1e3b)
12238 #define P_VIU2_OSD2_BLK0_CFG_W0 (volatile uint32_t *)((0x1e3b << 2) + 0xff900000)
12239 #define VIU2_OSD2_BLK1_CFG_W0 (0x1e3f)
12240 #define P_VIU2_OSD2_BLK1_CFG_W0 (volatile uint32_t *)((0x1e3f << 2) + 0xff900000)
12241 #define VIU2_OSD2_BLK2_CFG_W0 (0x1e43)
12242 #define P_VIU2_OSD2_BLK2_CFG_W0 (volatile uint32_t *)((0x1e43 << 2) + 0xff900000)
12243 #define VIU2_OSD2_BLK3_CFG_W0 (0x1e47)
12244 #define P_VIU2_OSD2_BLK3_CFG_W0 (volatile uint32_t *)((0x1e47 << 2) + 0xff900000)
12245 // Bit 31:29 Reserved
12246 // Bit 28:16 RW, x_end
12247 // Bit 15:13 Reserved
12248 // Bit 12: 0 RW, x_start
12249 #define VIU2_OSD2_BLK0_CFG_W1 (0x1e3c)
12250 #define P_VIU2_OSD2_BLK0_CFG_W1 (volatile uint32_t *)((0x1e3c << 2) + 0xff900000)
12251 #define VIU2_OSD2_BLK1_CFG_W1 (0x1e40)
12252 #define P_VIU2_OSD2_BLK1_CFG_W1 (volatile uint32_t *)((0x1e40 << 2) + 0xff900000)
12253 #define VIU2_OSD2_BLK2_CFG_W1 (0x1e44)
12254 #define P_VIU2_OSD2_BLK2_CFG_W1 (volatile uint32_t *)((0x1e44 << 2) + 0xff900000)
12255 #define VIU2_OSD2_BLK3_CFG_W1 (0x1e48)
12256 #define P_VIU2_OSD2_BLK3_CFG_W1 (volatile uint32_t *)((0x1e48 << 2) + 0xff900000)
12257 // Bit 31:29 Reserved
12258 // Bit 28:16 RW, y_end
12259 // Bit 15:13 Reserved
12260 // Bit 12: 0 RW, y_start
12261 #define VIU2_OSD2_BLK0_CFG_W2 (0x1e3d)
12262 #define P_VIU2_OSD2_BLK0_CFG_W2 (volatile uint32_t *)((0x1e3d << 2) + 0xff900000)
12263 #define VIU2_OSD2_BLK1_CFG_W2 (0x1e41)
12264 #define P_VIU2_OSD2_BLK1_CFG_W2 (volatile uint32_t *)((0x1e41 << 2) + 0xff900000)
12265 #define VIU2_OSD2_BLK2_CFG_W2 (0x1e45)
12266 #define P_VIU2_OSD2_BLK2_CFG_W2 (volatile uint32_t *)((0x1e45 << 2) + 0xff900000)
12267 #define VIU2_OSD2_BLK3_CFG_W2 (0x1e49)
12268 #define P_VIU2_OSD2_BLK3_CFG_W2 (volatile uint32_t *)((0x1e49 << 2) + 0xff900000)
12269 // Bit 31:28 Reserved
12270 // Bit 27:16 RW, h_end
12271 // Bit 15:12 Reserved
12272 // Bit 11: 0 RW, h_start
12273 #define VIU2_OSD2_BLK0_CFG_W3 (0x1e3e)
12274 #define P_VIU2_OSD2_BLK0_CFG_W3 (volatile uint32_t *)((0x1e3e << 2) + 0xff900000)
12275 #define VIU2_OSD2_BLK1_CFG_W3 (0x1e42)
12276 #define P_VIU2_OSD2_BLK1_CFG_W3 (volatile uint32_t *)((0x1e42 << 2) + 0xff900000)
12277 #define VIU2_OSD2_BLK2_CFG_W3 (0x1e46)
12278 #define P_VIU2_OSD2_BLK2_CFG_W3 (volatile uint32_t *)((0x1e46 << 2) + 0xff900000)
12279 #define VIU2_OSD2_BLK3_CFG_W3 (0x1e4a)
12280 #define P_VIU2_OSD2_BLK3_CFG_W3 (volatile uint32_t *)((0x1e4a << 2) + 0xff900000)
12281 // Bit 31:28 Reserved
12282 // Bit 27:16 RW, v_end
12283 // Bit 15:12 Reserved
12284 // Bit 11: 0 RW, v_start
12285 #define VIU2_OSD2_BLK0_CFG_W4 (0x1e64)
12286 #define P_VIU2_OSD2_BLK0_CFG_W4 (volatile uint32_t *)((0x1e64 << 2) + 0xff900000)
12287 #define VIU2_OSD2_BLK1_CFG_W4 (0x1e65)
12288 #define P_VIU2_OSD2_BLK1_CFG_W4 (volatile uint32_t *)((0x1e65 << 2) + 0xff900000)
12289 #define VIU2_OSD2_BLK2_CFG_W4 (0x1e66)
12290 #define P_VIU2_OSD2_BLK2_CFG_W4 (volatile uint32_t *)((0x1e66 << 2) + 0xff900000)
12291 #define VIU2_OSD2_BLK3_CFG_W4 (0x1e67)
12292 #define P_VIU2_OSD2_BLK3_CFG_W4 (volatile uint32_t *)((0x1e67 << 2) + 0xff900000)
12293 // Bit 31 RW, burst_len_sel[2] of [2:0]
12294 // Bit 30 RW, byte_swap: In addition to endian control, further define
12295 // whether to swap upper and lower byte within a 16-bit mem word.
12296 // 0=No swap; 1=Swap data[15:0] to be {data[7:0], data[15:8]}
12297 // Bit 29 RW, div_swap : swap the 2 64bits words in 128 bit word
12298 // Bit 28:24 RW, fifo_lim : when osd fifo is small than the fifo_lim*16, closed the rq port of osd_rd_mif
12299 // Bit 23:22 RW, fifo_ctrl: 00 : for 1 word in 1 burst , 01 : for 2words in 1burst, 10: for 4words in 1burst, 11: reserved
12300 // Bit 21:20 R, fifo_st. 0=IDLE, 1=FILL, 2=ABORT
12301 // Bit 19 R, fifo_overflow
12302 // Bit 18:12 RW, fifo_depth_val, max value=64: set actual fifo depth to fifo_depth_val*8.
12303 // Bit 11:10 RW, burst_len_sel[1:0] of [2:0]. 0=24(default), 1=32, 2=48, 3=64, 4=96, 5=128.
12304 // Bit 9: 5 RW, hold_fifo_lines[4:0]
12305 // Bit 4 RW, clear_err: one pulse to clear fifo_overflow
12306 // Bit 3 RW, fifo_sync_rst
12307 // Bit 2: 1 RW, endian
12308 // Bit 0 RW, urgent
12309 #define VIU2_OSD2_FIFO_CTRL_STAT (0x1e4b)
12310 #define P_VIU2_OSD2_FIFO_CTRL_STAT (volatile uint32_t *)((0x1e4b << 2) + 0xff900000)
12311 // Bit 31:24 R, Y or R
12312 // Bit 23:16 R, Cb or G
12313 // Bit 15: 8 R, Cr or B
12314 // Bit 7: 0 R, Output Alpha[8:1]
12315 #define VIU2_OSD2_TEST_RDDATA (0x1e4c)
12316 #define P_VIU2_OSD2_TEST_RDDATA (volatile uint32_t *)((0x1e4c << 2) + 0xff900000)
12317 // Bit 15 RW, prot_en: 1=Borrow PROT's FIFO storage, either for rotate or non-rotate.
12318 // Bit 12: 0 RW, effective FIFO size when prot_en=1.
12319 #define VIU2_OSD2_PROT_CTRL (0x1e4e)
12320 #define P_VIU2_OSD2_PROT_CTRL (volatile uint32_t *)((0x1e4e << 2) + 0xff900000)
12321 //------------------------------------------------------------------------------
12322 // VD1 path
12323 //------------------------------------------------------------------------------
12324 #define VIU2_VD1_IF0_GEN_REG (0x1e50)
12325 #define P_VIU2_VD1_IF0_GEN_REG (volatile uint32_t *)((0x1e50 << 2) + 0xff900000)
12326 #define VIU2_VD1_IF0_CANVAS0 (0x1e51)
12327 #define P_VIU2_VD1_IF0_CANVAS0 (volatile uint32_t *)((0x1e51 << 2) + 0xff900000)
12328 #define VIU2_VD1_IF0_CANVAS1 (0x1e52)
12329 #define P_VIU2_VD1_IF0_CANVAS1 (volatile uint32_t *)((0x1e52 << 2) + 0xff900000)
12330 #define VIU2_VD1_IF0_LUMA_X0 (0x1e53)
12331 #define P_VIU2_VD1_IF0_LUMA_X0 (volatile uint32_t *)((0x1e53 << 2) + 0xff900000)
12332 #define VIU2_VD1_IF0_LUMA_Y0 (0x1e54)
12333 #define P_VIU2_VD1_IF0_LUMA_Y0 (volatile uint32_t *)((0x1e54 << 2) + 0xff900000)
12334 #define VIU2_VD1_IF0_CHROMA_X0 (0x1e55)
12335 #define P_VIU2_VD1_IF0_CHROMA_X0 (volatile uint32_t *)((0x1e55 << 2) + 0xff900000)
12336 #define VIU2_VD1_IF0_CHROMA_Y0 (0x1e56)
12337 #define P_VIU2_VD1_IF0_CHROMA_Y0 (volatile uint32_t *)((0x1e56 << 2) + 0xff900000)
12338 #define VIU2_VD1_IF0_LUMA_X1 (0x1e57)
12339 #define P_VIU2_VD1_IF0_LUMA_X1 (volatile uint32_t *)((0x1e57 << 2) + 0xff900000)
12340 #define VIU2_VD1_IF0_LUMA_Y1 (0x1e58)
12341 #define P_VIU2_VD1_IF0_LUMA_Y1 (volatile uint32_t *)((0x1e58 << 2) + 0xff900000)
12342 #define VIU2_VD1_IF0_CHROMA_X1 (0x1e59)
12343 #define P_VIU2_VD1_IF0_CHROMA_X1 (volatile uint32_t *)((0x1e59 << 2) + 0xff900000)
12344 #define VIU2_VD1_IF0_CHROMA_Y1 (0x1e5a)
12345 #define P_VIU2_VD1_IF0_CHROMA_Y1 (volatile uint32_t *)((0x1e5a << 2) + 0xff900000)
12346 #define VIU2_VD1_IF0_RPT_LOOP (0x1e5b)
12347 #define P_VIU2_VD1_IF0_RPT_LOOP (volatile uint32_t *)((0x1e5b << 2) + 0xff900000)
12348 #define VIU2_VD1_IF0_LUMA0_RPT_PAT (0x1e5c)
12349 #define P_VIU2_VD1_IF0_LUMA0_RPT_PAT (volatile uint32_t *)((0x1e5c << 2) + 0xff900000)
12350 #define VIU2_VD1_IF0_CHROMA0_RPT_PAT (0x1e5d)
12351 #define P_VIU2_VD1_IF0_CHROMA0_RPT_PAT (volatile uint32_t *)((0x1e5d << 2) + 0xff900000)
12352 #define VIU2_VD1_IF0_LUMA1_RPT_PAT (0x1e5e)
12353 #define P_VIU2_VD1_IF0_LUMA1_RPT_PAT (volatile uint32_t *)((0x1e5e << 2) + 0xff900000)
12354 #define VIU2_VD1_IF0_CHROMA1_RPT_PAT (0x1e5f)
12355 #define P_VIU2_VD1_IF0_CHROMA1_RPT_PAT (volatile uint32_t *)((0x1e5f << 2) + 0xff900000)
12356 #define VIU2_VD1_IF0_LUMA_PSEL (0x1e60)
12357 #define P_VIU2_VD1_IF0_LUMA_PSEL (volatile uint32_t *)((0x1e60 << 2) + 0xff900000)
12358 #define VIU2_VD1_IF0_CHROMA_PSEL (0x1e61)
12359 #define P_VIU2_VD1_IF0_CHROMA_PSEL (volatile uint32_t *)((0x1e61 << 2) + 0xff900000)
12360 #define VIU2_VD1_IF0_DUMMY_PIXEL (0x1e62)
12361 #define P_VIU2_VD1_IF0_DUMMY_PIXEL (volatile uint32_t *)((0x1e62 << 2) + 0xff900000)
12362 #define VIU2_VD1_IF0_LUMA_FIFO_SIZE (0x1e63)
12363 #define P_VIU2_VD1_IF0_LUMA_FIFO_SIZE (volatile uint32_t *)((0x1e63 << 2) + 0xff900000)
12364 #define VIU2_VD1_IF0_RANGE_MAP_Y (0x1e6a)
12365 #define P_VIU2_VD1_IF0_RANGE_MAP_Y (volatile uint32_t *)((0x1e6a << 2) + 0xff900000)
12366 #define VIU2_VD1_IF0_RANGE_MAP_CB (0x1e6b)
12367 #define P_VIU2_VD1_IF0_RANGE_MAP_CB (volatile uint32_t *)((0x1e6b << 2) + 0xff900000)
12368 #define VIU2_VD1_IF0_RANGE_MAP_CR (0x1e6c)
12369 #define P_VIU2_VD1_IF0_RANGE_MAP_CR (volatile uint32_t *)((0x1e6c << 2) + 0xff900000)
12370 #define VIU2_VD1_IF0_GEN_REG2 (0x1e6d)
12371 #define P_VIU2_VD1_IF0_GEN_REG2 (volatile uint32_t *)((0x1e6d << 2) + 0xff900000)
12372 #define VIU2_VD1_IF0_PROT_CNTL (0x1e6e)
12373 #define P_VIU2_VD1_IF0_PROT_CNTL (volatile uint32_t *)((0x1e6e << 2) + 0xff900000)
12374 #define VIU2_VD1_IF0_URGENT_CTRL (0x1e6f)
12375 #define P_VIU2_VD1_IF0_URGENT_CTRL (volatile uint32_t *)((0x1e6f << 2) + 0xff900000)
12376 //Bit 31 it true, disable clock, otherwise enable clock
12377 //Bit 30 soft rst bit
12378 //Bit 28 if true, horizontal formatter use repeating to generete pixel, otherwise use bilinear interpolation
12379 //Bit 27:24 horizontal formatter initial phase
12380 //Bit 23 horizontal formatter repeat pixel 0 enable
12381 //Bit 22:21 horizontal Y/C ratio, 00: 1:1, 01: 2:1, 10: 4:1
12382 //Bit 20 horizontal formatter enable
12383 //Bit 19 if true, always use phase0 while vertical formater, meaning always
12384 // repeat data, no interpolation
12385 //Bit 18 if true, disable vertical formatter chroma repeat last line
12386 //Bit 17 veritcal formatter dont need repeat line on phase0, 1: enable, 0: disable
12387 //Bit 16 veritcal formatter repeat line 0 enable
12388 //Bit 15:12 vertical formatter skip line num at the beginning
12389 //Bit 11:8 vertical formatter initial phase
12390 //Bit 7:1 vertical formatter phase step (3.4)
12391 //Bit 0 vertical formatter enable
12392 #define VIU2_VD1_FMT_CTRL (0x1e68)
12393 #define P_VIU2_VD1_FMT_CTRL (volatile uint32_t *)((0x1e68 << 2) + 0xff900000)
12394 //Bit 27:16 horizontal formatter width
12395 //Bit 11:0 vertical formatter width
12396 #define VIU2_VD1_FMT_W (0x1e69)
12397 #define P_VIU2_VD1_FMT_W (volatile uint32_t *)((0x1e69 << 2) + 0xff900000)
12398 #define VIU2_VD1_IF0_GEN_REG3 (0x1e70)
12399 #define P_VIU2_VD1_IF0_GEN_REG3 (volatile uint32_t *)((0x1e70 << 2) + 0xff900000)
12400 //bit 31:1, reversed
12401 //bit 0, cntl_64bit_rev
12402 // synopsys translate_off
12403 // synopsys translate_on
12404 //
12405 // Closing file: v2regs.h
12406 //
12407 //`define VIUB_VCBUS_BASE 8'h20
12408 //
12409 // Reading file: vregs_clk1.h
12410 //
12411 //===========================================================================
12412 // Video Interface Registers 0xa00 - 0xaff
12413 //===========================================================================
12414 // -----------------------------------------------
12415 // CBUS_BASE: VIUB_VCBUS_BASE = 0x20
12416 // -----------------------------------------------
12417 #define VIUB_ADDR_START (0x2000)
12418 #define P_VIUB_ADDR_START (volatile uint32_t *)((0x2000 << 2) + 0xff900000)
12419 #define VIUB_ADDR_END (0x20ff)
12420 #define P_VIUB_ADDR_END (volatile uint32_t *)((0x20ff << 2) + 0xff900000)
12421 //`define TRACE_REG 8'ff
12422 //------------------------------------------------------------------------------
12423 // VIU top-level registers
12424 //------------------------------------------------------------------------------
12425 // Bit 0 RW, osd1_reset
12426 // Bit 1 RW, osd2_reset
12427 // Bit 2 RW, vd1_reset
12428 // Bit 3 RW, vd1_fmt_reset
12429 // Bit 4 RW, vd2_reset
12430 // Bit 5 RW, vd2_fmt_reset
12431 // Bit 6 RW, di_dsr1to2_reset
12432 // Bit 7 RW, vpp_reset
12433 // Bit 8 RW, di_if1_reset
12434 // Bit 9 RW, di_if1_fmt_reset
12435 // Bit 10 RW, di_inp_reset
12436 // Bit 11 RW, di_inp_fmt_reset
12437 // Bit 12 RW, di_mem_reset
12438 // Bit 13 RW, di_mem_fmt_reset
12439 // Bit 14 RW, di_nr_wr_mif_reset
12440 // Bit 15 RW, dein_wr_mif_reset
12441 // Bit 16 RW, di_chan2_mif_reset
12442 // Bit 17 RW, di_mtn_wr_mif_reset
12443 // Bit 18 RW, di_mtn_rd_mif_reset
12444 // Bit 19 RW, di_mad_reset
12445 // Bit 20 RW, vdin0_reset
12446 // Bit 21 RW, vdin1_reset
12447 // Bit 22 RW, nrin_mux_reset
12448 // Bit 23 RW, vdin0_wr_reset
12449 // Bit 24 RW, vdin1_wr_reset
12450 // Bit 25 RW, reserved
12451 // Bit 26 RW, d2d3_reset
12452 // Bit 27 RW, di_cont_wr_mif_reset
12453 // Bit 28 RW, di_cont_rd_mif_reset
12454 #define VIUB_SW_RESET (0x2001)
12455 #define P_VIUB_SW_RESET (volatile uint32_t *)((0x2001 << 2) + 0xff900000)
12456 #define VIUB_SW_RESET0 (0x2002)
12457 #define P_VIUB_SW_RESET0 (volatile uint32_t *)((0x2002 << 2) + 0xff900000)
12458 // Bit 0 RW, software reset for mcvecrd_mif
12459 // Bit 1 RW, software reset for mcinfowr_mif
12460 // Bit 2 RW, software reset for mcinford_mif
12461 //bit 8 if true, vsync interrup is generate only field == 0
12462 //bit 7:0 fix_disable
12463 #define VIUB_MISC_CTRL0 (0x2006)
12464 #define P_VIUB_MISC_CTRL0 (volatile uint32_t *)((0x2006 << 2) + 0xff900000)
12465 #define VIUB_GCLK_CTRL0 (0x2007)
12466 #define P_VIUB_GCLK_CTRL0 (volatile uint32_t *)((0x2007 << 2) + 0xff900000)
12467 //// gclk_ctrl0_gl[ 0] : def=1 di_top_wrap clk enable
12468 ////
12469 //// gclk_ctrl0_gl[ 8] : def=0 mad pre clock enable, from mad clock
12470 //// gclk_ctrl0_gl[ 9] : def=0 mad post clock enable, from mad clock
12471 //// gclk_ctrl0_gl[10] : def=0 div clock enable, di slow clock including di&mcdi
12472 //// gclk_ctrl0_gl[11] : def=0 mcdi clock enable, from div clock
12473 //// gclk_ctrl0_gl[12] : def=0 di post clock enable, from div clock
12474 //// gclk_ctrl0_gl[13] : def=0 reserved
12475 //// gclk_ctrl0_gl[14] : def=1 di_no_clk_gate, for old di
12476 //// gclk_ctrl0_gl[15] : def=0 di_gate_all, for old di
12477 #define VIUB_GCLK_CTRL1 (0x2008)
12478 #define P_VIUB_GCLK_CTRL1 (volatile uint32_t *)((0x2008 << 2) + 0xff900000)
12479 //// gclk_ctrl1_gl[ 1: 0] : def=2'b00 mif-sub-arb clock gate ctrl [1]: clock valid, [0]: clock close
12480 //// gclk_ctrl1_gl[ 3: 2] : def=2'b00 if1 rdmif clock gate ctrl [1]: clock valid, [0]: clock close
12481 //// gclk_ctrl1_gl[ 5: 4] : def=2'b00 if2 rdmif clock gate ctrl [1]: clock valid, [0]: clock close
12482 //// gclk_ctrl1_gl[ 7: 6] : def=2'b00 de wrmif clock gate ctrl [1]: clock valid, [0]: clock close
12483 //// gclk_ctrl1_gl[ 9: 8] : def=2'b00 mtnrd post mif clock gate ctrl [1]: clock valid, [0]: clock close
12484 //// gclk_ctrl1_gl[11:10] : def=2'b00 mcdi post mif clock gate ctrl [1]: clock valid, [0]: clock close
12485 //// gclk_ctrl1_gl[17:16] : def=2'b00 inp rdmif clock gate ctrl [1]: clock valid, [0]: clock close
12486 //// gclk_ctrl1_gl[19:18] : def=2'b00 mem rdmif clock gate ctrl [1]: clock valid, [0]: clock close
12487 //// gclk_ctrl1_gl[21:20] : def=2'b00 chan rdmif clock gate ctrl [1]: clock valid, [0]: clock close
12488 //// gclk_ctrl1_gl[23:22] : def=2'b00 nr wrmif clock gate ctrl [1]: clock valid, [0]: clock close
12489 //// gclk_ctrl1_gl[25:24] : def=2'b00 mtn mif clock gate ctrl [1]: clock valid, [0]: clock close
12490 //// gclk_ctrl1_gl[27:26] : def=2'b00 mcdi pre mif clock gate ctrl [1]: clock valid, [0]: clock close
12491 ////
12492 #define VIUB_GCLK_CTRL2 (0x2009)
12493 #define P_VIUB_GCLK_CTRL2 (volatile uint32_t *)((0x2009 << 2) + 0xff900000)
12494 //// gclk_ctrl_pre[ 1: 0] : def=2'b00 nr clock gate ctrl [1]: clock valid, [0]: clock close
12495 //// gclk_ctrl_pre[ 3: 2] : def=2'b00 pd clock gate ctrl [1]: clock valid, [0]: clock close
12496 //// gclk_ctrl_pre[ 5: 4] : def=2'b00 mtn det clock gate ctrl [1]: clock valid, [0]: clock close
12497 //// gclk_ctrl_pre[ 7: 6] : def=2'b00 debanding clock gate ctrl [1]: clock valid, [0]: clock close
12498 //// gclk_ctrl_pre[ 9: 8] : def=2'b00 dnr clock gate ctrl [1]: clock valid, [0]: clock close
12499 //// gclk_ctrl_pre[11:10] : def=2'b00 nr&dnr blend clock gate ctrl [1]: clock valid, [0]: clock close
12500 //// gclk_ctrl_pre[13:12] : def=2'b00 mcdi clock gate ctrl [1]: clock valid, [0]: clock close
12501 #define VIUB_GCLK_CTRL3 (0x200a)
12502 #define P_VIUB_GCLK_CTRL3 (volatile uint32_t *)((0x200a << 2) + 0xff900000)
12503 //// gclk_ctrl_post[ 1: 0] : def=2'b00 di blend clock gate ctrl [1]: clock valid, [0]: clock close
12504 //// gclk_ctrl_post[ 3: 2] : def=2'b00 ei clock gate ctrl [1]: clock valid, [0]: clock close
12505 //// gclk_ctrl_post[ 5: 4] : def=2'b00 ei_0 clock gate ctrl [1]: clock valid, [0]: clock close
12506 #define DI_IF2_GEN_REG (0x2010)
12507 #define P_DI_IF2_GEN_REG (volatile uint32_t *)((0x2010 << 2) + 0xff900000)
12508 #define DI_IF2_CANVAS0 (0x2011)
12509 #define P_DI_IF2_CANVAS0 (volatile uint32_t *)((0x2011 << 2) + 0xff900000)
12510 #define DI_IF2_LUMA_X0 (0x2012)
12511 #define P_DI_IF2_LUMA_X0 (volatile uint32_t *)((0x2012 << 2) + 0xff900000)
12512 #define DI_IF2_LUMA_Y0 (0x2013)
12513 #define P_DI_IF2_LUMA_Y0 (volatile uint32_t *)((0x2013 << 2) + 0xff900000)
12514 #define DI_IF2_CHROMA_X0 (0x2014)
12515 #define P_DI_IF2_CHROMA_X0 (volatile uint32_t *)((0x2014 << 2) + 0xff900000)
12516 #define DI_IF2_CHROMA_Y0 (0x2015)
12517 #define P_DI_IF2_CHROMA_Y0 (volatile uint32_t *)((0x2015 << 2) + 0xff900000)
12518 #define DI_IF2_RPT_LOOP (0x2016)
12519 #define P_DI_IF2_RPT_LOOP (volatile uint32_t *)((0x2016 << 2) + 0xff900000)
12520 #define DI_IF2_LUMA0_RPT_PAT (0x2017)
12521 #define P_DI_IF2_LUMA0_RPT_PAT (volatile uint32_t *)((0x2017 << 2) + 0xff900000)
12522 #define DI_IF2_CHROMA0_RPT_PAT (0x2018)
12523 #define P_DI_IF2_CHROMA0_RPT_PAT (volatile uint32_t *)((0x2018 << 2) + 0xff900000)
12524 #define DI_IF2_DUMMY_PIXEL (0x2019)
12525 #define P_DI_IF2_DUMMY_PIXEL (volatile uint32_t *)((0x2019 << 2) + 0xff900000)
12526 #define DI_IF2_LUMA_FIFO_SIZE (0x201a)
12527 #define P_DI_IF2_LUMA_FIFO_SIZE (volatile uint32_t *)((0x201a << 2) + 0xff900000)
12528 #define DI_IF2_RANGE_MAP_Y (0x201b)
12529 #define P_DI_IF2_RANGE_MAP_Y (volatile uint32_t *)((0x201b << 2) + 0xff900000)
12530 #define DI_IF2_RANGE_MAP_CB (0x201c)
12531 #define P_DI_IF2_RANGE_MAP_CB (volatile uint32_t *)((0x201c << 2) + 0xff900000)
12532 #define DI_IF2_RANGE_MAP_CR (0x201d)
12533 #define P_DI_IF2_RANGE_MAP_CR (volatile uint32_t *)((0x201d << 2) + 0xff900000)
12534 #define DI_IF2_GEN_REG2 (0x201e)
12535 #define P_DI_IF2_GEN_REG2 (volatile uint32_t *)((0x201e << 2) + 0xff900000)
12536 #define DI_IF2_FMT_CTRL (0x201f)
12537 #define P_DI_IF2_FMT_CTRL (volatile uint32_t *)((0x201f << 2) + 0xff900000)
12538 #define DI_IF2_FMT_W (0x2020)
12539 #define P_DI_IF2_FMT_W (volatile uint32_t *)((0x2020 << 2) + 0xff900000)
12540 #define DI_IF2_URGENT_CTRL (0x2021)
12541 #define P_DI_IF2_URGENT_CTRL (volatile uint32_t *)((0x2021 << 2) + 0xff900000)
12542 //bit15, auto enable; bit14, canvas write mode ;7:4, high threshold ;3:0 , low threshold for di inp chroma path
12543 //bit31, auto enable; bit30, canvas write mode ;23:20, high threshold ;19:16 , low threshold for di inp luma path
12544 #define DI_IF2_GEN_REG3 (0x2022)
12545 #define P_DI_IF2_GEN_REG3 (volatile uint32_t *)((0x2022 << 2) + 0xff900000)
12546 //bit 31:1, reversed
12547 //bit 0, cntl_64bit_rev
12548 #define DI_IF1_URGENT_CTRL (0x20a3)
12549 #define P_DI_IF1_URGENT_CTRL (volatile uint32_t *)((0x20a3 << 2) + 0xff900000)
12550 //bit15, auto enable; bit14, canvas write mode ;7:4, high threshold ;3:0 , low threshold for di inp chroma path
12551 //bit31, auto enable; bit30, canvas write mode ;23:20, high threshold ;19:16 , low threshold for di inp luma path
12552 #define DI_INP_URGENT_CTRL (0x20a4)
12553 #define P_DI_INP_URGENT_CTRL (volatile uint32_t *)((0x20a4 << 2) + 0xff900000)
12554 //bit15, auto enable; bit14, canvas write mode ;7:4, high threshold ;3:0 , low threshold for di mem chroma path
12555 //bit31, auto enable; bit30, canvas write mode ;23:20, high threshold ;19:16 , low threshold for di mem luma path
12556 #define DI_MEM_URGENT_CTRL (0x20a5)
12557 #define P_DI_MEM_URGENT_CTRL (volatile uint32_t *)((0x20a5 << 2) + 0xff900000)
12558 //bit15, auto enable; bit14, canvas write mode ;7:4, high threshold ;3:0 , low threshold for di chan2 chroma path
12559 //bit31, auto enable; bit30, canvas write mode ;23:20, high threshold ;19:16 , low threshold for di chan2 luma path
12560 #define DI_CHAN2_URGENT_CTRL (0x20a6)
12561 #define P_DI_CHAN2_URGENT_CTRL (volatile uint32_t *)((0x20a6 << 2) + 0xff900000)
12562 #define DI_IF1_GEN_REG3 (0x20a7)
12563 #define P_DI_IF1_GEN_REG3 (volatile uint32_t *)((0x20a7 << 2) + 0xff900000)
12564 //bit 31:1, reversed
12565 //bit 0, cntl_64bit_rev
12566 #define DI_INP_GEN_REG3 (0x20a8)
12567 #define P_DI_INP_GEN_REG3 (volatile uint32_t *)((0x20a8 << 2) + 0xff900000)
12568 //bit 31:1, reversed
12569 //bit 0, cntl_64bit_rev
12570 #define DI_MEM_GEN_REG3 (0x20a9)
12571 #define P_DI_MEM_GEN_REG3 (volatile uint32_t *)((0x20a9 << 2) + 0xff900000)
12572 //bit 31:1, reversed
12573 //bit 0, cntl_64bit_rev
12574 #define DI_CHAN2_GEN_REG3 (0x20aa)
12575 #define P_DI_CHAN2_GEN_REG3 (volatile uint32_t *)((0x20aa << 2) + 0xff900000)
12576 //bit 31:1, reversed
12577 //bit 0, cntl_64bit_rev
12578 //
12579 // Closing file: vregs_clk1.h
12580 //
12581 //======================================================================
12582 // vpu register.
12583 //======================================================================
12584 // -----------------------------------------------
12585 // CBUS_BASE: VPU_VCBUS_BASE = 0x27
12586 // -----------------------------------------------
12587 #define VPU_OSD1_MMC_CTRL (0x2701)
12588 #define P_VPU_OSD1_MMC_CTRL (volatile uint32_t *)((0x2701 << 2) + 0xff900000)
12589 #define VPU_OSD2_MMC_CTRL (0x2702)
12590 #define P_VPU_OSD2_MMC_CTRL (volatile uint32_t *)((0x2702 << 2) + 0xff900000)
12591 #define VPU_VD1_MMC_CTRL (0x2703)
12592 #define P_VPU_VD1_MMC_CTRL (volatile uint32_t *)((0x2703 << 2) + 0xff900000)
12593 #define VPU_VD2_MMC_CTRL (0x2704)
12594 #define P_VPU_VD2_MMC_CTRL (volatile uint32_t *)((0x2704 << 2) + 0xff900000)
12595 #define VPU_DI_IF1_MMC_CTRL (0x2705)
12596 #define P_VPU_DI_IF1_MMC_CTRL (volatile uint32_t *)((0x2705 << 2) + 0xff900000)
12597 #define VPU_DI_MEM_MMC_CTRL (0x2706)
12598 #define P_VPU_DI_MEM_MMC_CTRL (volatile uint32_t *)((0x2706 << 2) + 0xff900000)
12599 #define VPU_DI_INP_MMC_CTRL (0x2707)
12600 #define P_VPU_DI_INP_MMC_CTRL (volatile uint32_t *)((0x2707 << 2) + 0xff900000)
12601 #define VPU_DI_MTNRD_MMC_CTRL (0x2708)
12602 #define P_VPU_DI_MTNRD_MMC_CTRL (volatile uint32_t *)((0x2708 << 2) + 0xff900000)
12603 #define VPU_DI_CHAN2_MMC_CTRL (0x2709)
12604 #define P_VPU_DI_CHAN2_MMC_CTRL (volatile uint32_t *)((0x2709 << 2) + 0xff900000)
12605 #define VPU_DI_MTNWR_MMC_CTRL (0x270a)
12606 #define P_VPU_DI_MTNWR_MMC_CTRL (volatile uint32_t *)((0x270a << 2) + 0xff900000)
12607 #define VPU_DI_NRWR_MMC_CTRL (0x270b)
12608 #define P_VPU_DI_NRWR_MMC_CTRL (volatile uint32_t *)((0x270b << 2) + 0xff900000)
12609 #define VPU_DI_DIWR_MMC_CTRL (0x270c)
12610 #define P_VPU_DI_DIWR_MMC_CTRL (volatile uint32_t *)((0x270c << 2) + 0xff900000)
12611 #define VPU_VDIN0_MMC_CTRL (0x270d)
12612 #define P_VPU_VDIN0_MMC_CTRL (volatile uint32_t *)((0x270d << 2) + 0xff900000)
12613 #define VPU_VDIN1_MMC_CTRL (0x270e)
12614 #define P_VPU_VDIN1_MMC_CTRL (volatile uint32_t *)((0x270e << 2) + 0xff900000)
12615 #define VPU_BT656_MMC_CTRL (0x270f)
12616 #define P_VPU_BT656_MMC_CTRL (volatile uint32_t *)((0x270f << 2) + 0xff900000)
12617 #define VPU_TVD3D_MMC_CTRL (0x2710)
12618 #define P_VPU_TVD3D_MMC_CTRL (volatile uint32_t *)((0x2710 << 2) + 0xff900000)
12619 #define VPU_TVDVBI_MMC_CTRL (0x2711)
12620 #define P_VPU_TVDVBI_MMC_CTRL (volatile uint32_t *)((0x2711 << 2) + 0xff900000)
12621 //Read only
12622 //`define VPU_TVDVBI_VSLATCH_ADDR 8'h12
12623 //Read only
12624 //`define VPU_TVDVBI_WRRSP_ADDR 8'h13
12625 #define VPU_VDIN_PRE_ARB_CTRL (0x2714)
12626 #define P_VPU_VDIN_PRE_ARB_CTRL (volatile uint32_t *)((0x2714 << 2) + 0xff900000)
12627 #define VPU_VDISP_PRE_ARB_CTRL (0x2715)
12628 #define P_VPU_VDISP_PRE_ARB_CTRL (volatile uint32_t *)((0x2715 << 2) + 0xff900000)
12629 #define VPU_VPUARB2_PRE_ARB_CTRL (0x2716)
12630 #define P_VPU_VPUARB2_PRE_ARB_CTRL (volatile uint32_t *)((0x2716 << 2) + 0xff900000)
12631 #define VPU_OSD3_MMC_CTRL (0x2717)
12632 #define P_VPU_OSD3_MMC_CTRL (volatile uint32_t *)((0x2717 << 2) + 0xff900000)
12633 #define VPU_OSD4_MMC_CTRL (0x2718)
12634 #define P_VPU_OSD4_MMC_CTRL (volatile uint32_t *)((0x2718 << 2) + 0xff900000)
12635 #define VPU_VD3_MMC_CTRL (0x2719)
12636 #define P_VPU_VD3_MMC_CTRL (volatile uint32_t *)((0x2719 << 2) + 0xff900000)
12637 // [31:11] Reserved.
12638 // [10: 8] cntl_viu_vdin_sel_data. Select VIU to VDIN data path, must clear it first before changing the path selection:
12639 // 3'b000=Disable VIU to VDIN path;
12640 // 3'b001=Enable VIU of ENC_I domain to VDIN;
12641 // 3'b010=Enable VIU of ENC_P domain to VDIN;
12642 // 3'b100=Enable VIU of ENC_T domain to VDIN;
12643 // [ 6: 4] cntl_viu_vdin_sel_clk. Select which clock to VDIN path, must clear it first before changing the clock:
12644 // 3'b000=Disable VIU to VDIN clock;
12645 // 3'b001=Select encI clock to VDIN;
12646 // 3'b010=Select encP clock to VDIN;
12647 // 3'b100=Select encT clock to VDIN;
12648 // [ 3: 2] cntl_viu2_sel_venc. Select which one of the encI/P/T that VIU2 connects to:
12649 // 0=No connection, 1=ENCI, 2=ENCP, 3=ENCT.
12650 // [ 1: 0] cntl_viu1_sel_venc. Select which one of the encI/P/T that VIU1 connects to:
12651 // 0=No connection, 1=ENCI, 2=ENCP, 3=ENCT.
12652 #define VPU_VIU_VENC_MUX_CTRL (0x271a)
12653 #define P_VPU_VIU_VENC_MUX_CTRL (volatile uint32_t *)((0x271a << 2) + 0xff900000)
12654 // [15:12] rd_rate. 0=A read every clk2; 1=A read every 2 clk2; ...; 15=A read every 16 clk2.
12655 // [11: 8] wr_rate. 0=A write every clk1; 1=A write every 2 clk1; ...; 15=A write every 16 clk1.
12656 // [ 7: 5] data_comp_map. Input data is CrYCb(BRG), map the output data to desired format:
12657 // 0=output CrYCb(BRG);
12658 // 1=output YCbCr(RGB);
12659 // 2=output YCrCb(RBG);
12660 // 3=output CbCrY(GBR);
12661 // 4=output CbYCr(GRB);
12662 // 5=output CrCbY(BGR);
12663 // 6,7=Rsrv.
12664 // [ 4] inv_dvi_clk. 1=Invert clock to external DVI, (clock invertion exists at internal HDMI).
12665 // [ 3] inv_vsync. 1=Invert Vsync polarity.
12666 // [ 2] inv_hsync. 1=Invert Hsync polarity.
12667 // [ 1: 0] src_sel. 0=Disable output to HDMI; 1=Select VENC_I output to HDMI; 2=Select VENC_P output.
12668 #define VPU_HDMI_SETTING (0x271b)
12669 #define P_VPU_HDMI_SETTING (volatile uint32_t *)((0x271b << 2) + 0xff900000)
12670 #define ENCI_INFO_READ (0x271c)
12671 #define P_ENCI_INFO_READ (volatile uint32_t *)((0x271c << 2) + 0xff900000)
12672 #define ENCP_INFO_READ (0x271d)
12673 #define P_ENCP_INFO_READ (volatile uint32_t *)((0x271d << 2) + 0xff900000)
12674 #define ENCT_INFO_READ (0x271e)
12675 #define P_ENCT_INFO_READ (volatile uint32_t *)((0x271e << 2) + 0xff900000)
12676 #define ENCL_INFO_READ (0x271f)
12677 #define P_ENCL_INFO_READ (volatile uint32_t *)((0x271f << 2) + 0xff900000)
12678 // Bit 0 RW, viu_rst_n
12679 // Bit 1 RW, vdin_mmc_arb_rst_n
12680 // Bit 2 RW, vdisp_mmc_arb_rst_n
12681 // Bit 3 RW, vpuarb2_mmc_arb_rst_n
12682 #define VPU_SW_RESET (0x2720)
12683 #define P_VPU_SW_RESET (volatile uint32_t *)((0x2720 << 2) + 0xff900000)
12684 //Bit 30 d2d3_depr_req_sel, 0:vdisp_pre_arb, 1: vpuarb2_pre_arb
12685 //Bit 27:22 d2d3_depr_brst_num
12686 //Bit 21:16 d2d3_depr_id
12687 //Bit 14 d2d3_depw_req_sel, 0: vdin_pre_arb, 1: vdisp_pre_arb
12688 //Bit 11:6 d2d3_depw_brst_num
12689 //Bit 5:0 d2d3_depw_id
12690 #define VPU_D2D3_MMC_CTRL (0x2721)
12691 #define P_VPU_D2D3_MMC_CTRL (volatile uint32_t *)((0x2721 << 2) + 0xff900000)
12692 //Bit 30 mtn_contrd_req_pre, 0:disp1_arb, 1: vdin_pre_arb
12693 //Bit 27:22 mtn_contrd_brst_num
12694 //Bit 21:16 mtn_contrd_id
12695 //Bit 14 mtn_contwr_req_pre, 0: vdisp1_arb, 1: vdin_pre_arb
12696 //Bit 11:6 mtn_contwr_brst_num
12697 //Bit 5:0 mtn_contwr_id
12698 #define VPU_CONT_MMC_CTRL (0x2722)
12699 #define P_VPU_CONT_MMC_CTRL (volatile uint32_t *)((0x2722 << 2) + 0xff900000)
12700 // Bit 6 RW, gclk_mpeg_vpu_misc
12701 // Bit 5 RW, gclk_mpeg_venc_l_top
12702 // Bit 4 RW, gclk_mpeg_vencl_int
12703 // Bit 3 RW, gclk_mpeg_vencp_int
12704 // Bit 2 RW, gclk_mpeg_vi2_top
12705 // Bit 1 RW, gclk_mpeg_vi_top
12706 // Bit 0 RW, gclk_mpeg_venc_p_top
12707 #define VPU_CLK_GATE (0x2723)
12708 #define P_VPU_CLK_GATE (volatile uint32_t *)((0x2723 << 2) + 0xff900000)
12709 //Bit 12 RW, rdma_pre
12710 //Bit 11: 6 RW, rdma_num
12711 //Bit 5: 0 RW, rdma_id
12712 #define VPU_RDMA_MMC_CTRL (0x2724)
12713 #define P_VPU_RDMA_MMC_CTRL (volatile uint32_t *)((0x2724 << 2) + 0xff900000)
12714 #define VPU_MEM_PD_REG0 (0x2725)
12715 #define P_VPU_MEM_PD_REG0 (volatile uint32_t *)((0x2725 << 2) + 0xff900000)
12716 #define VPU_MEM_PD_REG1 (0x2726)
12717 #define P_VPU_MEM_PD_REG1 (volatile uint32_t *)((0x2726 << 2) + 0xff900000)
12718 // [ 31] hdmi_data_ovr_en: 1=Enable overriding data input to HDMI TX with hdmi_data_ovr[29:0]. 0=No override. Default 0.
12719 // [ 30] Reserved. Default 0
12720 // [29: 0] hdmi_data_ovr. Default 0.
12721 #define VPU_HDMI_DATA_OVR (0x2727)
12722 #define P_VPU_HDMI_DATA_OVR (volatile uint32_t *)((0x2727 << 2) + 0xff900000)
12723 //Bit 15 RW, prot1_sel_osd4
12724 //Bit 14 RW, prot1_sel_osd3
12725 //Bit 13 RW, prot1_sel_osd2
12726 //Bit 12 RW, prot1_sel_osd1
12727 //Bit 11: 6 RW, prot1_brst_num
12728 //Bit 5: 0 RW, prot1_id
12729 #define VPU_PROT1_MMC_CTRL (0x2728)
12730 #define P_VPU_PROT1_MMC_CTRL (volatile uint32_t *)((0x2728 << 2) + 0xff900000)
12731 //Bit 14 RW, prot2_sel_vd3
12732 //Bit 13 RW, prot2_sel_vd2
12733 //Bit 12 RW, prot2_sel_vd1
12734 //Bit 11: 6 RW, prot2_brst_num
12735 //Bit 5: 0 RW, prot2_id
12736 #define VPU_PROT2_MMC_CTRL (0x2729)
12737 #define P_VPU_PROT2_MMC_CTRL (volatile uint32_t *)((0x2729 << 2) + 0xff900000)
12738 //Bit 14 RW, prot3_sel_vd3
12739 //Bit 13 RW, prot3_sel_vd2
12740 //Bit 12 RW, prot3_sel_vd1
12741